\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
No Description
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : IP Version
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FREQOFFEST : Frequency offset estimate
bits : 0 - 12 (13 bit)
access : read-only
CORRVAL : Correlation value
bits : 16 - 23 (8 bit)
access : read-only
SOFTVAL : Soft detection value
bits : 24 - 31 (8 bit)
access : read-only
No Description
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTDEMODEN : Viterbi demodulator enable
bits : 0 - 0 (1 bit)
access : read-write
HARDDECISION : Hard decision
bits : 1 - 1 (1 bit)
access : read-write
VITERBIKSI1 : VITERBI KSI1
bits : 2 - 8 (7 bit)
access : read-write
VITERBIKSI2 : VITERBI KSI2
bits : 9 - 15 (7 bit)
access : read-write
VITERBIKSI3 : VITERBI KSI3
bits : 16 - 21 (6 bit)
access : read-write
SYNTHAFC : Synthesizer AFC in Viterbi demod
bits : 22 - 22 (1 bit)
access : read-write
CORRCYCLE : Correction cycles
bits : 23 - 26 (4 bit)
access : read-write
CORRSTPSIZE : Correction step size
bits : 27 - 30 (4 bit)
access : read-write
DISDEMODOF : Disable Demod Over Flow Detection
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXPECTPATT : Expected pattern
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIGMIXFREQ : Digital mixer frequency control word
bits : 0 - 19 (20 bit)
access : read-write
DIGMIXMODE : Digital mixer frequency control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : CFOSR
Mixer frequency specified by CFOSR.
1 : DIGMIXFREQ
Mixer frequency specified by DIGMIXFREQ.
End of enumeration elements list.
MIXERCONJ : Digital mixer input conjugate
bits : 21 - 21 (1 bit)
access : read-write
No Description
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CORRSHFTLEN : Correlator shift length
bits : 0 - 5 (6 bit)
access : read-write
VTFRQLIM : Viterbi frequency limiter
bits : 6 - 14 (9 bit)
access : read-write
EXPSYNCLEN : Expected sync length
bits : 15 - 22 (8 bit)
access : read-write
BUFFHEAD : Buffer header
bits : 23 - 26 (4 bit)
access : read-write
EXPECTHT : Expected patterns head and tail
bits : 27 - 30 (4 bit)
access : read-write
No Description
address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQTRACKMODE : Frequency tracking mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
Frequency tracking disabled. Only a one-time frequency offset compensation applied through DSA.
1 : MODE1
Frequency tracking enabled with one correction, when needed, every 16 symbol periods.
2 : MODE2
Frequency tracking enabled with one correction, when needed, every 32 symbol periods.
3 : MODE3
Frequency tracking enabled with one correction, when needed, every 48 symbol periods.
End of enumeration elements list.
TIMTRACKTHD : Timing tracking threshold
bits : 2 - 5 (4 bit)
access : read-write
TIMEACQUTHD : Time acquisition threshold
bits : 6 - 13 (8 bit)
access : read-write
TIMCHK : Time check
bits : 14 - 14 (1 bit)
access : read-write
TIMEOUTMODE : Timeout mode
bits : 15 - 15 (1 bit)
access : read-write
TIMGEAR : Timing Gear
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : GEAR0
Execute timing tracking regardless of difference between Early/Late and Current correlation values. Referred to as fast gear. Same as GEAR3
1 : GEAR1
Execute timing tracking only when correlation value of Early/Late is 75% or less of the Current correlation value. Referred to as medium gear.
2 : GEAR2
Execute timing tracking only when correlation value of Early/Late is 50% or less of the Current correlation value. Referred to as slow gear.
End of enumeration elements list.
FREQBIAS : Frequency estimation bias
bits : 18 - 21 (4 bit)
access : read-write
HIPWRTHD : High Power detection threshold
bits : 22 - 29 (8 bit)
access : read-write
No Description
address_offset : 0x118 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BRESTINT : Integer part of estimated baudrate
bits : 0 - 5 (6 bit)
access : read-only
BRESTNUM : Fractional part of estimated baudrate
bits : 6 - 10 (5 bit)
access : read-only
No Description
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTOCGEN : Enable automatic clock gating
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FORCEOFF : Manual control clocks
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x12C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
POEI : In-phase component of POE.
bits : 0 - 9 (10 bit)
access : read-only
POEQ : Quadrature component of POE.
bits : 16 - 25 (10 bit)
access : read-only
No Description
address_offset : 0x130 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POWABSTHDLOG : Power threshold in logarithm-scale
bits : 0 - 7 (8 bit)
access : read-write
JUMPDETEN : Power jump detection enable
bits : 9 - 9 (1 bit)
access : read-write
FDADJTHD : Frequency deviation ripple threshold
bits : 10 - 15 (6 bit)
access : read-write
PMDETPASSTHD : DSA Preamble detection counter threshold
bits : 16 - 19 (4 bit)
access : read-write
FREQESTTHD : Frequency Estimation Timeout Threshold
bits : 20 - 24 (5 bit)
access : read-write
INTERFERDET : Interference detection threshold
bits : 25 - 29 (5 bit)
access : read-write
PMDETFORCE : Force DSA preamble detector
bits : 30 - 30 (1 bit)
access : read-write
No Description
address_offset : 0x134 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMENABLE : Enable Direct Mode
bits : 0 - 0 (1 bit)
access : read-write
SYNCASYNC : Choose Synchronous or Asynchronous mode
bits : 1 - 1 (1 bit)
access : read-write
SYNCPREAM : Synchronous mode preamble
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : ADD0
No preamble bits appended
1 : ADD8
8 preamble bits appended
2 : ADD16
16 preamble bits appended
3 : ADD32
32 preamble bits appended
End of enumeration elements list.
CLKWIDTH : Synchronous mode clock pulse width
bits : 8 - 12 (5 bit)
access : read-write
No Description
address_offset : 0x138 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LRCORRTHD : Correlator threshold
bits : 0 - 10 (11 bit)
access : read-write
LRCORRSCHWIN : Window size
bits : 11 - 14 (4 bit)
access : read-write
LRBLE : Enable
bits : 15 - 15 (1 bit)
access : read-write
LRTIMCORRTHD : Correlator threshold
bits : 16 - 26 (11 bit)
access : read-write
LRBLEDSA : DSA enable
bits : 27 - 27 (1 bit)
access : read-write
LRDEC : DEC value
bits : 28 - 30 (3 bit)
access : read-write
LRCORRTHDDYNEN : Correlator THD dynamic enable
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x13C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LRSS : Long Range Signal Selection
bits : 0 - 3 (4 bit)
access : read-write
LRTIMEOUTTHD : Long Range Time Out Threshold
bits : 4 - 14 (11 bit)
access : read-write
CHPWRACCUDEL : Channel Power Accumulated Delay
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : DEL0
Use accumulated channel power value
1 : DEL32
Delayed by 32 chips
2 : DEL64
Delayed by 64 chips
End of enumeration elements list.
HYSVAL : Hysteresis Value for BBSS
bits : 18 - 20 (3 bit)
access : read-write
AVGWIN : Average window
bits : 21 - 23 (3 bit)
access : read-write
LRSPIKETHADD : Long Range DSA spike threshold addition
bits : 24 - 27 (4 bit)
access : read-write
LOGICBASEDPUGATE : Logic Based Phase Unwrap Gating
bits : 28 - 28 (1 bit)
access : read-write
LOGICBASEDLRDEMODGATE : Logic Based Long Range Demod Gating
bits : 29 - 29 (1 bit)
access : read-write
No Description
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AFCADJRX : AFC adjustment for RX
bits : 0 - 18 (19 bit)
access : read-only
No Description
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LRCHPWRTH1 : Long Range channel power threshold
bits : 0 - 7 (8 bit)
access : read-write
LRCHPWRTH2 : Long Range channel power threshold
bits : 8 - 15 (8 bit)
access : read-write
LRCHPWRTH3 : Long Range channel power threshold
bits : 16 - 23 (8 bit)
access : read-write
LRCHPWRTH4 : Long Range channel power threshold
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LRCHPWRTH5 : Long Range channel power threshold
bits : 0 - 7 (8 bit)
access : read-write
LRCHPWRTH6 : Long Range channel power threshold
bits : 8 - 15 (8 bit)
access : read-write
LRCHPWRTH7 : Long Range channel power threshold
bits : 16 - 23 (8 bit)
access : read-write
LRCHPWRTH8 : Long Range channel power threshold
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LRCHPWRTH9 : Long Range channel power threshold
bits : 0 - 7 (8 bit)
access : read-write
LRCHPWRTH10 : Long Range channel power threshold
bits : 8 - 15 (8 bit)
access : read-write
LRCHPWRSH1 : Long Range channel power shift
bits : 16 - 19 (4 bit)
access : read-write
LRCHPWRSH2 : Long Range channel power shift
bits : 20 - 23 (4 bit)
access : read-write
LRCHPWRSH3 : Long Range channel power shift
bits : 24 - 27 (4 bit)
access : read-write
LRCHPWRSH4 : Long Range channel power shift
bits : 28 - 31 (4 bit)
access : read-write
No Description
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LRCHPWRSH5 : Long Range channel power shift
bits : 0 - 3 (4 bit)
access : read-write
LRCHPWRSH6 : Long Range channel power shift
bits : 4 - 7 (4 bit)
access : read-write
LRCHPWRSH7 : Long Range channel power shift
bits : 8 - 11 (4 bit)
access : read-write
LRCHPWRSH8 : Long Range channel power shift
bits : 12 - 15 (4 bit)
access : read-write
LRCHPWRSH9 : Long Range channel power shift
bits : 16 - 19 (4 bit)
access : read-write
LRCHPWRSH10 : Long Range channel power shift
bits : 20 - 23 (4 bit)
access : read-write
LRCHPWRSH11 : Long Range channel power shift
bits : 24 - 27 (4 bit)
access : read-write
No Description
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LRCHPWRSPIKETH : Long Range channel power spike threshold
bits : 0 - 7 (8 bit)
access : read-write
LRSPIKETHD : Long Range spike threshold
bits : 8 - 18 (11 bit)
access : read-write
LRCHPWRTH11 : Long Range channel power threshold
bits : 20 - 27 (8 bit)
access : read-write
LRCHPWRSH12 : Long Range channel power shift
bits : 28 - 31 (4 bit)
access : read-write
No Description
address_offset : 0x154 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CI500 : Long Range CI mapping for 500kbps
bits : 0 - 1 (2 bit)
access : read-write
FRCACKTIMETHD : FRC acknowledge timeout threshold
bits : 2 - 7 (6 bit)
access : read-write
No Description
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COHDYNAMICBBSSEN : Dynamic BBSS enable bit
bits : 0 - 0 (1 bit)
access : read-write
COHDYNAMICSYNCTHRESH : Dynamic syncword threshold enable bit
bits : 1 - 1 (1 bit)
access : read-write
COHDYNAMICPRETHRESH : Dynamic preamble threshold enable bit
bits : 2 - 2 (1 bit)
access : read-write
COHDYNAMICPRETHRESHSEL : Dynamic preamble threshold selection
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
0 : SEL0
1x sync coeff
1 : SEL1
0.94x sync coeff
2 : SEL2
0.88x sync coeff
3 : SEL3
0.74x sync coeff
4 : SEL4
0.5x sync coeff
End of enumeration elements list.
COHCHPWRTH0 : Channel power threshold
bits : 8 - 15 (8 bit)
access : read-write
COHCHPWRTH1 : Channel power threshold
bits : 16 - 23 (8 bit)
access : read-write
COHCHPWRTH2 : Channel power threshold
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCTHRESH0 : Minimum correlation threshold
bits : 0 - 7 (8 bit)
access : read-write
SYNCTHRESH1 : Minimum correlation threshold
bits : 8 - 15 (8 bit)
access : read-write
SYNCTHRESH2 : Minimum correlation threshold
bits : 16 - 23 (8 bit)
access : read-write
SYNCTHRESH3 : Minimum correlation threshold
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCTHRESHDELTA0 : Syncword correlation delta threshold
bits : 0 - 3 (4 bit)
access : read-write
SYNCTHRESHDELTA1 : Syncword correlation delta threshold
bits : 4 - 7 (4 bit)
access : read-write
SYNCTHRESHDELTA2 : Syncword correlation delta threshold
bits : 8 - 11 (4 bit)
access : read-write
SYNCTHRESHDELTA3 : Syncword correlation delta threshold
bits : 12 - 15 (4 bit)
access : read-write
DSAPEAKCHPWRTH : DSA Peak Check CHpwr Threshold
bits : 16 - 23 (8 bit)
access : read-write
FIXEDCDTHFORIIR : .
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0x164 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COHDSAEN : DSA enable bit
bits : 0 - 0 (1 bit)
access : read-write
COHDSAADDWNDSIZE : DSA additional window size
bits : 1 - 10 (10 bit)
access : read-write
CDSS : DSA Signal Selection
bits : 11 - 13 (3 bit)
access : read-write
DSAPEAKCHKEN : DSA Peak Checking Enable
bits : 14 - 14 (1 bit)
access : read-write
DSAPEAKINDLEN : DSA Peak Index length
bits : 15 - 17 (3 bit)
access : read-write
DSAPEAKCHPWREN : DSA Peak Check channel power enable
bits : 18 - 18 (1 bit)
access : read-write
LOGICBASEDCOHDEMODGATE : Logic Based clock gate
bits : 19 - 19 (1 bit)
access : read-write
DYNIIRCOEFOPTION : Dynamic IIR
bits : 20 - 21 (2 bit)
access : read-write
ONEPEAKQUALEN : One Peak
bits : 22 - 22 (1 bit)
access : read-write
PEAKCHKTIMOUT : Peak Check Time Out
bits : 23 - 27 (5 bit)
access : read-write
COHDSADETDIS : DSA Detection Disable
bits : 28 - 28 (1 bit)
access : read-write
No Description
address_offset : 0x168 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIKETHDLO : Spike threshold
bits : 0 - 7 (8 bit)
access : read-write
UNMODTHDLO : Unmodulated carrier detector threshold
bits : 8 - 13 (6 bit)
access : read-write
FDEVMINTHDLO : Frequency deviation minimum threshold
bits : 14 - 19 (6 bit)
access : read-write
FDEVMAXTHDLO : Frequency deviation maximum threshold
bits : 20 - 31 (12 bit)
access : read-write
No Description
address_offset : 0x16C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POWABSTHDLO : Power absolute threshold for low power
bits : 0 - 15 (16 bit)
access : read-write
ARRTOLERTHD0LO : Arrival tolerance threshold 0
bits : 16 - 20 (5 bit)
access : read-write
ARRTOLERTHD1LO : Arrival tolerance threshold 1
bits : 21 - 25 (5 bit)
access : read-write
SWTHD : Enable switch threshold for low power
bits : 26 - 26 (1 bit)
access : read-write
No Description
address_offset : 0x170 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTBLETIMINGSEL : Viterbi BLE timing stamp selection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : FRAMEDET_DELAY
Delayed frame detection will be used as Timing stamp. This mode should be selected for legacy demod and Long Range BLE demod.
1 : END_FRAME_PULSE
The end of frame detection from Narrow Viterbi demod will be used as Timing stamp. This signal is a narrow pulse signal and pulse width is one xo clock cycle.
2 : END_FRAME
The end of frame detection from Narrow Viterbi demod will be used as Timing stamp. This signal is a wdie pulse signal
3 : INV_END_FRAME
For testing only.
End of enumeration elements list.
TIMINGDELAY : Viterbi BLE Delay timer
bits : 4 - 11 (8 bit)
access : read-write
FLENOFF : Timing Stamp Frame Length Offset
bits : 12 - 15 (4 bit)
access : read-write
No Description
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AFCADJTX : AFC adjustment for TX
bits : 0 - 18 (19 bit)
access : read-only
No Description
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANAMIXMODE : Analog receiver mixer mode of operation
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : NORMAL
The analog mixer operates in its normal mode
1 : IPQPIQSWAP
I path is positive, Q path is positive, I and Q are swapped
2 : IPQN
I path is positive, Q path is negative
3 : IPQNIQSWAP
I path is positive, Q path is negative, I and Q are swapped
4 : INQP
I path is negative, Q path is positive
5 : INQPIQSWAP
I path is negative, Q path is positive, I and Q are swapped
6 : INQN
I path is negative, Q path is negative
7 : INQNIQSWAP
I path is negative, Q path is negative, I and Q are swapped
8 : UPCONVERT
Control the analog receiver mixer such that the analog mixer performs a digital up-conversion on the mixer output, with the frequency set by the DEC0 and CFOSR settings. This mode may be used to perform RF loopback using the normal synthesizer both for transmit and receive, and still get a positive IF frequency on the IF receive signal.
9 : DOWNCONVERT
Control the analog receiver mixer such that the analog mixer performs a digital down-conversion on the mixer output, with the frequency set by the DEC0 and CFOSR settings.
End of enumeration elements list.
DIGIQSWAPEN : Digital I/Q swap enable
bits : 4 - 4 (1 bit)
access : read-write
No Description
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FDM0DIFFDIS : Frame Detection Mode 0 disable
bits : 0 - 0 (1 bit)
access : read-write
MAPFSK : Mapping of FSK symbols
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
0 : MAP0
4FSK: Symbol 11, 10, 00, 01 for decreasing frequency. 2FSK/MSK/ASK/OOK: Symbol 1 is high/positive frequency or high amplitude, symbol 0 is low/negative frequency or low amplitude.
1 : MAP1
4FSK: Symbol 01, 00, 10, 11 for decreasing frequency. 2FSK/MSK/ASK/OOK: Symbol 0 is high/negative frequency or high amplitude, symbol 1 is low/negative frequency or low amplitude.
2 : MAP2
4FSK: Symbol 10, 11, 01, 00 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined.
3 : MAP3
4FSK: Symbol 00, 01, 11, 10 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined.
4 : MAP4
4FSK: Symbol 11, 01, 00, 10 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined.
5 : MAP5
4FSK: Symbol 10, 00, 01, 11 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined.
6 : MAP6
4FSK: Symbol 01, 11, 10, 00 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined.
7 : MAP7
4FSK: Symbol 00, 10, 11, 01 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined.
End of enumeration elements list.
CODING : Symbol coding
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : NRZ
Non Return to Zero
1 : MANCHESTER
Manchester Coding
2 : DSSS
Direct Sequence Spread Spectrum
3 : LINECODE
Line code. Maps 0 to 0011 symbol and 1 to 1100 symbols
End of enumeration elements list.
MODFORMAT : Modulation format
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : FSK2
Frequency Shift Keying with 2 symbols
1 : FSK4
Frequency Shift Keying with 4 symbols
2 : BPSK
Binary Phase Shift Keying
3 : DBPSK
Differentially encoded Binary Phase Shift Keying
4 : OQPSK
Half Sine Shaped Offset Quadrature Phase Shift Keying
5 : MSK
Minimum Shift Keying
6 : OOKASK
On Off Keying and Amplitude Shift Keying
End of enumeration elements list.
DUALCORROPTDIS : Dual Correlation Optimization Disable
bits : 9 - 9 (1 bit)
access : read-write
OOKASYNCPIN : OOK asynchronous pin mode
bits : 10 - 10 (1 bit)
access : read-write
DSSSLEN : DSSS length
bits : 11 - 15 (5 bit)
access : read-write
DSSSSHIFTS : DSSS shifts
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : NOSHIFT
No symbols are defined by shifting.
1 : SHIFT1
Next symbol generated by 1 cyclic shift.
2 : SHIFT2
Next symbol generated by 2 cyclic shifts.
3 : SHIFT4
Next symbol generated by 4 cyclic shifts.
4 : SHIFT8
Next symbol generated by 8 cyclic shifts.
5 : SHIFT16
Next symbol generated by 16 cyclic shifts.
End of enumeration elements list.
DSSSDOUBLE : DSSS double
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
0 : DIS
Doubling is disabled.
1 : INV
Doubling is enabled by using inverted symbols.
2 : CONJ
Doubling is enabled by using complex conjugated symbols.
End of enumeration elements list.
DETDIS : Detection disable
bits : 21 - 21 (1 bit)
access : read-write
DIFFENCMODE : Differential encoding mode
bits : 22 - 24 (3 bit)
access : read-write
Enumeration:
0 : DIS
Differential Encoding is disabled.
1 : RR0
Transmit the XOR-ed value of the Raw symbol and the last Raw symbol. Initial Raw symbol is 0.
2 : RE0
Transmit the XOR-ed value of the Raw symbol and the last Encoded symbol. Initial Encoded symbol is 0.
3 : RR1
Transmit the XOR-ed value of the Raw symbol and the last Raw symbol. Initial Raw symbol is 1.
4 : RE1
Transmit the XOR-ed value of the Raw symbol and the last Encoded symbol. Initial Encoded symbol is 1.
End of enumeration elements list.
SHAPING : Shaping filter
bits : 25 - 26 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
Filter disabled.
1 : ODDLENGTH
Filter has odd length. Filter uses coefficients 0,1,2,3,4,5,6,7,8,7,6,5,4,3,2,1,0.
2 : EVENLENGTH
Filter has even length. Filter uses coefficients 0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0.
3 : ASYMMETRIC
Filter has asymmetrical coefficients. Filter uses coefficients 0,1,2,3,4,5,6,7.
End of enumeration elements list.
DEMODRAWDATASEL : Demod raw data select
bits : 27 - 29 (3 bit)
access : read-write
Enumeration:
0 : DIS
Disabled.
1 : ENTROPY
1-bit entropy source extracted from the RF receive chain, to be used for random number generation.
2 : ADC
2 * 3-bit I and Q ADC data.
3 : FILTLSB
2 * 16-bit I and Q channel filtered data downmixed to zero-IF. The receive signal chain has 19 bits dynamic range at this point, and the FILTLSB setting outputs the 16 least significant bits (with saturation).
4 : FILTMSB
2 * 16-bit I and Q channel filtered data downmixed to zero-IF. The receive signal chain has 19 bits dynamic range at this point, and the FILTMSB setting outputs the 16 most significant bits (with truncation).
5 : FILTFULL
2 * 19-bit I and Q channel filtered data downmixed to zero-IF. The FILTFULL option will output all 19 bits of dynamic range, sign extended to 32 bits.
6 : FREQ
8-bit received frequency data (or logarithmic amplitude for ASK/OOK).
7 : DEMOD
8-bit demodulated data (freq/amp/phase). When coherent detection is enabled, only the in-phase component is selected.
End of enumeration elements list.
FRAMEDETDEL : FRAMEDET delay
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : DEL0
No delay
1 : DEL8
8 baud delay
2 : DEL16
16 baud delay
3 : DEL32
32 baud delay
End of enumeration elements list.
No Description
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXFRAMESENT : Frame sent
bits : 0 - 0 (1 bit)
access : read-write
TXSYNCSENT : Sync word sent
bits : 1 - 1 (1 bit)
access : read-write
TXPRESENT : Preamble sent
bits : 2 - 2 (1 bit)
access : read-write
RXTIMDET : Timing detected
bits : 8 - 8 (1 bit)
access : read-write
RXPREDET : Preamble detected
bits : 9 - 9 (1 bit)
access : read-write
RXFRAMEDET0 : Frame with sync-word 0 detected
bits : 10 - 10 (1 bit)
access : read-write
RXFRAMEDET1 : Frame with sync-word 1 detected
bits : 11 - 11 (1 bit)
access : read-write
RXTIMLOST : Timing lost
bits : 12 - 12 (1 bit)
access : read-write
RXPRELOST : Preamble lost
bits : 13 - 13 (1 bit)
access : read-write
RXFRAMEDETOF : Frame detection overflow
bits : 14 - 14 (1 bit)
access : read-write
RXTIMNF : Timing not found
bits : 15 - 15 (1 bit)
access : read-write
FRCTIMOUT : DEMOD-FRC req/ack timeout
bits : 16 - 16 (1 bit)
access : read-write
No Description
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXFRAMESENT : Frame sent
bits : 0 - 0 (1 bit)
access : read-write
TXSYNCSENT : Sync word sent
bits : 1 - 1 (1 bit)
access : read-write
TXPRESENT : Preamble sent
bits : 2 - 2 (1 bit)
access : read-write
RXTIMDET : Timing detected
bits : 8 - 8 (1 bit)
access : read-write
RXPREDET : Preamble detected
bits : 9 - 9 (1 bit)
access : read-write
RXFRAMEDET0 : Frame with sync-word 0 detected
bits : 10 - 10 (1 bit)
access : read-write
RXFRAMEDET1 : Frame with sync-word 1 detected
bits : 11 - 11 (1 bit)
access : read-write
RXTIMLOST : Timing lost
bits : 12 - 12 (1 bit)
access : read-write
RXPRELOST : Preamble lost
bits : 13 - 13 (1 bit)
access : read-write
RXFRAMEDETOF : Frame detection overflow
bits : 14 - 14 (1 bit)
access : read-write
RXTIMNF : Timing not found
bits : 15 - 15 (1 bit)
access : read-write
FRCTIMOUT : DEMOD-FRC req/ack timeout
bits : 16 - 16 (1 bit)
access : read-write
No Description
address_offset : 0x218 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PRESTOP : Preamble stop
bits : 0 - 0 (1 bit)
access : write-only
AFCTXLOCK : Lock AFC TX compensation
bits : 3 - 3 (1 bit)
access : write-only
AFCTXCLEAR : Clear AFC TX compensation.
bits : 4 - 4 (1 bit)
access : write-only
AFCRXCLEAR : Clear AFC RX compensation.
bits : 5 - 5 (1 bit)
access : write-only
No Description
address_offset : 0x21C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DETSTATE : Detection FSM state
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
0 : OFF
Off state
10 : TIMINGSEARCH
Timing search
20 : PRESEARCH
Preamble search
30 : FRAMESEARCH
Frame search
40 : RXFRAME
Payload Detection
50 : FRAMEDETMODE0
Timing search with sliding window (FDM0)
End of enumeration elements list.
DSASTATE : Demodulator DSA FSM state
bits : 7 - 9 (3 bit)
access : read-only
Enumeration:
0 : IDLE
IDLE state
1 : ARRIVALCHK
Arrival Check
2 : STATUSCHK
Status Check
3 : SAMPPW
SAMP_PW
4 : WAITPWRUP
WAIT_PWRUP
5 : WAITDSALO
WAIT_DSALO
6 : WAITABORT
WAIT_ABORT
7 : STOP
STOP
End of enumeration elements list.
LRBLESTATE : Demodulator long-range BLE FSM state
bits : 10 - 14 (5 bit)
access : read-only
Enumeration:
0 : IDLE
IDLE state
1 : CLEANUP
CLEANUP
2 : CORRCOE
CORRCOE
3 : WAITLRDSA
WAIT_LR_DSA
4 : MAXCORR
MAXCORR
5 : WAITRDY
WAIT_RDY
6 : FEC1DATA
FEC1_DATA
7 : FEC1ACK
FEC1_ACK
8 : PAUSE
PAUSE
9 : FEC2DATA
FEC2_DATA
10 : FEC2ACK
FEC2_ACK
11 : TRACKCUR
TRACK_CUR
12 : TRACKEAR
TRACK_EAR
13 : TRACKLAT
TRACK_LAT
14 : TRACKDONE
TRACK_DONE
15 : TDECISION
T_DECISION
16 : STOP
STOP
End of enumeration elements list.
NBBLESTATE : Demodulator Narrow-band BLE FSM state
bits : 15 - 19 (5 bit)
access : read-only
Enumeration:
0 : IDLE
IDLE state
1 : VTINITI
VTINITI
2 : ADDRNXT
ADDR_NXT
3 : INICOST
INI_COST
4 : CALCCOST
CALC_COST
5 : INITALACQU
INITAL_ACQU
6 : INITALCOSTCALC
INITAL_COST_CALC
7 : MINCOSTCALC
MIN_COST_CALC
8 : FREQACQU
FREQ_ACQU
9 : FREQACQUDONE
FREQ_ACQU_DONE
10 : TIMINGACQUEARLY
TIMING_ACQU_EARLY
11 : TIMINGACQUCURR
TIMING_ACQU_CURR
12 : TIMINGACQULATE
TIMING_ACQU_LATE
13 : TIMINGACQUDONE
TIMING_ACQU_DONE
14 : VIRTBIINIT0
VIRTBI_INIT0
15 : VIRTBIINIT1
VIRTBI_INIT1
16 : VIRTBIRXSYNC
VIRTBI_RXSYNC
17 : VIRTBIRXPAYLOAD
VIRTBI_RXPAYLOAD
18 : HARDRXSYNC
HARD_RXSYNC
19 : HARDXPAYLOAD
HARD_RXPAYLOAD
20 : TRACKFREQ
TRACK_FREQ
21 : TRACKTIMEARLY
TRACK_TIM_EARLY
22 : TRACKTIMCURR
TRACK_TIM_CURR
23 : TRACKTIMLATE
TRACK_TIM_LATE
24 : TRACKDONE
TRACK_DONE
25 : TRACKDECISION
TRACK_DECISION
26 : STOP
STOP
27 : WAITACK
WAIT_ACK
28 : DEBUG
DEBUG
End of enumeration elements list.
No Description
address_offset : 0x220 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHPWRACCUMUX : Channel power
bits : 0 - 7 (8 bit)
access : read-only
BBSSMUX : Actual Baseband Signal Selection
bits : 8 - 11 (4 bit)
access : read-only
LRBLECI : RXed packet's LR BLE coding indicator
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0 : LR125k
FEC block 2 coded using C=8, 125kbps
1 : LR500k
FEC block 2 coded using C=2, 500kbps
End of enumeration elements list.
No Description
address_offset : 0x224 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BBPFOUTABS1 : Pre-filter Correlation Output
bits : 0 - 10 (11 bit)
access : read-only
BBPFOUTABS : Pre-filter Correlation Output for BLR
bits : 11 - 21 (11 bit)
access : read-only
LRDSALIVE : BLRDSA Prefilter above LRSPIKETHD
bits : 22 - 22 (1 bit)
access : read-only
COHDSALIVE : COHDSA Prefilter above CDTH
bits : 23 - 23 (1 bit)
access : read-only
LRDSADET : DSA prefilter above LRSPIKETHD
bits : 24 - 24 (1 bit)
access : read-only
COHDSADET : DSA prefilter above CDTH
bits : 25 - 25 (1 bit)
access : read-only
SYNCSECPEAKABTH : SYNC second peak above threshold
bits : 26 - 26 (1 bit)
access : read-only
No Description
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRCALEN : IRCAL enable bit
bits : 0 - 0 (1 bit)
access : read-write
MURSHF : MUR shift value
bits : 1 - 5 (5 bit)
access : read-write
MUISHF : MUI shift value
bits : 7 - 12 (6 bit)
access : read-write
IRCORREN : IR Correction enable bit
bits : 13 - 13 (1 bit)
access : read-write
No Description
address_offset : 0x22C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRV : CRV coefficient
bits : 0 - 14 (15 bit)
access : read-only
CIV : CIV coefficient
bits : 16 - 30 (15 bit)
access : read-only
No Description
address_offset : 0x230 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLEIQDSAEN : BLEIQDSA Enable
bits : 0 - 0 (1 bit)
access : read-write
BLEIQDSATH : BLEIQDSA Threshold
bits : 1 - 14 (14 bit)
access : read-write
BLEIQDSAIIRCOEFPWR : BLEIQDSA IIRCOEFPWR
bits : 15 - 17 (3 bit)
access : read-write
BLEIQDSADIFFTH1 : BLEIQDSA BLEIQDSADIFFTH1
bits : 18 - 31 (14 bit)
access : read-write
No Description
address_offset : 0x234 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQSCALEIQDSA : I/Q DSA Frequency scale
bits : 0 - 1 (2 bit)
access : read-write
CHPWRFIRAVGEN : Channel Power FIR Avg Enable
bits : 2 - 2 (1 bit)
access : read-write
CHPWRFIRAVGVAL : Channel Power FIR Avg Value
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : AVG0
No Avg
1 : AVG2
2 sample avg
2 : AVG4
4 sample avg
3 : AVG8
8 sample avg
End of enumeration elements list.
CORRIIRAVGMULFACT : Corr IIR Avg Multiplication Factor
bits : 5 - 6 (2 bit)
access : read-write
BLEIQDSAADDRBIAS : BLEIQDSA ADDRBIAS
bits : 7 - 10 (4 bit)
access : read-write
BLEIQDSATHCOMB : Threshold when i and q are added
bits : 11 - 24 (14 bit)
access : read-write
MAXCORRCNTIQDSA : Max Corr Cnt IQDSA
bits : 25 - 28 (4 bit)
access : read-write
IIRRST : IIR Reset
bits : 29 - 29 (1 bit)
access : read-write
No Description
address_offset : 0x238 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCCORRCLR : Sync auto corr clear bit
bits : 0 - 0 (1 bit)
access : read-write
SYNCSECPEAKTH : SYNC auto corr second peak threshold
bits : 1 - 7 (7 bit)
access : read-write
No Description
address_offset : 0x23C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIGIGAINEN : Digital Gain Enable
bits : 0 - 0 (1 bit)
access : read-write
DIGIGAINSEL : Digital Gain Select
bits : 1 - 5 (5 bit)
access : read-write
Enumeration:
0 : GAINM3
GAINM3
1 : GAINM2P75
GAINM2P75
2 : GAINM2P5
GAINM2P5
3 : GAINM2P25
GAINM2P25
4 : GAINM2
GAINM2
5 : GAINM1P75
GAINM1P75
6 : GAINM1P5
GAINM1P5
7 : GAINM1P25
GAINM1P25
8 : GAINM1
GAINM1
9 : GAINM0P75
GAINM0P75
10 : GAINM0P5
GAINM0P5
11 : GAINM0P25
GAINM0P25
12 : GAINM0
GAINM0
13 : GAINP0P25
GAINP0P25
14 : GAINP0P5
GAINP0P5
15 : GAINP0P75
GAINP0P75
16 : GAINP1
GAINP1
17 : GAINP1P25
GAINP1P25
18 : GAINP1P5
GAINP1P5
19 : GAINP1P75
GAINP1P75
20 : GAINP2
GAINP2
21 : GAINP2P25
GAINP2P25
22 : GAINP2P5
GAINP2P5
23 : GAINP2P75
GAINP2P75
24 : GAINP3
GAINP3
End of enumeration elements list.
DIGIGAINDOUBLE : Digital Gain Doubled
bits : 6 - 6 (1 bit)
access : read-write
DIGIGAINHALF : Digital Gain Halved
bits : 7 - 7 (1 bit)
access : read-write
DEC0GAIN : DEC0 Gain Select
bits : 8 - 8 (1 bit)
access : read-write
No Description
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCBITS : Number of sync-word bits
bits : 0 - 4 (5 bit)
access : read-write
SYNCERRORS : Maximum number of sync errors
bits : 5 - 8 (4 bit)
access : read-write
DUALSYNC : Dual sync words.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Demodulator only searches for SYNC0.
1 : ENABLED
Demodulator searches for SYNC0 and SYNC1 in parallel.
End of enumeration elements list.
TXSYNC : Transmit sync word.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : SYNC0
Modulator transmits SYNC0.
1 : SYNC1
Modulator transmits SYNC1.
End of enumeration elements list.
SYNCDATA : Sync data.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
SYNC is not part of transmit payload. Modulator adds SYNC in transmit.
1 : ENABLED
SYNC is part of transmit payload. Modulator does not add SYNC in transmit.
End of enumeration elements list.
SYNC1INV : SYNC1 invert.
bits : 12 - 12 (1 bit)
access : read-write
COMPMODE : Compensation mode
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : DIS
Compensation is disabled.
1 : PRELOCK
Compensation locks when preamble is detected.
2 : FRAMELOCK
Compensation locks when frame is detected.
3 : NOLOCK
Compensation is always running
End of enumeration elements list.
RESYNCPER : Resync period
bits : 16 - 19 (4 bit)
access : read-write
PHASEDEMOD : Phase demodulation
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : BDD
Bit Differential Detection.
1 : MBDD
Multibit Differential Detection.
2 : COH
Coherent Detection.
End of enumeration elements list.
FREQOFFESTPER : Frequency offset estimation period
bits : 22 - 24 (3 bit)
access : read-write
FREQOFFESTLIM : Frequency offset limit
bits : 25 - 31 (7 bit)
access : read-write
No Description
address_offset : 0x240 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSTPONESEL : None
bits : 0 - 1 (2 bit)
access : read-write
ADVANCESEL : None
bits : 2 - 3 (2 bit)
access : read-write
NEWWNDSEL : None
bits : 4 - 5 (2 bit)
access : read-write
WEAKSEL : None
bits : 6 - 7 (2 bit)
access : read-write
SYNCSENTSEL : None
bits : 8 - 9 (2 bit)
access : read-write
PRESENTSEL : None
bits : 10 - 11 (2 bit)
access : read-write
LOWCORRSEL : None
bits : 12 - 13 (2 bit)
access : read-write
ANT0SEL : None
bits : 14 - 15 (2 bit)
access : read-write
ANT1SEL : None
bits : 16 - 17 (2 bit)
access : read-write
No Description
address_offset : 0x250 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRVWD : CRV coefficient
bits : 0 - 14 (15 bit)
access : read-write
CRVWEN : CIV Coefficient Write Enable
bits : 15 - 15 (1 bit)
access : read-write
CIVWD : CIV coefficient
bits : 16 - 30 (15 bit)
access : read-write
CIVWEN : CIV Coefficient Write Enable
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x254 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRVWD : CRV coefficient
bits : 0 - 14 (15 bit)
access : read-write
CRVWEN : CIV Coefficient Write Enable
bits : 15 - 15 (1 bit)
access : read-write
CIVWD : CIV coefficient
bits : 16 - 30 (15 bit)
access : read-write
CIVWEN : CIV Coefficient Write Enable
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQITHRESH : Signal Quality Indicator threshold
bits : 0 - 7 (8 bit)
access : read-write
RXFRCDIS : Receive FRC disable
bits : 8 - 8 (1 bit)
access : read-write
RXPINMODE : Receive pin mode
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SYNCHRONOUS
Detected payload bits are clocked out on DOUT. Only setups with 1 bit per symbol are supported.
1 : ASYNCHRONOUS
DOUT is continuously providing the sign of the detected frequency deviation before offset compensation. Only 2/4-FSK is supported.
End of enumeration elements list.
TXPINMODE : Transmit pin mode
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : OFF
Pinmode is turned off. Data is gathered from FRC. DOUT/DCLK clocks out transmitted data.
1 : UNUSED
Unused mode
2 : ASYNCHRONOUS
DIN/PRS controls transmitted baud directly. DCLK is set to 0. No support for frame handling nor coding. Only 2-FSK and OOK/ASK can be used.
3 : SYNCHRONOUS
DIN/PRS is sampled on the rising edge of DCLK and used as payload. Frame handling and coding is supported. Only setups with 1 bit per symbol is supported.
End of enumeration elements list.
DATAFILTER : Datafilter
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : DISABLED
Datafilter disabled
1 : SHORT
Short datafilter enabled. 2*RXBRFRAC should be more than 3.
2 : MEDIUM
Medium datafilter enabled. 2*RXBRFRAC should be more than 4.
3 : LONG
Long datafilter enabled. 2*RXBRFRAC should be more than 5.
4 : LEN6
Datafilter with length 6 enabled. 2*RXBRFRAC should be more than 6.
5 : LEN7
Datafilter with length 7 enabled. 2*RXBRFRAC should be more than 7.
6 : LEN8
Datafilter with length 8 enabled. 2*RXBRFRAC should be more than 8.
7 : LEN9
Datafilter with length 9 enabled. 2*RXBRFRAC should be more than 9.
End of enumeration elements list.
BRDIVA : Baudrate division factor A
bits : 15 - 18 (4 bit)
access : read-write
BRDIVB : Baudrate division factor B
bits : 19 - 22 (4 bit)
access : read-write
DEVMULA : Deviation multiplication factor A
bits : 23 - 24 (2 bit)
access : read-write
DEVMULB : Deviation multiplication factor B
bits : 25 - 26 (2 bit)
access : read-write
RATESELMODE : Rate select mode
bits : 27 - 28 (2 bit)
access : read-write
Enumeration:
0 : NOCHANGE
No rate change. BRDIVA/DEVMULA is used for entire frame.
1 : PAYLOAD
Change rate for payload. BRDIVA/DEVMULA is used for header and BRDIVB/DEVMULB is used for payload.
2 : FRC
FRC selects between BRDIVA/DEVMULA and BRDIVB/DEVMULB for each symbol in the payload. Header uses BRDIVA/DEVMULA.
3 : SYNC
The configured/detected syncword decides the settings used for the payload. SYNC0 uses BRDIVA/DEVMULA and SYNC1 uses BRDIVB/DEVMULB. Header uses BRDIVA/DEVMULA.
End of enumeration elements list.
DEVWEIGHTDIS : Deviation weighting disable.
bits : 29 - 29 (1 bit)
access : read-write
DMASEL : DMA select.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : SOFT
SOFTVAL field
1 : CORR
CORRVAL field
2 : FREQOFFEST
FREQOFFEST field
3 : POE
POE field
End of enumeration elements list.
No Description
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSDINEN : DIN PRS enable
bits : 0 - 0 (1 bit)
access : read-write
ANTDIVMODE : Antenna Diversity mode
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : ANTENNA0
Antenna 0 (ANT0=1, ANT1=0) is used
1 : ANTENNA1
Antenna 1 (ANT0=0, ANT1=1) is used
2 : ANTSELFIRST
Select-First algorithm.
3 : ANTSELCORR
Select-Best algorithm based on correlation value.
4 : ANTSELRSSI
Select-Best algorithm based on RSSI value.
End of enumeration elements list.
ANTDIVREPEATDIS : Antenna diversity repeat disable
bits : 11 - 11 (1 bit)
access : read-write
TSAMPMODE : Timing Search Amplitude Mode
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : OFF
Amplitude is not used during timing search.
1 : ON
Timing detection is disabled for windows where at least one sample is below limit set by TSAMPLIM.
2 : DIFF
Timing detection is disabled for windows where the difference between samples is higher than the limit set by TSAMPLIM.
End of enumeration elements list.
TSAMPDEL : Timing Search Amplitude delay
bits : 14 - 15 (2 bit)
access : read-write
TSAMPLIM : Timing Search Amplitude limit
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISICOMP : Inter Symbol Interference compensation
bits : 0 - 3 (4 bit)
access : read-write
DEVOFFCOMP : Deviation offset compensation
bits : 4 - 4 (1 bit)
access : read-write
PREDISTGAIN : Predistortion gain
bits : 5 - 9 (5 bit)
access : read-write
PREDISTDEB : Predistortion debounce
bits : 10 - 12 (3 bit)
access : read-write
PREDISTAVG : Predistortion Average
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : AVG8
Average over 8 samples.
1 : AVG16
Average over 16 samples.
End of enumeration elements list.
PREDISTRST : Predistortion Reset
bits : 14 - 14 (1 bit)
access : read-write
PHASECLICKFILT : Phase click filter
bits : 15 - 21 (7 bit)
access : read-write
SOFTDSSSMODE : Soft DSSS mode
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : CORR0INV
Soft value is inverted value of symbol-0 correlation value.
1 : CORRDIFF
Soft value is difference between correlation values for symbol-0 and symbol-1.
End of enumeration elements list.
ADCSATLEVEL : ADC Saturation Level setting
bits : 23 - 25 (3 bit)
access : read-write
Enumeration:
0 : CONS1
AGC enters fast loop after first saturation sample.
1 : CONS2
2 saturation samples required before AGC enters fast loop.
2 : CONS4
4 saturation samples required before AGC enters fast loop.
3 : CONS8
8 saturation samples required before AGC enters fast loop.
4 : CONS16
16 saturation samples required before AGC enters fast loop.
5 : CONS32
32 saturation samples required before AGC enters fast loop.
6 : CONS64
64 saturation samples required before AGC enters fast loop.
End of enumeration elements list.
ADCSATDENS : ADC Saturation Density setting
bits : 26 - 27 (2 bit)
access : read-write
OFFSETPHASEMASKING : Offset phase masking
bits : 28 - 28 (1 bit)
access : read-write
OFFSETPHASESCALING : Offset phase scaling
bits : 29 - 29 (1 bit)
access : read-write
No Description
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRCALEN : Baudrate calibration enable
bits : 1 - 1 (1 bit)
access : read-write
BRCALMODE : Baudrate calibration mode
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : PEAK
Measure period between peaks in demodulated signal. This mode can give false peaks for high oversampling ratios without sufficient datafiltering.
1 : ZERO
Measure period between zero-crossings in demodulated signal. This mode can miss zero-crossings for high frequency offsets.
2 : PEAKZERO
Combine peak-period and zero-crossing periods. This mode gives best accuracy, but includes weaknesses from both PEAK and ZERO modes.
End of enumeration elements list.
BRCALAVG : Baudrate calibration averaging
bits : 4 - 5 (2 bit)
access : read-write
DETDEL : Detection delay
bits : 6 - 8 (3 bit)
access : read-write
TDEDGE : Timing detection edge mode
bits : 9 - 9 (1 bit)
access : read-write
TREDGE : Timing resynchronization edge mode
bits : 10 - 10 (1 bit)
access : read-write
DSSSCTD : DSSS Correlation Threshold Disable
bits : 11 - 11 (1 bit)
access : read-write
BBSS : Baseband Signal Selection
bits : 12 - 15 (4 bit)
access : read-write
POEPER : Phase Offset Estimation Period
bits : 16 - 19 (4 bit)
access : read-write
DEMODRAWDATASEL2 : Demod raw data select 2
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : DIS
Disabled.
1 : COH
Coherent demod 5-bit I and Q input data, 10-bit I and Q data after FOE/POE.
2 : CORR
4-bit max_corr_index and 17-bit max_corr .
3 : CHPW
8-bit channel power and 4-bit BBSSMUX
4 : BBPF
11-bit pre-filter correlation output for BLR and 11-bit pre-filter correlation output for COH demod
5 : FSM
5-bit Narrow-band BLE FSM state, 5-bit Long-range BLE FSM state, 3-bit DSA FSM state, 7-bit Detection FSM State. Captured each time state changes
End of enumeration elements list.
FOEPREAVG : Frequency Offset Estimate Pre-Averaging
bits : 24 - 26 (3 bit)
access : read-write
LINCORR : Linear Correlation
bits : 27 - 27 (1 bit)
access : read-write
RESYNCBAUDTRANS : Resynchronization Baud Transitions
bits : 29 - 29 (1 bit)
access : read-write
RESYNCLIMIT : Resynchronization Limit
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : HALF
Adjust timing if accumulated timing is higher/lower than RESYNCPER/2.
1 : ALWAYS
Adjust timing if accumulated timing is non-zero.
End of enumeration elements list.
No Description
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDREW : Timing Detection Rewind
bits : 0 - 6 (7 bit)
access : read-write
PREBASES : Preamble Bases
bits : 7 - 10 (4 bit)
access : read-write
PSTIMABORT0 : Preamble Search Timing Abort Criteria 0
bits : 11 - 11 (1 bit)
access : read-write
PSTIMABORT1 : Preamble Search Timing Abort Criteria 1
bits : 12 - 12 (1 bit)
access : read-write
PSTIMABORT2 : Preamble Search Timing Abort Criteria 2
bits : 13 - 13 (1 bit)
access : read-write
PSTIMABORT3 : Preamble Search Timing Abort Criteria 3
bits : 14 - 14 (1 bit)
access : read-write
ARW : Allow Received Window
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
0 : SMALLWND
Allow received windows when window size is less than half the RAM size.
1 : ALWAYS
Always allow received windows.
2 : NEVER
Never allow received windows.
3 : PSABORT
Allow received windows right after PSTIMABORTn tests have aborted timing and coherent detection is enabled, or when window size is less than half the RAM size.
End of enumeration elements list.
TIMTHRESHGAIN : Timing Threshold Gain
bits : 17 - 19 (3 bit)
access : read-write
CPLXCORREN : Enable Complex Correlation
bits : 20 - 20 (1 bit)
access : read-write
DSSS3SYMBOLSYNCEN : Enable three symbol sync detection
bits : 21 - 21 (1 bit)
access : read-write
CODINGB : Coding format
bits : 25 - 26 (2 bit)
access : read-write
Enumeration:
0 : NRZ
Non Return to Zero
1 : MANCHESTER
Manchester Coding
2 : DSSS
Direct Sequence Spread Spectrum
3 : LINECODE
Line code. Maps 0 to 0011 symbol and 1 to 1100 symbols
End of enumeration elements list.
RXBRCALCDIS : RX Baudrate Calculation Disable
bits : 30 - 30 (1 bit)
access : read-write
No Description
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable peripheral clock to this module
bits : 0 - 0 (1 bit)
access : read-write
No Description
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXBRNUM : Transmit baudrate numerator
bits : 0 - 15 (16 bit)
access : read-write
TXBRDEN : Transmit baudrate denominator
bits : 16 - 23 (8 bit)
access : read-write
No Description
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXBRNUM : Receive baudrate numerator
bits : 0 - 4 (5 bit)
access : read-write
RXBRDEN : Receive baudrate denominator
bits : 5 - 9 (5 bit)
access : read-write
RXBRINT : Receive baudrate integer
bits : 10 - 12 (3 bit)
access : read-write
No Description
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEC0 : First decimation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DF3
Decimation Factor 0 = 3. Cutoff 0.050 * f
1 : DF4WIDE
Decimation Factor 0 = 4. Cutoff 0.069 * f
2 : DF4NARROW
Decimation Factor 0 = 4. Cutoff 0.037 * f
3 : DF8WIDE
Decimation Factor 0 = 8. Cutoff 0.012 * f
4 : DF8NARROW
Decimation Factor 0 = 8. Cutoff 0.005 * f
End of enumeration elements list.
DEC1 : Second decimation
bits : 3 - 16 (14 bit)
access : read-write
DEC2 : Third decimation
bits : 17 - 22 (6 bit)
access : read-write
CFOSR : Center Frequency Oversampling Ratio
bits : 23 - 25 (3 bit)
access : read-write
Enumeration:
0 : CF7
Oversampling ratio = 7
1 : CF8
Oversampling ratio = 8
2 : CF12
Oversampling ratio = 12
3 : CF16
Oversampling ratio = 16
4 : CF32
Oversampling ratio = 32
5 : CF0
Center frequency set to 0
End of enumeration elements list.
DEC1GAIN : Second decimation filter gain
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : ADD0
No additional gain. Suggested setting for BW higher than 1kHz
1 : ADD6
6 dB additional gain. Suggested setting for BW between 250 Hz and 1 kHz
2 : ADD12
12 dB additional gain. Suggested setting for BW less than 250 Hz
End of enumeration elements list.
No Description
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE : Preamble base
bits : 0 - 3 (4 bit)
access : read-write
BASEBITS : BASE bits
bits : 4 - 5 (2 bit)
access : read-write
PRESYMB4FSK : Preamble symbols 4-FSK
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : OUTER
Symbols corresponding to +/- 3dev.
1 : INNER
Symbols corresponding to +/- dev.
End of enumeration elements list.
PREERRORS : Preamble errors
bits : 7 - 10 (4 bit)
access : read-write
DSSSPRE : DSSS preamble
bits : 11 - 11 (1 bit)
access : read-write
SYNCSYMB4FSK : Sync symbols 4FSK
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : FSK2
The syncword is 2FSK modulated. Each bit in SYNCn is encoded as a positive or negative deviation. The deviation is controlled by PRESYMB4FSK.
1 : FSK4
The syncword is 4FSK modulated. Every two bits in SYNCn are encoded as a 4FSK symbol.
End of enumeration elements list.
TXBASES : TX bases
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNC0 : Sync-word 0
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNC1 : Sync word 1
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEMODSTATE : DEMOD state
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0 : OFF
Off state
1 : TIMINGSEARCH
Timing search
2 : PRESEARCH
Preamble search
3 : FRAMESEARCH
Frame search
4 : RXFRAME
Payload Detection
5 : FRAMEDETMODE0
Timing search with sliding window (FDM0)
End of enumeration elements list.
FRAMEDETID : Frame Detected ID
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : FRAMEDET0
Last frame was detected with sync word defined in SYNC0.
1 : FRAMEDET1
Last frame was detected with sync word defined in SYNC1.
End of enumeration elements list.
ANTSEL : Selected Antenna
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : ANTENNA0
Antenna 0 is selected (ANT0 = 1 and ANT1 = 0).
1 : ANTENNA1
Antenna 1 is selected (ANT0 = 0 and ANT1 = 1).
End of enumeration elements list.
TIMSEQINV : Timing Sequence Inverted
bits : 6 - 6 (1 bit)
access : read-only
TIMLOSTCAUSE : Timing Lost Cause
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : LOWCORR
Timing lost during Preamble Search or due to low correlation value during Frame Search.
1 : TIMEOUT
Timing lost due to incorrect symbols detected during Frame Search.
End of enumeration elements list.
DSADETECTED : DSA detected
bits : 8 - 8 (1 bit)
access : read-only
DSAFREQESTDONE : DSA frequency estimation complete
bits : 9 - 9 (1 bit)
access : read-only
VITERBIDEMODTIMDET : Viterbi Demod timing detected
bits : 10 - 10 (1 bit)
access : read-only
VITERBIDEMODFRAMEDET : Viterbi Demod frame detected
bits : 11 - 11 (1 bit)
access : read-only
STAMPSTATE : BLE Viterbi Demod Timing Stamp
bits : 12 - 14 (3 bit)
access : read-only
CORR : Correlation
bits : 16 - 23 (8 bit)
access : read-only
WEAKSYMBOLS : Weak symbols
bits : 24 - 31 (8 bit)
access : read-only
No Description
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMTHRESH : Timing threshold
bits : 0 - 7 (8 bit)
access : read-write
TIMINGBASES : Timing bases
bits : 8 - 11 (4 bit)
access : read-write
ADDTIMSEQ : Additional timing sequences
bits : 12 - 15 (4 bit)
access : read-write
TIMSEQINVEN : Timing sequence inversion enable
bits : 16 - 16 (1 bit)
access : read-write
TIMSEQSYNC : Timing sequence part of sync-word
bits : 17 - 17 (1 bit)
access : read-write
FDM0THRESH : Frame Detection Mode 0 threshold
bits : 18 - 20 (3 bit)
access : read-write
OFFSUBNUM : Offset subperiod numerator
bits : 21 - 24 (4 bit)
access : read-write
OFFSUBDEN : Offset subperiod denominator
bits : 25 - 28 (4 bit)
access : read-write
TSAGCDEL : Timing Search AGC delay
bits : 29 - 29 (1 bit)
access : read-write
FASTRESYNC : Fast timing resynchronization
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : DIS
Disabled.
1 : PREDET
Allow fast resynchronization until preamble is detected.
2 : FRAMEDET
Allow fast resynchronization until frame is detected.
End of enumeration elements list.
No Description
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSSS0 : DSSS symbol 0
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODINDEXM : Modulation index mantissa.
bits : 0 - 4 (5 bit)
access : read-write
MODINDEXE : Modulation index exponent.
bits : 5 - 9 (5 bit)
access : read-write
FREQGAINE : Frequency demodulation gain - exponent
bits : 16 - 18 (3 bit)
access : read-write
FREQGAINM : Frequency demodulation gain - mantissa
bits : 19 - 21 (3 bit)
access : read-write
No Description
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AFCSCALEM : AFC scaling mantissa
bits : 0 - 4 (5 bit)
access : read-write
AFCSCALEE : AFC scaling exponent
bits : 5 - 8 (4 bit)
access : read-write
AFCRXMODE : AFC RX mode
bits : 10 - 12 (3 bit)
access : read-write
Enumeration:
0 : DIS
Disabled.
1 : FREE
Free running. AFCADJRX constantly updated.
2 : FREEPRESTART
Free running. AFCADJRX not updated before preamble is detected.
3 : TIMLOCK
AFCADJRX locked when timing is detected.
4 : PRELOCK
AFCADJRX locked when preamble is detected.
5 : FRAMELOCK
AFCADJRX locked when frame is detected.
6 : FRAMELOCKPRESTART
AFCADJRX not updated before preamble is detected and locked when frame is detected.
End of enumeration elements list.
AFCTXMODE : AFC TX mode
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0 : DIS
Disabled.
1 : PRELOCK
AFCADJTX loaded from AFCADJRX when preamble is detected.
2 : FRAMELOCK
AFCADJTX loaded from AFCADJRX when frame is detected.
End of enumeration elements list.
AFCRXCLR : AFCRX clear mode
bits : 15 - 15 (1 bit)
access : read-write
AFCDEL : AFC delay
bits : 16 - 20 (5 bit)
access : read-write
AFCAVGPER : AFC average period
bits : 21 - 23 (3 bit)
access : read-write
AFCLIMRESET : Reset AFCADJRX value
bits : 24 - 24 (1 bit)
access : read-write
AFCONESHOT : AFC One-Shot feature
bits : 25 - 25 (1 bit)
access : read-write
AFCENINTCOMP : Internal frequency offset compensation
bits : 26 - 26 (1 bit)
access : read-write
AFCDSAFREQOFFEST : Consider frequency offset estimation
bits : 27 - 27 (1 bit)
access : read-write
AFCDELDET : Delay Detection state machine
bits : 28 - 28 (1 bit)
access : read-write
No Description
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AFCADJLIM : AFC adjustment limit
bits : 0 - 17 (18 bit)
access : read-write
No Description
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF0 : Shaping Coefficient 0
bits : 0 - 7 (8 bit)
access : read-write
COEFF1 : Shaping Coefficient 1
bits : 8 - 15 (8 bit)
access : read-write
COEFF2 : Shaping Coefficient 2
bits : 16 - 23 (8 bit)
access : read-write
COEFF3 : Shaping Coefficient 3
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF4 : Shaping Coefficient 4
bits : 0 - 7 (8 bit)
access : read-write
COEFF5 : Shaping Coefficient 5
bits : 8 - 15 (8 bit)
access : read-write
COEFF6 : Shaping Coefficient 6
bits : 16 - 23 (8 bit)
access : read-write
COEFF7 : Shaping Coefficient 7
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF8 : Shaping Coefficient 8
bits : 0 - 7 (8 bit)
access : read-write
COEFF9 : Shaping Coefficient 9
bits : 8 - 15 (8 bit)
access : read-write
COEFF10 : Shaping Coefficient 10
bits : 16 - 23 (8 bit)
access : read-write
COEFF11 : Shaping Coefficient 11
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF12 : Shaping Coefficient 12
bits : 0 - 7 (8 bit)
access : read-write
COEFF13 : Shaping Coefficient 13
bits : 8 - 15 (8 bit)
access : read-write
COEFF14 : Shaping Coefficient 14
bits : 16 - 23 (8 bit)
access : read-write
COEFF15 : Shaping Coefficient 15
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF16 : Shaping Coefficient 16
bits : 0 - 5 (6 bit)
access : read-write
COEFF17 : Shaping Coefficient 17
bits : 6 - 11 (6 bit)
access : read-write
COEFF18 : Shaping Coefficient 18
bits : 12 - 17 (6 bit)
access : read-write
COEFF19 : Shaping Coefficient 19
bits : 18 - 22 (5 bit)
access : read-write
COEFF20 : Shaping Coefficient 20
bits : 23 - 27 (5 bit)
access : read-write
COEFF21 : Shaping Coefficient 21
bits : 28 - 31 (4 bit)
access : read-write
No Description
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF22 : Shaping Coefficient 22
bits : 0 - 3 (4 bit)
access : read-write
COEFF23 : Shaping Coefficient 23
bits : 4 - 7 (4 bit)
access : read-write
COEFF24 : Shaping Coefficient 24
bits : 8 - 11 (4 bit)
access : read-write
COEFF25 : Shaping Coefficient 25
bits : 12 - 15 (4 bit)
access : read-write
COEFF26 : Shaping Coefficient 26
bits : 16 - 19 (4 bit)
access : read-write
COEFF27 : Shaping Coefficient 27
bits : 20 - 23 (4 bit)
access : read-write
COEFF28 : Shaping Coefficient 28
bits : 24 - 27 (4 bit)
access : read-write
COEFF29 : Shaping Coefficient 29
bits : 28 - 31 (4 bit)
access : read-write
No Description
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFF30 : Shaping Coefficient 30
bits : 0 - 3 (4 bit)
access : read-write
COEFF31 : Shaping Coefficient 31
bits : 4 - 7 (4 bit)
access : read-write
COEFF32 : Shaping Coefficient 32
bits : 8 - 10 (3 bit)
access : read-write
COEFF33 : Shaping Coefficient 33
bits : 11 - 13 (3 bit)
access : read-write
COEFF34 : Shaping Coefficient 34
bits : 14 - 16 (3 bit)
access : read-write
COEFF35 : Shaping Coefficient 35
bits : 17 - 19 (3 bit)
access : read-write
COEFF36 : Shaping Coefficient 36
bits : 20 - 22 (3 bit)
access : read-write
COEFF37 : Shaping Coefficient 37
bits : 23 - 25 (3 bit)
access : read-write
COEFF38 : Shaping Coefficient 38
bits : 26 - 28 (3 bit)
access : read-write
COEFF39 : Shaping Coefficient 39
bits : 29 - 31 (3 bit)
access : read-write
No Description
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIMDETCORR : Correlation value
bits : 0 - 7 (8 bit)
access : read-only
TIMDETFREQOFFEST : Frequency offset estimate
bits : 8 - 15 (8 bit)
access : read-only
TIMDETPREERRORS : Preamble errors
bits : 16 - 19 (4 bit)
access : read-only
TIMDETPASS : Timing detection pass
bits : 24 - 24 (1 bit)
access : read-only
TIMDETINDEX : Timing detection index
bits : 25 - 28 (4 bit)
access : read-only
No Description
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMPRATE0 : Ramp rate 0
bits : 0 - 3 (4 bit)
access : read-write
RAMPRATE1 : Ramp rate 1
bits : 4 - 7 (4 bit)
access : read-write
RAMPRATE2 : Ramp rate 2
bits : 8 - 11 (4 bit)
access : read-write
No Description
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMPLEV0 : Ramp level 0
bits : 0 - 7 (8 bit)
access : read-write
RAMPLEV1 : Ramp level 1
bits : 8 - 15 (8 bit)
access : read-write
RAMPLEV2 : Ramp level 2
bits : 16 - 23 (8 bit)
access : read-write
No Description
address_offset : 0xE0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCESTIEN : DC Offset Estimation Enable
bits : 0 - 0 (1 bit)
access : read-write
DCCOMPEN : DC Offset Compensation Enable
bits : 1 - 1 (1 bit)
access : read-write
DCRSTEN : DC Compensation Filter Reset Enable
bits : 2 - 2 (1 bit)
access : read-write
DCCOMPFREEZE : DC Offset Compensation Filter Freeze
bits : 3 - 3 (1 bit)
access : read-write
DCCOMPGEAR : DC Offset Compensation Filter Gear
bits : 4 - 6 (3 bit)
access : read-write
DCLIMIT : DC offset limit
bits : 7 - 8 (2 bit)
access : read-write
Enumeration:
0 : FULLSCALE
1000 mV
1 : FULLSCALEBY4
250 mV
2 : FULLSCALEBY8
125 mV
3 : FULLSCALEBY16
62 mV
End of enumeration elements list.
No Description
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCCOMPINITVALI : I-channel initialization value
bits : 0 - 14 (15 bit)
access : read-write
DCCOMPINITVALQ : Q-channel initialization value
bits : 15 - 29 (15 bit)
access : read-write
DCCOMPINIT : Initialize filter state
bits : 30 - 30 (1 bit)
access : read-write
No Description
address_offset : 0xE8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCCOMPESTIVALI : I-channel DC-Offset Estimated value
bits : 0 - 14 (15 bit)
access : read-only
DCCOMPESTIVALQ : Q-channel DC-Offset Estimated value
bits : 15 - 29 (15 bit)
access : read-only
No Description
address_offset : 0xEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCRATIO1 : I-channel SRC ratio
bits : 0 - 7 (8 bit)
access : read-write
SRCENABLE1 : SRC1 enable
bits : 11 - 11 (1 bit)
access : read-write
SRCRATIO2 : Q-channel SRC ratio
bits : 12 - 26 (15 bit)
access : read-write
SRCENABLE2 : SRC2 enable
bits : 27 - 27 (1 bit)
access : read-write
BWSEL : Channel filter bandwidth
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : X0
wide bandwidth selected BW = 0.263*Fxtal/dec0-factor/dec1-factor
1 : X1
wide bandwidth selected BW = 0.263*Fxtal/dec0-factor/dec1-factor
2 : X2
narrow bandwidth selected BW = 0.196*Fxtal/dec0-factor/dec1-factor
3 : X3
narrow bandwidth selected BW = 0.196*Fxtal/dec0-factor/dec1-factor
End of enumeration elements list.
INTOSR : Forcing Integer OSR
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FOEPREAVG0 : First estimate
bits : 0 - 2 (3 bit)
access : read-write
FOEPREAVG1 : Second estimate
bits : 3 - 5 (3 bit)
access : read-write
FOEPREAVG2 : Third estimate
bits : 6 - 8 (3 bit)
access : read-write
FOEPREAVG3 : Fourth estimate
bits : 9 - 11 (3 bit)
access : read-write
FOEPREAVG4 : Fifth estimate
bits : 12 - 14 (3 bit)
access : read-write
FOEPREAVG5 : Sixth estimate
bits : 15 - 17 (3 bit)
access : read-write
FOEPREAVG6 : Seventh estimate
bits : 18 - 20 (3 bit)
access : read-write
FOEPREAVG7 : Eighth estimate
bits : 21 - 23 (3 bit)
access : read-write
No Description
address_offset : 0xF4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIKETHD : Spike threshold
bits : 0 - 7 (8 bit)
access : read-write
UNMODTHD : Unmodulated carrier detector threshold
bits : 8 - 13 (6 bit)
access : read-write
FDEVMINTHD : Frequency deviation minimum threshold
bits : 14 - 19 (6 bit)
access : read-write
FDEVMAXTHD : Frequency deviation maximum threshold
bits : 20 - 31 (12 bit)
access : read-write
No Description
address_offset : 0xF8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POWABSTHD : Power absolute threshold
bits : 0 - 15 (16 bit)
access : read-write
POWRELTHD : Relative power detector threshold
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
Threshold is 6dB. The relative power detector will trigger when the current RSSI is 6dB stronger than the previously detected RSSI.
1 : MODE1
Threshold is 9dB. The relative power detector will trigger when the current RSSI is 9dB stronger than the previously detected RSSI.
2 : MODE2
Threshold is 12dB. The relative power detector will trigger when the current RSSI is 12dB stronger than the previously detected RSSI.
3 : MODE3
Threshold is 15dB. The relative power detector will trigger when the current RSSI is 15dB stronger than the previously detected RSSI.
End of enumeration elements list.
DSARSTCNT : DSA reset counter
bits : 18 - 20 (3 bit)
access : read-write
RSSIJMPTHD : RSSI jump detector threshold
bits : 21 - 24 (4 bit)
access : read-write
FREQLATDLY : Frequency late delay
bits : 25 - 26 (2 bit)
access : read-write
PWRFLTBYP : Power filter bypass
bits : 27 - 27 (1 bit)
access : read-write
AMPFLTBYP : Amplitude filter bypass
bits : 28 - 28 (1 bit)
access : read-write
PWRDETDIS : Power detection disabled
bits : 29 - 29 (1 bit)
access : read-write
FREQSCALE : Frequency scale factor
bits : 30 - 30 (1 bit)
access : read-write
No Description
address_offset : 0xFC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSAMODE : Mode of Digital Signal Arrival detector
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
DSA is disabled
1 : ENABLED
DSA is enabled by the relative/absolute RSSI detector and is reset by using detectors for spike content and frequency deviation. The RSSI jump detector is used to recover from false detects.
End of enumeration elements list.
ARRTHD : Signal arrival valid counter threshold
bits : 2 - 5 (4 bit)
access : read-write
ARRTOLERTHD0 : Arrival tolerance threshold 0
bits : 6 - 10 (5 bit)
access : read-write
ARRTOLERTHD1 : Arrival tolerance threshold 1
bits : 11 - 15 (5 bit)
access : read-write
SCHPRD : Search period window length
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : TS2
The search period is 2 symbol periods.
1 : TS4
The search period is 4 symbol periods.
End of enumeration elements list.
FREQAVGSYM : DSA frequency estimation averaging
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : AVG2TS
Frequency estimation over 2 symbol periods.
1 : AVG4TS
Frequency estimation over 4 symbol periods.
End of enumeration elements list.
TRANRSTDSA : power transient detector Reset DSA
bits : 18 - 18 (1 bit)
access : read-write
DSARSTON : DSA detection reset
bits : 19 - 19 (1 bit)
access : read-write
GAINREDUCDLY : Detection Delay of AGC gain reduction
bits : 21 - 22 (2 bit)
access : read-write
LOWDUTY : Low duty cycle delay
bits : 23 - 25 (3 bit)
access : read-write
RESTORE : Power detector reset of DSA
bits : 26 - 26 (1 bit)
access : read-write
AGCBAUDEN : Consider Baud_en from AGC
bits : 27 - 27 (1 bit)
access : read-write
AMPJUPTHD : Amplitude jump detection thrshold
bits : 28 - 31 (4 bit)
access : read-write
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