\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
UDPHS Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEV_ADDR : UDPHS Address
bits : 0 - 6 (7 bit)
access : read-write
FADDR_EN : Function Address Enable
bits : 7 - 7 (1 bit)
access : read-write
EN_UDPHS : UDPHS Enable
bits : 8 - 8 (1 bit)
access : read-write
DETACH : Detach Command
bits : 9 - 9 (1 bit)
access : read-write
REWAKEUP : Send Remote Wake Up
bits : 10 - 10 (1 bit)
access : read-write
PULLD_DIS : Pull-Down Disable
bits : 11 - 11 (1 bit)
access : read-write
UDPHS Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DET_SUSPD : Suspend Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
MICRO_SOF : Micro-SOF Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
INT_SOF : SOF Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
ENDRESET : End Of Reset Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
WAKE_UP : Wake Up CPU Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
ENDOFRSM : End Of Resume Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
UPSTR_RES : Upstream Resume Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
EPT_0 : Endpoint 0 Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
EPT_1 : Endpoint 1 Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
EPT_2 : Endpoint 2 Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
EPT_3 : Endpoint 3 Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
EPT_4 : Endpoint 4 Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
EPT_5 : Endpoint 5 Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
EPT_6 : Endpoint 6 Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write
EPT_7 : Endpoint 7 Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-write
EPT_8 : Endpoint 8 Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write
EPT_9 : Endpoint 9 Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write
EPT_10 : Endpoint 10 Interrupt Enable
bits : 18 - 18 (1 bit)
access : read-write
EPT_11 : Endpoint 11 Interrupt Enable
bits : 19 - 19 (1 bit)
access : read-write
EPT_12 : Endpoint 12 Interrupt Enable
bits : 20 - 20 (1 bit)
access : read-write
EPT_13 : Endpoint 13 Interrupt Enable
bits : 21 - 21 (1 bit)
access : read-write
EPT_14 : Endpoint 14 Interrupt Enable
bits : 22 - 22 (1 bit)
access : read-write
EPT_15 : Endpoint 15 Interrupt Enable
bits : 23 - 23 (1 bit)
access : read-write
DMA_1 : DMA Channel 1 Interrupt Enable
bits : 25 - 25 (1 bit)
access : read-write
DMA_2 : DMA Channel 2 Interrupt Enable
bits : 26 - 26 (1 bit)
access : read-write
DMA_3 : DMA Channel 3 Interrupt Enable
bits : 27 - 27 (1 bit)
access : read-write
DMA_4 : DMA Channel 4 Interrupt Enable
bits : 28 - 28 (1 bit)
access : read-write
DMA_5 : DMA Channel 5 Interrupt Enable
bits : 29 - 29 (1 bit)
access : read-write
DMA_6 : DMA Channel 6 Interrupt Enable
bits : 30 - 30 (1 bit)
access : read-write
DMA_7 : DMA Channel 7 Interrupt Enable
bits : 31 - 31 (1 bit)
access : read-write
UDPHS Endpoint Configuration Register (endpoint = 0)
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 8
8 bytes
0x1 : 16
16 bytes
0x2 : 32
32 bytes
0x3 : 64
64 bytes
0x4 : 128
128 bytes
0x5 : 256
256 bytes
0x6 : 512
512 bytes
0x7 : 1024
1024 bytes
End of enumeration elements list.
EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write
EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL8
Control endpoint
0x1 : ISO
Isochronous endpoint
0x2 : BULK
Bulk endpoint
0x3 : INT
Interrupt endpoint
End of enumeration elements list.
BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : 0
Zero bank, the endpoint is not mapped in memory
0x1 : 1
One bank (bank 0)
0x2 : 2
Double bank (Ping-Pong: bank0/bank1)
0x3 : 3
Triple bank (bank0/bank1/bank2)
End of enumeration elements list.
NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write
EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write
UDPHS Endpoint Control Enable Register (endpoint = 0)
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Enable Register (endpoint = 0)
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 0)
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 0)
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Register (endpoint = 0)
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Control Register (endpoint = 0)
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only
MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Set Status Register (endpoint = 0)
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Set Status Register (endpoint = 0)
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 0)
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 0)
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only
UDPHS Endpoint Status Register (endpoint = 0)
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Reserved for High Bandwidth Isochronous Endpoint
0x3 : MDATA
Reserved for High Bandwidth Isochronous Endpoint
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only
CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Status Register (endpoint = 0)
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Data2 (only for High Bandwidth Isochronous Endpoint)
0x3 : MDATA
MData (only for High Bandwidth Isochronous Endpoint)
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only
CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Bank 0 (or single bank)
0x1 : BANK1
Bank 1
0x2 : BANK2
Bank 2
End of enumeration elements list.
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Configuration Register (endpoint = 1)
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 8
8 bytes
0x1 : 16
16 bytes
0x2 : 32
32 bytes
0x3 : 64
64 bytes
0x4 : 128
128 bytes
0x5 : 256
256 bytes
0x6 : 512
512 bytes
0x7 : 1024
1024 bytes
End of enumeration elements list.
EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write
EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL8
Control endpoint
0x1 : ISO
Isochronous endpoint
0x2 : BULK
Bulk endpoint
0x3 : INT
Interrupt endpoint
End of enumeration elements list.
BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : 0
Zero bank, the endpoint is not mapped in memory
0x1 : 1
One bank (bank 0)
0x2 : 2
Double bank (Ping-Pong: bank0/bank1)
0x3 : 3
Triple bank (bank0/bank1/bank2)
End of enumeration elements list.
NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write
EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write
UDPHS Endpoint Control Enable Register (endpoint = 1)
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Enable Register (endpoint = 1)
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 1)
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 1)
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Register (endpoint = 1)
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Control Register (endpoint = 1)
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only
MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Set Status Register (endpoint = 1)
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Set Status Register (endpoint = 1)
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 1)
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 1)
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only
UDPHS Endpoint Status Register (endpoint = 1)
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Reserved for High Bandwidth Isochronous Endpoint
0x3 : MDATA
Reserved for High Bandwidth Isochronous Endpoint
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only
CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Status Register (endpoint = 1)
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Data2 (only for High Bandwidth Isochronous Endpoint)
0x3 : MDATA
MData (only for High Bandwidth Isochronous Endpoint)
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only
CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Bank 0 (or single bank)
0x1 : BANK1
Bank 1
0x2 : BANK2
Bank 2
End of enumeration elements list.
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Interrupt Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPEED : Speed Status
bits : 0 - 0 (1 bit)
access : read-only
DET_SUSPD : Suspend Interrupt
bits : 1 - 1 (1 bit)
access : read-only
MICRO_SOF : Micro Start Of Frame Interrupt
bits : 2 - 2 (1 bit)
access : read-only
INT_SOF : Start Of Frame Interrupt
bits : 3 - 3 (1 bit)
access : read-only
ENDRESET : End Of Reset Interrupt
bits : 4 - 4 (1 bit)
access : read-only
WAKE_UP : Wake Up CPU Interrupt
bits : 5 - 5 (1 bit)
access : read-only
ENDOFRSM : End Of Resume Interrupt
bits : 6 - 6 (1 bit)
access : read-only
UPSTR_RES : Upstream Resume Interrupt
bits : 7 - 7 (1 bit)
access : read-only
EPT_0 : Endpoint 0 Interrupt
bits : 8 - 8 (1 bit)
access : read-only
EPT_1 : Endpoint 1 Interrupt
bits : 9 - 9 (1 bit)
access : read-only
EPT_2 : Endpoint 2 Interrupt
bits : 10 - 10 (1 bit)
access : read-only
EPT_3 : Endpoint 3 Interrupt
bits : 11 - 11 (1 bit)
access : read-only
EPT_4 : Endpoint 4 Interrupt
bits : 12 - 12 (1 bit)
access : read-only
EPT_5 : Endpoint 5 Interrupt
bits : 13 - 13 (1 bit)
access : read-only
EPT_6 : Endpoint 6 Interrupt
bits : 14 - 14 (1 bit)
access : read-only
EPT_7 : Endpoint 7 Interrupt
bits : 15 - 15 (1 bit)
access : read-only
EPT_8 : Endpoint 8 Interrupt
bits : 16 - 16 (1 bit)
access : read-only
EPT_9 : Endpoint 9 Interrupt
bits : 17 - 17 (1 bit)
access : read-only
EPT_10 : Endpoint 10 Interrupt
bits : 18 - 18 (1 bit)
access : read-only
EPT_11 : Endpoint 11 Interrupt
bits : 19 - 19 (1 bit)
access : read-only
EPT_12 : Endpoint 12 Interrupt
bits : 20 - 20 (1 bit)
access : read-only
EPT_13 : Endpoint 13 Interrupt
bits : 21 - 21 (1 bit)
access : read-only
EPT_14 : Endpoint 14 Interrupt
bits : 22 - 22 (1 bit)
access : read-only
EPT_15 : Endpoint 15 Interrupt
bits : 23 - 23 (1 bit)
access : read-only
DMA_1 : DMA Channel 1 Interrupt
bits : 25 - 25 (1 bit)
access : read-only
DMA_2 : DMA Channel 2 Interrupt
bits : 26 - 26 (1 bit)
access : read-only
DMA_3 : DMA Channel 3 Interrupt
bits : 27 - 27 (1 bit)
access : read-only
DMA_4 : DMA Channel 4 Interrupt
bits : 28 - 28 (1 bit)
access : read-only
DMA_5 : DMA Channel 5 Interrupt
bits : 29 - 29 (1 bit)
access : read-only
DMA_6 : DMA Channel 6 Interrupt
bits : 30 - 30 (1 bit)
access : read-only
DMA_7 : DMA Channel 7 Interrupt
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Configuration Register (endpoint = 2)
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 8
8 bytes
0x1 : 16
16 bytes
0x2 : 32
32 bytes
0x3 : 64
64 bytes
0x4 : 128
128 bytes
0x5 : 256
256 bytes
0x6 : 512
512 bytes
0x7 : 1024
1024 bytes
End of enumeration elements list.
EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write
EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL8
Control endpoint
0x1 : ISO
Isochronous endpoint
0x2 : BULK
Bulk endpoint
0x3 : INT
Interrupt endpoint
End of enumeration elements list.
BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : 0
Zero bank, the endpoint is not mapped in memory
0x1 : 1
One bank (bank 0)
0x2 : 2
Double bank (Ping-Pong: bank0/bank1)
0x3 : 3
Triple bank (bank0/bank1/bank2)
End of enumeration elements list.
NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write
EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write
UDPHS Endpoint Control Enable Register (endpoint = 2)
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Enable Register (endpoint = 2)
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 2)
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 2)
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Register (endpoint = 2)
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Control Register (endpoint = 2)
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only
MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Set Status Register (endpoint = 2)
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Set Status Register (endpoint = 2)
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 2)
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 2)
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only
UDPHS Endpoint Status Register (endpoint = 2)
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Reserved for High Bandwidth Isochronous Endpoint
0x3 : MDATA
Reserved for High Bandwidth Isochronous Endpoint
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only
CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Status Register (endpoint = 2)
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Data2 (only for High Bandwidth Isochronous Endpoint)
0x3 : MDATA
MData (only for High Bandwidth Isochronous Endpoint)
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only
CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Bank 0 (or single bank)
0x1 : BANK1
Bank 1
0x2 : BANK2
Bank 2
End of enumeration elements list.
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Configuration Register (endpoint = 3)
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 8
8 bytes
0x1 : 16
16 bytes
0x2 : 32
32 bytes
0x3 : 64
64 bytes
0x4 : 128
128 bytes
0x5 : 256
256 bytes
0x6 : 512
512 bytes
0x7 : 1024
1024 bytes
End of enumeration elements list.
EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write
EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL8
Control endpoint
0x1 : ISO
Isochronous endpoint
0x2 : BULK
Bulk endpoint
0x3 : INT
Interrupt endpoint
End of enumeration elements list.
BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : 0
Zero bank, the endpoint is not mapped in memory
0x1 : 1
One bank (bank 0)
0x2 : 2
Double bank (Ping-Pong: bank0/bank1)
0x3 : 3
Triple bank (bank0/bank1/bank2)
End of enumeration elements list.
NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write
EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write
UDPHS Endpoint Control Enable Register (endpoint = 3)
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Enable Register (endpoint = 3)
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 3)
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 3)
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Register (endpoint = 3)
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Control Register (endpoint = 3)
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only
MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Set Status Register (endpoint = 3)
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Set Status Register (endpoint = 3)
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 3)
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 3)
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only
UDPHS Endpoint Status Register (endpoint = 3)
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Reserved for High Bandwidth Isochronous Endpoint
0x3 : MDATA
Reserved for High Bandwidth Isochronous Endpoint
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only
CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Status Register (endpoint = 3)
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Data2 (only for High Bandwidth Isochronous Endpoint)
0x3 : MDATA
MData (only for High Bandwidth Isochronous Endpoint)
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only
CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Bank 0 (or single bank)
0x1 : BANK1
Bank 1
0x2 : BANK2
Bank 2
End of enumeration elements list.
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Clear Interrupt Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DET_SUSPD : Suspend Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
MICRO_SOF : Micro Start Of Frame Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
INT_SOF : Start Of Frame Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
ENDRESET : End Of Reset Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
WAKE_UP : Wake Up CPU Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
ENDOFRSM : End Of Resume Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
UPSTR_RES : Upstream Resume Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
UDPHS Endpoint Configuration Register (endpoint = 4)
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 8
8 bytes
0x1 : 16
16 bytes
0x2 : 32
32 bytes
0x3 : 64
64 bytes
0x4 : 128
128 bytes
0x5 : 256
256 bytes
0x6 : 512
512 bytes
0x7 : 1024
1024 bytes
End of enumeration elements list.
EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write
EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL8
Control endpoint
0x1 : ISO
Isochronous endpoint
0x2 : BULK
Bulk endpoint
0x3 : INT
Interrupt endpoint
End of enumeration elements list.
BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : 0
Zero bank, the endpoint is not mapped in memory
0x1 : 1
One bank (bank 0)
0x2 : 2
Double bank (Ping-Pong: bank0/bank1)
0x3 : 3
Triple bank (bank0/bank1/bank2)
End of enumeration elements list.
NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write
EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write
UDPHS Endpoint Control Enable Register (endpoint = 4)
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Enable Register (endpoint = 4)
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 4)
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 4)
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Register (endpoint = 4)
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Control Register (endpoint = 4)
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only
MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Set Status Register (endpoint = 4)
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Set Status Register (endpoint = 4)
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 4)
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 4)
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only
UDPHS Endpoint Status Register (endpoint = 4)
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Reserved for High Bandwidth Isochronous Endpoint
0x3 : MDATA
Reserved for High Bandwidth Isochronous Endpoint
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only
CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Status Register (endpoint = 4)
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Data2 (only for High Bandwidth Isochronous Endpoint)
0x3 : MDATA
MData (only for High Bandwidth Isochronous Endpoint)
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only
CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Bank 0 (or single bank)
0x1 : BANK1
Bank 1
0x2 : BANK2
Bank 2
End of enumeration elements list.
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Configuration Register (endpoint = 5)
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 8
8 bytes
0x1 : 16
16 bytes
0x2 : 32
32 bytes
0x3 : 64
64 bytes
0x4 : 128
128 bytes
0x5 : 256
256 bytes
0x6 : 512
512 bytes
0x7 : 1024
1024 bytes
End of enumeration elements list.
EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write
EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL8
Control endpoint
0x1 : ISO
Isochronous endpoint
0x2 : BULK
Bulk endpoint
0x3 : INT
Interrupt endpoint
End of enumeration elements list.
BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : 0
Zero bank, the endpoint is not mapped in memory
0x1 : 1
One bank (bank 0)
0x2 : 2
Double bank (Ping-Pong: bank0/bank1)
0x3 : 3
Triple bank (bank0/bank1/bank2)
End of enumeration elements list.
NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write
EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write
UDPHS Endpoint Control Enable Register (endpoint = 5)
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Enable Register (endpoint = 5)
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 5)
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 5)
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Register (endpoint = 5)
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Control Register (endpoint = 5)
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only
MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Set Status Register (endpoint = 5)
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Set Status Register (endpoint = 5)
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 5)
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 5)
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only
UDPHS Endpoint Status Register (endpoint = 5)
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Reserved for High Bandwidth Isochronous Endpoint
0x3 : MDATA
Reserved for High Bandwidth Isochronous Endpoint
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only
CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Status Register (endpoint = 5)
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Data2 (only for High Bandwidth Isochronous Endpoint)
0x3 : MDATA
MData (only for High Bandwidth Isochronous Endpoint)
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only
CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Bank 0 (or single bank)
0x1 : BANK1
Bank 1
0x2 : BANK2
Bank 2
End of enumeration elements list.
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoints Reset Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_0 : Endpoint 0 Reset
bits : 0 - 0 (1 bit)
access : write-only
EPT_1 : Endpoint 1 Reset
bits : 1 - 1 (1 bit)
access : write-only
EPT_2 : Endpoint 2 Reset
bits : 2 - 2 (1 bit)
access : write-only
EPT_3 : Endpoint 3 Reset
bits : 3 - 3 (1 bit)
access : write-only
EPT_4 : Endpoint 4 Reset
bits : 4 - 4 (1 bit)
access : write-only
EPT_5 : Endpoint 5 Reset
bits : 5 - 5 (1 bit)
access : write-only
EPT_6 : Endpoint 6 Reset
bits : 6 - 6 (1 bit)
access : write-only
EPT_7 : Endpoint 7 Reset
bits : 7 - 7 (1 bit)
access : write-only
EPT_8 : Endpoint 8 Reset
bits : 8 - 8 (1 bit)
access : write-only
EPT_9 : Endpoint 9 Reset
bits : 9 - 9 (1 bit)
access : write-only
EPT_10 : Endpoint 10 Reset
bits : 10 - 10 (1 bit)
access : write-only
EPT_11 : Endpoint 11 Reset
bits : 11 - 11 (1 bit)
access : write-only
EPT_12 : Endpoint 12 Reset
bits : 12 - 12 (1 bit)
access : write-only
EPT_13 : Endpoint 13 Reset
bits : 13 - 13 (1 bit)
access : write-only
EPT_14 : Endpoint 14 Reset
bits : 14 - 14 (1 bit)
access : write-only
EPT_15 : Endpoint 15 Reset
bits : 15 - 15 (1 bit)
access : write-only
UDPHS Endpoint Configuration Register (endpoint = 6)
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 8
8 bytes
0x1 : 16
16 bytes
0x2 : 32
32 bytes
0x3 : 64
64 bytes
0x4 : 128
128 bytes
0x5 : 256
256 bytes
0x6 : 512
512 bytes
0x7 : 1024
1024 bytes
End of enumeration elements list.
EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write
EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL8
Control endpoint
0x1 : ISO
Isochronous endpoint
0x2 : BULK
Bulk endpoint
0x3 : INT
Interrupt endpoint
End of enumeration elements list.
BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : 0
Zero bank, the endpoint is not mapped in memory
0x1 : 1
One bank (bank 0)
0x2 : 2
Double bank (Ping-Pong: bank0/bank1)
0x3 : 3
Triple bank (bank0/bank1/bank2)
End of enumeration elements list.
NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write
EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write
UDPHS Endpoint Control Enable Register (endpoint = 6)
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Enable Register (endpoint = 6)
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 6)
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 6)
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Register (endpoint = 6)
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Control Register (endpoint = 6)
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only
MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Set Status Register (endpoint = 6)
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Set Status Register (endpoint = 6)
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 6)
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 6)
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only
UDPHS Endpoint Status Register (endpoint = 6)
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Reserved for High Bandwidth Isochronous Endpoint
0x3 : MDATA
Reserved for High Bandwidth Isochronous Endpoint
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only
CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Status Register (endpoint = 6)
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Data2 (only for High Bandwidth Isochronous Endpoint)
0x3 : MDATA
MData (only for High Bandwidth Isochronous Endpoint)
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only
CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Bank 0 (or single bank)
0x1 : BANK1
Bank 1
0x2 : BANK2
Bank 2
End of enumeration elements list.
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Configuration Register (endpoint = 7)
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 8
8 bytes
0x1 : 16
16 bytes
0x2 : 32
32 bytes
0x3 : 64
64 bytes
0x4 : 128
128 bytes
0x5 : 256
256 bytes
0x6 : 512
512 bytes
0x7 : 1024
1024 bytes
End of enumeration elements list.
EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write
EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL8
Control endpoint
0x1 : ISO
Isochronous endpoint
0x2 : BULK
Bulk endpoint
0x3 : INT
Interrupt endpoint
End of enumeration elements list.
BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : 0
Zero bank, the endpoint is not mapped in memory
0x1 : 1
One bank (bank 0)
0x2 : 2
Double bank (Ping-Pong: bank0/bank1)
0x3 : 3
Triple bank (bank0/bank1/bank2)
End of enumeration elements list.
NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write
EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write
UDPHS Endpoint Control Enable Register (endpoint = 7)
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Enable Register (endpoint = 7)
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 7)
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 7)
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Register (endpoint = 7)
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Control Register (endpoint = 7)
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only
MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Set Status Register (endpoint = 7)
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Set Status Register (endpoint = 7)
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 7)
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 7)
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only
UDPHS Endpoint Status Register (endpoint = 7)
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Reserved for High Bandwidth Isochronous Endpoint
0x3 : MDATA
Reserved for High Bandwidth Isochronous Endpoint
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only
CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Status Register (endpoint = 7)
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Data2 (only for High Bandwidth Isochronous Endpoint)
0x3 : MDATA
MData (only for High Bandwidth Isochronous Endpoint)
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only
CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Bank 0 (or single bank)
0x1 : BANK1
Bank 1
0x2 : BANK2
Bank 2
End of enumeration elements list.
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Configuration Register (endpoint = 8)
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 8
8 bytes
0x1 : 16
16 bytes
0x2 : 32
32 bytes
0x3 : 64
64 bytes
0x4 : 128
128 bytes
0x5 : 256
256 bytes
0x6 : 512
512 bytes
0x7 : 1024
1024 bytes
End of enumeration elements list.
EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write
EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL8
Control endpoint
0x1 : ISO
Isochronous endpoint
0x2 : BULK
Bulk endpoint
0x3 : INT
Interrupt endpoint
End of enumeration elements list.
BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : 0
Zero bank, the endpoint is not mapped in memory
0x1 : 1
One bank (bank 0)
0x2 : 2
Double bank (Ping-Pong: bank0/bank1)
0x3 : 3
Triple bank (bank0/bank1/bank2)
End of enumeration elements list.
NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write
EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write
UDPHS Endpoint Control Enable Register (endpoint = 8)
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Enable Register (endpoint = 8)
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 8)
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 8)
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Register (endpoint = 8)
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Control Register (endpoint = 8)
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only
MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Set Status Register (endpoint = 8)
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Set Status Register (endpoint = 8)
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 8)
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 8)
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only
UDPHS Endpoint Status Register (endpoint = 8)
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Reserved for High Bandwidth Isochronous Endpoint
0x3 : MDATA
Reserved for High Bandwidth Isochronous Endpoint
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only
CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Status Register (endpoint = 8)
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Data2 (only for High Bandwidth Isochronous Endpoint)
0x3 : MDATA
MData (only for High Bandwidth Isochronous Endpoint)
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only
CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Bank 0 (or single bank)
0x1 : BANK1
Bank 1
0x2 : BANK2
Bank 2
End of enumeration elements list.
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Configuration Register (endpoint = 9)
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 8
8 bytes
0x1 : 16
16 bytes
0x2 : 32
32 bytes
0x3 : 64
64 bytes
0x4 : 128
128 bytes
0x5 : 256
256 bytes
0x6 : 512
512 bytes
0x7 : 1024
1024 bytes
End of enumeration elements list.
EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write
EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL8
Control endpoint
0x1 : ISO
Isochronous endpoint
0x2 : BULK
Bulk endpoint
0x3 : INT
Interrupt endpoint
End of enumeration elements list.
BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : 0
Zero bank, the endpoint is not mapped in memory
0x1 : 1
One bank (bank 0)
0x2 : 2
Double bank (Ping-Pong: bank0/bank1)
0x3 : 3
Triple bank (bank0/bank1/bank2)
End of enumeration elements list.
NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write
EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write
UDPHS Endpoint Control Enable Register (endpoint = 9)
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Enable Register (endpoint = 9)
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 9)
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 9)
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Register (endpoint = 9)
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Control Register (endpoint = 9)
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only
MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Set Status Register (endpoint = 9)
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Set Status Register (endpoint = 9)
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 9)
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 9)
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only
UDPHS Endpoint Status Register (endpoint = 9)
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Reserved for High Bandwidth Isochronous Endpoint
0x3 : MDATA
Reserved for High Bandwidth Isochronous Endpoint
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only
CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Status Register (endpoint = 9)
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Data2 (only for High Bandwidth Isochronous Endpoint)
0x3 : MDATA
MData (only for High Bandwidth Isochronous Endpoint)
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only
CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Bank 0 (or single bank)
0x1 : BANK1
Bank 1
0x2 : BANK2
Bank 2
End of enumeration elements list.
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Configuration Register (endpoint = 10)
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 8
8 bytes
0x1 : 16
16 bytes
0x2 : 32
32 bytes
0x3 : 64
64 bytes
0x4 : 128
128 bytes
0x5 : 256
256 bytes
0x6 : 512
512 bytes
0x7 : 1024
1024 bytes
End of enumeration elements list.
EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write
EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL8
Control endpoint
0x1 : ISO
Isochronous endpoint
0x2 : BULK
Bulk endpoint
0x3 : INT
Interrupt endpoint
End of enumeration elements list.
BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : 0
Zero bank, the endpoint is not mapped in memory
0x1 : 1
One bank (bank 0)
0x2 : 2
Double bank (Ping-Pong: bank0/bank1)
0x3 : 3
Triple bank (bank0/bank1/bank2)
End of enumeration elements list.
NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write
EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write
UDPHS Endpoint Control Enable Register (endpoint = 10)
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Enable Register (endpoint = 10)
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 10)
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 10)
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Register (endpoint = 10)
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Control Register (endpoint = 10)
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only
MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Set Status Register (endpoint = 10)
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Set Status Register (endpoint = 10)
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 10)
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 10)
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only
UDPHS Endpoint Status Register (endpoint = 10)
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Reserved for High Bandwidth Isochronous Endpoint
0x3 : MDATA
Reserved for High Bandwidth Isochronous Endpoint
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only
CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Status Register (endpoint = 10)
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Data2 (only for High Bandwidth Isochronous Endpoint)
0x3 : MDATA
MData (only for High Bandwidth Isochronous Endpoint)
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only
CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Bank 0 (or single bank)
0x1 : BANK1
Bank 1
0x2 : BANK2
Bank 2
End of enumeration elements list.
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Configuration Register (endpoint = 11)
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 8
8 bytes
0x1 : 16
16 bytes
0x2 : 32
32 bytes
0x3 : 64
64 bytes
0x4 : 128
128 bytes
0x5 : 256
256 bytes
0x6 : 512
512 bytes
0x7 : 1024
1024 bytes
End of enumeration elements list.
EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write
EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL8
Control endpoint
0x1 : ISO
Isochronous endpoint
0x2 : BULK
Bulk endpoint
0x3 : INT
Interrupt endpoint
End of enumeration elements list.
BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : 0
Zero bank, the endpoint is not mapped in memory
0x1 : 1
One bank (bank 0)
0x2 : 2
Double bank (Ping-Pong: bank0/bank1)
0x3 : 3
Triple bank (bank0/bank1/bank2)
End of enumeration elements list.
NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write
EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write
UDPHS Endpoint Control Enable Register (endpoint = 11)
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Enable Register (endpoint = 11)
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 11)
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 11)
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Register (endpoint = 11)
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Control Register (endpoint = 11)
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only
MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Set Status Register (endpoint = 11)
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Set Status Register (endpoint = 11)
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 11)
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 11)
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only
UDPHS Endpoint Status Register (endpoint = 11)
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Reserved for High Bandwidth Isochronous Endpoint
0x3 : MDATA
Reserved for High Bandwidth Isochronous Endpoint
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only
CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Status Register (endpoint = 11)
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Data2 (only for High Bandwidth Isochronous Endpoint)
0x3 : MDATA
MData (only for High Bandwidth Isochronous Endpoint)
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only
CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Bank 0 (or single bank)
0x1 : BANK1
Bank 1
0x2 : BANK2
Bank 2
End of enumeration elements list.
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Configuration Register (endpoint = 12)
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 8
8 bytes
0x1 : 16
16 bytes
0x2 : 32
32 bytes
0x3 : 64
64 bytes
0x4 : 128
128 bytes
0x5 : 256
256 bytes
0x6 : 512
512 bytes
0x7 : 1024
1024 bytes
End of enumeration elements list.
EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write
EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL8
Control endpoint
0x1 : ISO
Isochronous endpoint
0x2 : BULK
Bulk endpoint
0x3 : INT
Interrupt endpoint
End of enumeration elements list.
BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : 0
Zero bank, the endpoint is not mapped in memory
0x1 : 1
One bank (bank 0)
0x2 : 2
Double bank (Ping-Pong: bank0/bank1)
0x3 : 3
Triple bank (bank0/bank1/bank2)
End of enumeration elements list.
NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write
EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write
UDPHS Endpoint Control Enable Register (endpoint = 12)
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Enable Register (endpoint = 12)
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 12)
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 12)
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Register (endpoint = 12)
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Control Register (endpoint = 12)
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only
MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Set Status Register (endpoint = 12)
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Set Status Register (endpoint = 12)
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 12)
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 12)
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only
UDPHS Endpoint Status Register (endpoint = 12)
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Reserved for High Bandwidth Isochronous Endpoint
0x3 : MDATA
Reserved for High Bandwidth Isochronous Endpoint
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only
CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Status Register (endpoint = 12)
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Data2 (only for High Bandwidth Isochronous Endpoint)
0x3 : MDATA
MData (only for High Bandwidth Isochronous Endpoint)
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only
CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Bank 0 (or single bank)
0x1 : BANK1
Bank 1
0x2 : BANK2
Bank 2
End of enumeration elements list.
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Configuration Register (endpoint = 13)
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 8
8 bytes
0x1 : 16
16 bytes
0x2 : 32
32 bytes
0x3 : 64
64 bytes
0x4 : 128
128 bytes
0x5 : 256
256 bytes
0x6 : 512
512 bytes
0x7 : 1024
1024 bytes
End of enumeration elements list.
EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write
EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL8
Control endpoint
0x1 : ISO
Isochronous endpoint
0x2 : BULK
Bulk endpoint
0x3 : INT
Interrupt endpoint
End of enumeration elements list.
BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : 0
Zero bank, the endpoint is not mapped in memory
0x1 : 1
One bank (bank 0)
0x2 : 2
Double bank (Ping-Pong: bank0/bank1)
0x3 : 3
Triple bank (bank0/bank1/bank2)
End of enumeration elements list.
NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write
EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write
UDPHS Endpoint Control Enable Register (endpoint = 13)
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Enable Register (endpoint = 13)
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 13)
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 13)
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Register (endpoint = 13)
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Control Register (endpoint = 13)
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only
MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Set Status Register (endpoint = 13)
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Set Status Register (endpoint = 13)
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 13)
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 13)
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only
UDPHS Endpoint Status Register (endpoint = 13)
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Reserved for High Bandwidth Isochronous Endpoint
0x3 : MDATA
Reserved for High Bandwidth Isochronous Endpoint
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only
CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Status Register (endpoint = 13)
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Data2 (only for High Bandwidth Isochronous Endpoint)
0x3 : MDATA
MData (only for High Bandwidth Isochronous Endpoint)
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only
CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Bank 0 (or single bank)
0x1 : BANK1
Bank 1
0x2 : BANK2
Bank 2
End of enumeration elements list.
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Configuration Register (endpoint = 14)
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 8
8 bytes
0x1 : 16
16 bytes
0x2 : 32
32 bytes
0x3 : 64
64 bytes
0x4 : 128
128 bytes
0x5 : 256
256 bytes
0x6 : 512
512 bytes
0x7 : 1024
1024 bytes
End of enumeration elements list.
EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write
EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL8
Control endpoint
0x1 : ISO
Isochronous endpoint
0x2 : BULK
Bulk endpoint
0x3 : INT
Interrupt endpoint
End of enumeration elements list.
BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : 0
Zero bank, the endpoint is not mapped in memory
0x1 : 1
One bank (bank 0)
0x2 : 2
Double bank (Ping-Pong: bank0/bank1)
0x3 : 3
Triple bank (bank0/bank1/bank2)
End of enumeration elements list.
NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write
EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write
UDPHS Endpoint Control Enable Register (endpoint = 14)
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Enable Register (endpoint = 14)
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 14)
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 14)
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Register (endpoint = 14)
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Control Register (endpoint = 14)
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only
MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Set Status Register (endpoint = 14)
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Set Status Register (endpoint = 14)
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 14)
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 14)
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only
UDPHS Endpoint Status Register (endpoint = 14)
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Reserved for High Bandwidth Isochronous Endpoint
0x3 : MDATA
Reserved for High Bandwidth Isochronous Endpoint
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only
CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Status Register (endpoint = 14)
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Data2 (only for High Bandwidth Isochronous Endpoint)
0x3 : MDATA
MData (only for High Bandwidth Isochronous Endpoint)
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only
CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Bank 0 (or single bank)
0x1 : BANK1
Bank 1
0x2 : BANK2
Bank 2
End of enumeration elements list.
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Configuration Register (endpoint = 15)
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPT_SIZE : Endpoint Size
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 8
8 bytes
0x1 : 16
16 bytes
0x2 : 32
32 bytes
0x3 : 64
64 bytes
0x4 : 128
128 bytes
0x5 : 256
256 bytes
0x6 : 512
512 bytes
0x7 : 1024
1024 bytes
End of enumeration elements list.
EPT_DIR : Endpoint Direction
bits : 3 - 3 (1 bit)
access : read-write
EPT_TYPE : Endpoint Type
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL8
Control endpoint
0x1 : ISO
Isochronous endpoint
0x2 : BULK
Bulk endpoint
0x3 : INT
Interrupt endpoint
End of enumeration elements list.
BK_NUMBER : Number of Banks
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : 0
Zero bank, the endpoint is not mapped in memory
0x1 : 1
One bank (bank 0)
0x2 : 2
Double bank (Ping-Pong: bank0/bank1)
0x3 : 3
Triple bank (bank0/bank1/bank2)
End of enumeration elements list.
NB_TRANS : Number Of Transaction per Microframe
bits : 8 - 9 (2 bit)
access : read-write
EPT_MAPD : Endpoint Mapped
bits : 31 - 31 (1 bit)
access : read-write
UDPHS Endpoint Control Enable Register (endpoint = 15)
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Enable Register (endpoint = 15)
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Enable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Send/Short Packet Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 15)
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
NYET_DIS : NYET Enable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY : TX Packet Ready Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
RX_SETUP : Received SETUP Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Disable Register (endpoint = 15)
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_DISABL : Endpoint Disable
bits : 0 - 0 (1 bit)
access : write-only
AUTO_VALID : Packet Auto-Valid Disable
bits : 1 - 1 (1 bit)
access : write-only
INTDIS_DMA : Interrupts Disable DMA
bits : 3 - 3 (1 bit)
access : write-only
DATAX_RX : DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : write-only
MDATA_RX : MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : write-only
ERR_OVFLW : Overflow Error Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : bank flush error Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
BUSY_BANK : Busy Bank Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
SHRT_PCKT : Short Packet Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
UDPHS Endpoint Control Register (endpoint = 15)
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
NYET_DIS : NYET Disable (Only for High Speed Bulk OUT endpoints)
bits : 4 - 4 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAKIN Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAKOUT Interrupt Enabled
bits : 15 - 15 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Control Register (endpoint = 15)
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
EPT_ENABL : Endpoint Enable
bits : 0 - 0 (1 bit)
access : read-only
AUTO_VALID : Packet Auto-Valid Enabled
bits : 1 - 1 (1 bit)
access : read-only
INTDIS_DMA : Interrupt Disables DMA
bits : 3 - 3 (1 bit)
access : read-only
DATAX_RX : DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 6 - 6 (1 bit)
access : read-only
MDATA_RX : MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
bits : 7 - 7 (1 bit)
access : read-only
ERR_OVFLW : Overflow Error Interrupt Enabled
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data Interrupt Enabled
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete Interrupt Enabled
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error Interrupt Enabled
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow Interrupt Enabled
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : ISO CRC Error/Number of Transaction Error Interrupt Enabled
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error Interrupt Enabled
bits : 14 - 14 (1 bit)
access : read-only
BUSY_BANK : Busy Bank Interrupt Enabled
bits : 18 - 18 (1 bit)
access : read-only
SHRT_PCKT : Short Packet Interrupt Enabled
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Set Status Register (endpoint = 15)
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Set
bits : 5 - 5 (1 bit)
access : write-only
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Set Status Register (endpoint = 15)
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
RXRDY_TXKL : KILL Bank Set (for IN Endpoint)
bits : 9 - 9 (1 bit)
access : write-only
TXRDY_TRER : TX Packet Ready Set
bits : 11 - 11 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 15)
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request Clear
bits : 5 - 5 (1 bit)
access : write-only
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
RX_SETUP : Received SETUP Clear
bits : 12 - 12 (1 bit)
access : write-only
STALL_SNT : Stall Sent Clear
bits : 13 - 13 (1 bit)
access : write-only
NAK_IN : NAKIN Clear
bits : 14 - 14 (1 bit)
access : write-only
NAK_OUT : NAKOUT Clear
bits : 15 - 15 (1 bit)
access : write-only
UDPHS Endpoint Clear Status Register (endpoint = 15)
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ : Data Toggle Clear
bits : 6 - 6 (1 bit)
access : write-only
RXRDY_TXKL : Received OUT Data Clear
bits : 9 - 9 (1 bit)
access : write-only
TX_COMPLT : Transmitted IN Data Complete Clear
bits : 10 - 10 (1 bit)
access : write-only
ERR_FL_ISO : Error Flow Clear
bits : 12 - 12 (1 bit)
access : write-only
ERR_CRC_NTR : Number of Transaction Error Clear
bits : 13 - 13 (1 bit)
access : write-only
ERR_FLUSH : Bank Flush Error Clear
bits : 14 - 14 (1 bit)
access : write-only
UDPHS Endpoint Status Register (endpoint = 15)
address_offset : 0x2FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRCESTALL : Stall Handshake Request
bits : 5 - 5 (1 bit)
access : read-only
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Reserved for High Bandwidth Isochronous Endpoint
0x3 : MDATA
Reserved for High Bandwidth Isochronous Endpoint
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY : TX Packet Ready
bits : 11 - 11 (1 bit)
access : read-only
RX_SETUP : Received SETUP
bits : 12 - 12 (1 bit)
access : read-only
STALL_SNT : Stall Sent
bits : 13 - 13 (1 bit)
access : read-only
NAK_IN : NAK IN
bits : 14 - 14 (1 bit)
access : read-only
NAK_OUT : NAK OUT
bits : 15 - 15 (1 bit)
access : read-only
CURBK_CTLDIR : Current Bank/Control Direction
bits : 16 - 17 (2 bit)
access : read-only
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Endpoint Status Register (endpoint = 15)
address_offset : 0x2FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENDPT
reset_Mask : 0x0
TOGGLESQ_STA : Toggle Sequencing
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : DATA0
DATA0
0x1 : DATA1
DATA1
0x2 : DATA2
Data2 (only for High Bandwidth Isochronous Endpoint)
0x3 : MDATA
MData (only for High Bandwidth Isochronous Endpoint)
End of enumeration elements list.
ERR_OVFLW : Overflow Error
bits : 8 - 8 (1 bit)
access : read-only
RXRDY_TXKL : Received OUT Data/KILL Bank
bits : 9 - 9 (1 bit)
access : read-only
TX_COMPLT : Transmitted IN Data Complete
bits : 10 - 10 (1 bit)
access : read-only
TXRDY_TRER : TX Packet Ready/Transaction Error
bits : 11 - 11 (1 bit)
access : read-only
ERR_FL_ISO : Error Flow
bits : 12 - 12 (1 bit)
access : read-only
ERR_CRC_NTR : CRC ISO Error/Number of Transaction Error
bits : 13 - 13 (1 bit)
access : read-only
ERR_FLUSH : Bank Flush Error
bits : 14 - 14 (1 bit)
access : read-only
CURBK : Current Bank
bits : 16 - 17 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Bank 0 (or single bank)
0x1 : BANK1
Bank 1
0x2 : BANK2
Bank 2
End of enumeration elements list.
BUSY_BANK_STA : Busy Bank Number
bits : 18 - 19 (2 bit)
access : read-only
Enumeration:
0x0 : 1BUSYBANK
1 busy bank
0x1 : 2BUSYBANKS
2 busy banks
0x2 : 3BUSYBANKS
3 busy banks
End of enumeration elements list.
BYTE_COUNT : UDPHS Byte Count
bits : 20 - 30 (11 bit)
access : read-only
SHRT_PCKT : Short Packet
bits : 31 - 31 (1 bit)
access : read-only
UDPHS DMA Next Descriptor Address Register (channel = 0)
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
UDPHS DMA Channel Address Register (channel = 0)
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
UDPHS DMA Channel Control Register (channel = 0)
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : (Channel Enable Command)
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable (Command)
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable (Control)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable (Control)
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
UDPHS DMA Channel Status Register (channel = 0)
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
UDPHS DMA Next Descriptor Address Register (channel = 1)
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
UDPHS DMA Channel Address Register (channel = 1)
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
UDPHS DMA Channel Control Register (channel = 1)
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : (Channel Enable Command)
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable (Command)
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable (Control)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable (Control)
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
UDPHS DMA Channel Status Register (channel = 1)
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
UDPHS DMA Next Descriptor Address Register (channel = 2)
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
UDPHS DMA Channel Address Register (channel = 2)
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
UDPHS DMA Channel Control Register (channel = 2)
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : (Channel Enable Command)
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable (Command)
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable (Control)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable (Control)
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
UDPHS DMA Channel Status Register (channel = 2)
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
UDPHS DMA Next Descriptor Address Register (channel = 3)
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
UDPHS DMA Channel Address Register (channel = 3)
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
UDPHS DMA Channel Control Register (channel = 3)
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : (Channel Enable Command)
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable (Command)
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable (Control)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable (Control)
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
UDPHS DMA Channel Status Register (channel = 3)
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
UDPHS DMA Next Descriptor Address Register (channel = 4)
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
UDPHS DMA Channel Address Register (channel = 4)
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
UDPHS DMA Channel Control Register (channel = 4)
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : (Channel Enable Command)
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable (Command)
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable (Control)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable (Control)
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
UDPHS DMA Channel Status Register (channel = 4)
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
UDPHS DMA Next Descriptor Address Register (channel = 5)
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
UDPHS DMA Channel Address Register (channel = 5)
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
UDPHS DMA Channel Control Register (channel = 5)
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : (Channel Enable Command)
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable (Command)
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable (Control)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable (Control)
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
UDPHS DMA Channel Status Register (channel = 5)
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
UDPHS DMA Next Descriptor Address Register (channel = 6)
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
UDPHS DMA Channel Address Register (channel = 6)
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
UDPHS DMA Channel Control Register (channel = 6)
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : (Channel Enable Command)
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable (Command)
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable (Control)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable (Control)
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
UDPHS DMA Channel Status Register (channel = 6)
address_offset : 0x36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
UDPHS Frame Number Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MICRO_FRAME_NUM : Microframe Number
bits : 0 - 2 (3 bit)
access : read-only
FRAME_NUMBER : Frame Number as defined in the Packet Field Formats
bits : 3 - 13 (11 bit)
access : read-only
FNUM_ERR : Frame Number CRC Error
bits : 31 - 31 (1 bit)
access : read-only
UDPHS Test Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPEED_CFG : Speed Configuration
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : NORMAL
Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode
0x2 : HIGH_SPEED
Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose.
0x3 : FULL_SPEED
Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake.
End of enumeration elements list.
TST_J : Test J Mode
bits : 2 - 2 (1 bit)
access : read-write
TST_K : Test K Mode
bits : 3 - 3 (1 bit)
access : read-write
TST_PKT : Test Packet Mode
bits : 4 - 4 (1 bit)
access : read-write
OPMODE2 : OpMode2
bits : 5 - 5 (1 bit)
access : read-write
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