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TWI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

CWGR

SR

IER

IDR

IMR

RHR

THR

MMR

SMR

IADR

WPROT_MODE

WPROT_STATUS


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START STOP MSEN MSDIS SVEN SVDIS QUICK SWRST

START : Send a START Condition
bits : 0 - 0 (1 bit)
access : write-only

STOP : Send a STOP Condition
bits : 1 - 1 (1 bit)
access : write-only

MSEN : TWI Master Mode Enabled
bits : 2 - 2 (1 bit)
access : write-only

MSDIS : TWI Master Mode Disabled
bits : 3 - 3 (1 bit)
access : write-only

SVEN : TWI Slave Mode Enabled
bits : 4 - 4 (1 bit)
access : write-only

SVDIS : TWI Slave Mode Disabled
bits : 5 - 5 (1 bit)
access : write-only

QUICK : SMBUS Quick Command
bits : 6 - 6 (1 bit)
access : write-only

SWRST : Software Reset
bits : 7 - 7 (1 bit)
access : write-only


CWGR

Clock Waveform Generator Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CWGR CWGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLDIV CHDIV CKDIV

CLDIV : Clock Low Divider
bits : 0 - 7 (8 bit)
access : read-write

CHDIV : Clock High Divider
bits : 8 - 15 (8 bit)
access : read-write

CKDIV : Clock Divider
bits : 16 - 18 (3 bit)
access : read-write


SR

Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCOMP RXRDY TXRDY SVREAD SVACC GACC OVRE NACK ARBLST SCLWS EOSACC

TXCOMP : Transmission Completed (automatically set / reset)
bits : 0 - 0 (1 bit)
access : read-only

RXRDY : Receive Holding Register Ready (automatically set / reset)
bits : 1 - 1 (1 bit)
access : read-only

TXRDY : Transmit Holding Register Ready (automatically set / reset)
bits : 2 - 2 (1 bit)
access : read-only

SVREAD : Slave Read (automatically set / reset)
bits : 3 - 3 (1 bit)
access : read-only

SVACC : Slave Access (automatically set / reset)
bits : 4 - 4 (1 bit)
access : read-only

GACC : General Call Access (clear on read)
bits : 5 - 5 (1 bit)
access : read-only

OVRE : Overrun Error (clear on read)
bits : 6 - 6 (1 bit)
access : read-only

NACK : Not Acknowledged (clear on read)
bits : 8 - 8 (1 bit)
access : read-only

ARBLST : Arbitration Lost (clear on read)
bits : 9 - 9 (1 bit)
access : read-only

SCLWS : Clock Wait State (automatically set / reset)
bits : 10 - 10 (1 bit)
access : read-only

EOSACC : End Of Slave Access (clear on read)
bits : 11 - 11 (1 bit)
access : read-only


IER

Interrupt Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCOMP RXRDY TXRDY SVACC GACC OVRE NACK ARBLST SCL_WS EOSACC

TXCOMP : Transmission Completed Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

RXRDY : Receive Holding Register Ready Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

TXRDY : Transmit Holding Register Ready Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

SVACC : Slave Access Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

GACC : General Call Access Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

OVRE : Overrun Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

NACK : Not Acknowledge Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

ARBLST : Arbitration Lost Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

SCL_WS : Clock Wait State Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

EOSACC : End Of Slave Access Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only


IDR

Interrupt Disable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCOMP RXRDY TXRDY SVACC GACC OVRE NACK ARBLST SCL_WS EOSACC

TXCOMP : Transmission Completed Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

RXRDY : Receive Holding Register Ready Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

TXRDY : Transmit Holding Register Ready Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

SVACC : Slave Access Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

GACC : General Call Access Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

OVRE : Overrun Error Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

NACK : Not Acknowledge Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

ARBLST : Arbitration Lost Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

SCL_WS : Clock Wait State Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

EOSACC : End Of Slave Access Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only


IMR

Interrupt Mask Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCOMP RXRDY TXRDY SVACC GACC OVRE NACK ARBLST SCL_WS EOSACC

TXCOMP : Transmission Completed Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

RXRDY : Receive Holding Register Ready Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

TXRDY : Transmit Holding Register Ready Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only

SVACC : Slave Access Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only

GACC : General Call Access Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only

OVRE : Overrun Error Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only

NACK : Not Acknowledge Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only

ARBLST : Arbitration Lost Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only

SCL_WS : Clock Wait State Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only

EOSACC : End Of Slave Access Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-only


RHR

Receive Holding Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RHR RHR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : Master or Slave Receive Holding Data
bits : 0 - 7 (8 bit)
access : read-only


THR

Transmit Holding Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

THR THR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA

TXDATA : Master or Slave Transmit Holding Data
bits : 0 - 7 (8 bit)
access : write-only


MMR

Master Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMR MMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IADRSZ MREAD DADR

IADRSZ : Internal Device Address Size
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No internal device address

0x1 : 1_BYTE

One-byte internal device address

0x2 : 2_BYTE

Two-byte internal device address

0x3 : 3_BYTE

Three-byte internal device address

End of enumeration elements list.

MREAD : Master Read Direction
bits : 12 - 12 (1 bit)
access : read-write

DADR : Device Address
bits : 16 - 22 (7 bit)
access : read-write


SMR

Slave Mode Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMR SMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SADR

SADR : Slave Address
bits : 16 - 22 (7 bit)
access : read-write


IADR

Internal Address Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IADR IADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IADR

IADR : Internal Address
bits : 0 - 23 (24 bit)
access : read-write


WPROT_MODE

Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPROT_MODE WPROT_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPROT SECURITY_CODE

WPROT : Write protection bit
bits : 0 - 0 (1 bit)
access : read-write

SECURITY_CODE : Write protection mode security code
bits : 8 - 31 (24 bit)
access : read-write


WPROT_STATUS

Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPROT_STATUS WPROT_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPROTERR WPROTADDR

WPROTERR : Write Protection Error
bits : 0 - 0 (1 bit)
access : read-only

WPROTADDR : Write Protection Error Address
bits : 8 - 31 (24 bit)
access : read-only



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