\n

EVSYS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

INTENCLR

INTENSET

INTFLAG

CHANNEL

USER

CHSTATUS


CTRL

Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRST GCLKREQ

SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only

GCLKREQ : Generic Clock Requests
bits : 4 - 4 (1 bit)


INTENCLR

Interrupt Enable Clear
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVR0 OVR1 OVR2 OVR3 OVR4 OVR5 OVR6 OVR7 EVD0 EVD1 EVD2 EVD3 EVD4 EVD5 EVD6 EVD7 OVR8 OVR9 OVR10 OVR11 EVD8 EVD9 EVD10 EVD11

OVR0 : Channel 0 Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

OVR1 : Channel 1 Overrun Interrupt Enable
bits : 1 - 1 (1 bit)

OVR2 : Channel 2 Overrun Interrupt Enable
bits : 2 - 2 (1 bit)

OVR3 : Channel 3 Overrun Interrupt Enable
bits : 3 - 3 (1 bit)

OVR4 : Channel 4 Overrun Interrupt Enable
bits : 4 - 4 (1 bit)

OVR5 : Channel 5 Overrun Interrupt Enable
bits : 5 - 5 (1 bit)

OVR6 : Channel 6 Overrun Interrupt Enable
bits : 6 - 6 (1 bit)

OVR7 : Channel 7 Overrun Interrupt Enable
bits : 7 - 7 (1 bit)

EVD0 : Channel 0 Event Detection Interrupt Enable
bits : 8 - 8 (1 bit)

EVD1 : Channel 1 Event Detection Interrupt Enable
bits : 9 - 9 (1 bit)

EVD2 : Channel 2 Event Detection Interrupt Enable
bits : 10 - 10 (1 bit)

EVD3 : Channel 3 Event Detection Interrupt Enable
bits : 11 - 11 (1 bit)

EVD4 : Channel 4 Event Detection Interrupt Enable
bits : 12 - 12 (1 bit)

EVD5 : Channel 5 Event Detection Interrupt Enable
bits : 13 - 13 (1 bit)

EVD6 : Channel 6 Event Detection Interrupt Enable
bits : 14 - 14 (1 bit)

EVD7 : Channel 7 Event Detection Interrupt Enable
bits : 15 - 15 (1 bit)

OVR8 : Channel 8 Overrun Interrupt Enable
bits : 16 - 16 (1 bit)

OVR9 : Channel 9 Overrun Interrupt Enable
bits : 17 - 17 (1 bit)

OVR10 : Channel 10 Overrun Interrupt Enable
bits : 18 - 18 (1 bit)

OVR11 : Channel 11 Overrun Interrupt Enable
bits : 19 - 19 (1 bit)

EVD8 : Channel 8 Event Detection Interrupt Enable
bits : 24 - 24 (1 bit)

EVD9 : Channel 9 Event Detection Interrupt Enable
bits : 25 - 25 (1 bit)

EVD10 : Channel 10 Event Detection Interrupt Enable
bits : 26 - 26 (1 bit)

EVD11 : Channel 11 Event Detection Interrupt Enable
bits : 27 - 27 (1 bit)


INTENSET

Interrupt Enable Set
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVR0 OVR1 OVR2 OVR3 OVR4 OVR5 OVR6 OVR7 EVD0 EVD1 EVD2 EVD3 EVD4 EVD5 EVD6 EVD7 OVR8 OVR9 OVR10 OVR11 EVD8 EVD9 EVD10 EVD11

OVR0 : Channel 0 Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

OVR1 : Channel 1 Overrun Interrupt Enable
bits : 1 - 1 (1 bit)

OVR2 : Channel 2 Overrun Interrupt Enable
bits : 2 - 2 (1 bit)

OVR3 : Channel 3 Overrun Interrupt Enable
bits : 3 - 3 (1 bit)

OVR4 : Channel 4 Overrun Interrupt Enable
bits : 4 - 4 (1 bit)

OVR5 : Channel 5 Overrun Interrupt Enable
bits : 5 - 5 (1 bit)

OVR6 : Channel 6 Overrun Interrupt Enable
bits : 6 - 6 (1 bit)

OVR7 : Channel 7 Overrun Interrupt Enable
bits : 7 - 7 (1 bit)

EVD0 : Channel 0 Event Detection Interrupt Enable
bits : 8 - 8 (1 bit)

EVD1 : Channel 1 Event Detection Interrupt Enable
bits : 9 - 9 (1 bit)

EVD2 : Channel 2 Event Detection Interrupt Enable
bits : 10 - 10 (1 bit)

EVD3 : Channel 3 Event Detection Interrupt Enable
bits : 11 - 11 (1 bit)

EVD4 : Channel 4 Event Detection Interrupt Enable
bits : 12 - 12 (1 bit)

EVD5 : Channel 5 Event Detection Interrupt Enable
bits : 13 - 13 (1 bit)

EVD6 : Channel 6 Event Detection Interrupt Enable
bits : 14 - 14 (1 bit)

EVD7 : Channel 7 Event Detection Interrupt Enable
bits : 15 - 15 (1 bit)

OVR8 : Channel 8 Overrun Interrupt Enable
bits : 16 - 16 (1 bit)

OVR9 : Channel 9 Overrun Interrupt Enable
bits : 17 - 17 (1 bit)

OVR10 : Channel 10 Overrun Interrupt Enable
bits : 18 - 18 (1 bit)

OVR11 : Channel 11 Overrun Interrupt Enable
bits : 19 - 19 (1 bit)

EVD8 : Channel 8 Event Detection Interrupt Enable
bits : 24 - 24 (1 bit)

EVD9 : Channel 9 Event Detection Interrupt Enable
bits : 25 - 25 (1 bit)

EVD10 : Channel 10 Event Detection Interrupt Enable
bits : 26 - 26 (1 bit)

EVD11 : Channel 11 Event Detection Interrupt Enable
bits : 27 - 27 (1 bit)


INTFLAG

Interrupt Flag Status and Clear
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVR0 OVR1 OVR2 OVR3 OVR4 OVR5 OVR6 OVR7 EVD0 EVD1 EVD2 EVD3 EVD4 EVD5 EVD6 EVD7 OVR8 OVR9 OVR10 OVR11 EVD8 EVD9 EVD10 EVD11

OVR0 : Channel 0 Overrun
bits : 0 - 0 (1 bit)

OVR1 : Channel 1 Overrun
bits : 1 - 1 (1 bit)

OVR2 : Channel 2 Overrun
bits : 2 - 2 (1 bit)

OVR3 : Channel 3 Overrun
bits : 3 - 3 (1 bit)

OVR4 : Channel 4 Overrun
bits : 4 - 4 (1 bit)

OVR5 : Channel 5 Overrun
bits : 5 - 5 (1 bit)

OVR6 : Channel 6 Overrun
bits : 6 - 6 (1 bit)

OVR7 : Channel 7 Overrun
bits : 7 - 7 (1 bit)

EVD0 : Channel 0 Event Detection
bits : 8 - 8 (1 bit)

EVD1 : Channel 1 Event Detection
bits : 9 - 9 (1 bit)

EVD2 : Channel 2 Event Detection
bits : 10 - 10 (1 bit)

EVD3 : Channel 3 Event Detection
bits : 11 - 11 (1 bit)

EVD4 : Channel 4 Event Detection
bits : 12 - 12 (1 bit)

EVD5 : Channel 5 Event Detection
bits : 13 - 13 (1 bit)

EVD6 : Channel 6 Event Detection
bits : 14 - 14 (1 bit)

EVD7 : Channel 7 Event Detection
bits : 15 - 15 (1 bit)

OVR8 : Channel 8 Overrun
bits : 16 - 16 (1 bit)

OVR9 : Channel 9 Overrun
bits : 17 - 17 (1 bit)

OVR10 : Channel 10 Overrun
bits : 18 - 18 (1 bit)

OVR11 : Channel 11 Overrun
bits : 19 - 19 (1 bit)

EVD8 : Channel 8 Event Detection
bits : 24 - 24 (1 bit)

EVD9 : Channel 9 Event Detection
bits : 25 - 25 (1 bit)

EVD10 : Channel 10 Event Detection
bits : 26 - 26 (1 bit)

EVD11 : Channel 11 Event Detection
bits : 27 - 27 (1 bit)


CHANNEL

Channel
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL SWEVT EVGEN PATH EDGSEL

CHANNEL : Channel Selection
bits : 0 - 3 (4 bit)

SWEVT : Software Event
bits : 8 - 8 (1 bit)

EVGEN : Event Generator Selection
bits : 16 - 22 (7 bit)

PATH : Path Selection
bits : 24 - 25 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 26 - 27 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.


USER

User Multiplexer
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER USER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USER CHANNEL

USER : User Multiplexer Selection
bits : 0 - 4 (5 bit)

CHANNEL : Channel Event Selection
bits : 8 - 12 (5 bit)

Enumeration: CHANNELSelect

0x0 : 0

No Channel Output Selected

End of enumeration elements list.


CHSTATUS

Channel Status
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS CHSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USRRDY0 USRRDY1 USRRDY2 USRRDY3 USRRDY4 USRRDY5 USRRDY6 USRRDY7 CHBUSY0 CHBUSY1 CHBUSY2 CHBUSY3 CHBUSY4 CHBUSY5 CHBUSY6 CHBUSY7 USRRDY8 USRRDY9 USRRDY10 USRRDY11 CHBUSY8 CHBUSY9 CHBUSY10 CHBUSY11

USRRDY0 : Channel 0 User Ready
bits : 0 - 0 (1 bit)
access : read-only

USRRDY1 : Channel 1 User Ready
bits : 1 - 1 (1 bit)
access : read-only

USRRDY2 : Channel 2 User Ready
bits : 2 - 2 (1 bit)
access : read-only

USRRDY3 : Channel 3 User Ready
bits : 3 - 3 (1 bit)
access : read-only

USRRDY4 : Channel 4 User Ready
bits : 4 - 4 (1 bit)
access : read-only

USRRDY5 : Channel 5 User Ready
bits : 5 - 5 (1 bit)
access : read-only

USRRDY6 : Channel 6 User Ready
bits : 6 - 6 (1 bit)
access : read-only

USRRDY7 : Channel 7 User Ready
bits : 7 - 7 (1 bit)
access : read-only

CHBUSY0 : Channel 0 Busy
bits : 8 - 8 (1 bit)
access : read-only

CHBUSY1 : Channel 1 Busy
bits : 9 - 9 (1 bit)
access : read-only

CHBUSY2 : Channel 2 Busy
bits : 10 - 10 (1 bit)
access : read-only

CHBUSY3 : Channel 3 Busy
bits : 11 - 11 (1 bit)
access : read-only

CHBUSY4 : Channel 4 Busy
bits : 12 - 12 (1 bit)
access : read-only

CHBUSY5 : Channel 5 Busy
bits : 13 - 13 (1 bit)
access : read-only

CHBUSY6 : Channel 6 Busy
bits : 14 - 14 (1 bit)
access : read-only

CHBUSY7 : Channel 7 Busy
bits : 15 - 15 (1 bit)
access : read-only

USRRDY8 : Channel 8 User Ready
bits : 16 - 16 (1 bit)
access : read-only

USRRDY9 : Channel 9 User Ready
bits : 17 - 17 (1 bit)
access : read-only

USRRDY10 : Channel 10 User Ready
bits : 18 - 18 (1 bit)
access : read-only

USRRDY11 : Channel 11 User Ready
bits : 19 - 19 (1 bit)
access : read-only

CHBUSY8 : Channel 8 Busy
bits : 24 - 24 (1 bit)
access : read-only

CHBUSY9 : Channel 9 Busy
bits : 25 - 25 (1 bit)
access : read-only

CHBUSY10 : Channel 10 Busy
bits : 26 - 26 (1 bit)
access : read-only

CHBUSY11 : Channel 11 Busy
bits : 27 - 27 (1 bit)
access : read-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.