\n
address_offset : 0x0 Bytes (0x0)
size : 0x298 byte (0x0)
mem_usage : registers
protection : not protected
RIDR register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PUBMNR : PUBMNR
bits : 0 - 3 (4 bit)
access : read-only
PUBMDR : PUBMDR
bits : 4 - 7 (4 bit)
access : read-only
PUBMJR : PUBMJR
bits : 8 - 11 (4 bit)
access : read-only
PHYMNR : PHYMNR
bits : 12 - 15 (4 bit)
access : read-only
PHYMDR : PHYMDR
bits : 16 - 19 (4 bit)
access : read-only
PHYMJR : PHYMJR
bits : 20 - 23 (4 bit)
access : read-only
UDRID : UDRID
bits : 24 - 31 (8 bit)
access : read-only
DLLGCR register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRES : DRES
bits : 0 - 1 (2 bit)
access : read-write
IPUMP : IPUMP
bits : 2 - 4 (3 bit)
access : read-write
TESTEN : TESTEN
bits : 5 - 5 (1 bit)
access : read-write
DTC : DTC
bits : 6 - 8 (3 bit)
access : read-write
ATC : ATC
bits : 9 - 10 (2 bit)
access : read-write
TESTSW : TESTSW
bits : 11 - 11 (1 bit)
access : read-write
MBIAS : MBIAS
bits : 12 - 19 (8 bit)
access : read-write
SBIAS2_0 : SBIAS2_0
bits : 20 - 22 (3 bit)
access : read-write
BPS200 : BPS200
bits : 23 - 23 (1 bit)
access : read-write
SBIAS5_3 : SBIAS5_3
bits : 24 - 26 (3 bit)
access : read-write
FDTRMSL : FDTRMSL
bits : 27 - 28 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Nominal delay
0x1 : B_0x1
Nominal delay less 10
0x2 : B_0x2
Nominal delay more 10
0x3 : B_0x3
Nominal delay more 20
End of enumeration elements list.
LOCKDET : LOCKDET
bits : 29 - 29 (1 bit)
access : read-write
DLLRSVD2 : DLLRSVD2
bits : 30 - 31 (2 bit)
access : read-write
BISTRR register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BINST : BINST
bits : 0 - 2 (3 bit)
access : read-write
BMODE : BMODE
bits : 3 - 3 (1 bit)
access : read-write
BINF : BINF
bits : 4 - 4 (1 bit)
access : read-write
NFAIL : NFAIL
bits : 5 - 12 (8 bit)
access : read-write
BSCONF : BSCONF
bits : 13 - 13 (1 bit)
access : read-write
BDXEN : BDXEN
bits : 14 - 14 (1 bit)
access : read-write
BACEN : BACEN
bits : 15 - 15 (1 bit)
access : read-write
BDMEN : BDMEN
bits : 16 - 16 (1 bit)
access : read-write
BDPAT : BDPAT
bits : 17 - 18 (2 bit)
access : read-write
BDXSEL : BDXSEL
bits : 19 - 22 (4 bit)
access : read-write
BCKSEL : BCKSEL
bits : 23 - 25 (3 bit)
access : read-write
BISTMSKR0 register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AMSK : AMSK
bits : 0 - 15 (16 bit)
access : read-write
BAMSK : BAMSK
bits : 16 - 18 (3 bit)
access : read-write
WEMSK : WEMSK
bits : 19 - 19 (1 bit)
access : read-write
CKEMSK : CKEMSK
bits : 20 - 23 (4 bit)
access : read-write
CSMSK : CSMSK
bits : 24 - 27 (4 bit)
access : read-write
ODTMSK : ODTMSK
bits : 28 - 31 (4 bit)
access : read-write
BISTMSKR1 register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DQMSK : DQMSK
bits : 0 - 15 (16 bit)
access : read-write
DMMSK : DMMSK
bits : 16 - 17 (2 bit)
access : read-write
RASMSK : RASMSK
bits : 18 - 18 (1 bit)
access : read-write
CASMSK : CASMSK
bits : 19 - 19 (1 bit)
access : read-write
PARMSK : PARMSK
bits : 30 - 30 (1 bit)
access : read-write
TPDMASK : TPDMASK
bits : 31 - 31 (1 bit)
access : read-write
BISTWCR register
address_offset : 0x10C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BWCNT : BWCNT
bits : 0 - 15 (16 bit)
access : read-write
BISTLSR register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BISTLSR : BISTLSR
bits : 0 - 31 (32 bit)
access : read-write
BISTAR0 register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCOL : BCOL
bits : 0 - 11 (12 bit)
access : read-write
BROW : BROW
bits : 12 - 27 (16 bit)
access : read-write
BBANK : BBANK
bits : 28 - 31 (4 bit)
access : read-write
BISTAR1 register
address_offset : 0x118 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRANK : BRANK
bits : 0 - 1 (2 bit)
access : read-write
BMRANK : BMRANK
bits : 2 - 3 (2 bit)
access : read-write
BAINC : BAINC
bits : 4 - 15 (12 bit)
access : read-write
BISTAR2 register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BMCOL : BMCOL
bits : 0 - 11 (12 bit)
access : read-write
BMROW : BMROW
bits : 12 - 27 (16 bit)
access : read-write
BMBANK : BMBANK
bits : 28 - 31 (4 bit)
access : read-write
BISTUDPR register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUDP0 : BUDP0
bits : 0 - 15 (16 bit)
access : read-write
BUDP1 : BUDP1
bits : 16 - 31 (16 bit)
access : read-write
BISTGSR register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BDONE : BDONE
bits : 0 - 0 (1 bit)
access : read-only
BACERR : BACERR
bits : 1 - 1 (1 bit)
access : read-only
BDXERR : BDXERR
bits : 2 - 2 (1 bit)
access : read-only
PARBER : PARBER
bits : 20 - 21 (2 bit)
access : read-only
TPDBER : TPDBER
bits : 22 - 23 (2 bit)
access : read-only
DMBER : DMBER
bits : 24 - 27 (4 bit)
access : read-only
RASBER : RASBER
bits : 28 - 29 (2 bit)
access : read-only
CASBER : CASBER
bits : 30 - 31 (2 bit)
access : read-only
BISTWER register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACWER : ACWER
bits : 0 - 15 (16 bit)
access : read-only
DXWER : DXWER
bits : 16 - 31 (16 bit)
access : read-only
BISTBER0 register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ABER : ABER
bits : 0 - 31 (32 bit)
access : read-only
BISTBER1 register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BABER : BABER
bits : 0 - 5 (6 bit)
access : read-only
WEBER : WEBER
bits : 6 - 7 (2 bit)
access : read-only
CKEBER : CKEBER
bits : 8 - 15 (8 bit)
access : read-only
CSBER : CSBER
bits : 16 - 23 (8 bit)
access : read-only
ODTBER : ODTBER
bits : 24 - 31 (8 bit)
access : read-only
BISTBER2 register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DQBER : DQBER
bits : 0 - 31 (32 bit)
access : read-only
BISTWCSR register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACWCNT : ACWCNT
bits : 0 - 15 (16 bit)
access : read-only
DXWCNT : DXWCNT
bits : 16 - 31 (16 bit)
access : read-only
BISTFWR0 register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AWEBS : AWEBS
bits : 0 - 15 (16 bit)
access : read-only
BAWEBS : BAWEBS
bits : 16 - 18 (3 bit)
access : read-only
WEWEBS : WEWEBS
bits : 19 - 19 (1 bit)
access : read-only
CKEWEBS : CKEWEBS
bits : 20 - 23 (4 bit)
access : read-only
CSWEBS : CSWEBS
bits : 24 - 27 (4 bit)
access : read-only
ODTWEBS : ODTWEBS
bits : 28 - 31 (4 bit)
access : read-only
ACDLLCR register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MFBDLY : MFBDLY
bits : 6 - 8 (3 bit)
access : read-write
MFWDLY : MFWDLY
bits : 9 - 11 (3 bit)
access : read-write
ATESTEN : ATESTEN
bits : 18 - 18 (1 bit)
access : read-write
DLLSRST : DLLSRST
bits : 30 - 30 (1 bit)
access : read-write
DLLDIS : DLLDIS
bits : 31 - 31 (1 bit)
access : read-write
BISTFWR1 register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DQWEBS : DQWEBS
bits : 0 - 15 (16 bit)
access : read-only
DMWEBS : DMWEBS
bits : 16 - 17 (2 bit)
access : read-only
RASWEBS : RASWEBS
bits : 18 - 18 (1 bit)
access : read-only
CASWEBS : CASWEBS
bits : 19 - 19 (1 bit)
access : read-only
PARWEBS : PARWEBS
bits : 30 - 30 (1 bit)
access : read-only
TPDWEBS : TPDWEBS
bits : 31 - 31 (1 bit)
access : read-only
General Purpose Register 0
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPR0 : GPR0
bits : 0 - 31 (32 bit)
access : read-write
General Purpose Register register 1
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPR1 : GPR1
bits : 0 - 31 (32 bit)
access : read-write
PTR0 register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDLLSRST : TDLLSRST
bits : 0 - 5 (6 bit)
access : read-write
TDLLLOCK : TDLLLOCK
bits : 6 - 17 (12 bit)
access : read-write
TITMSRST : TITMSRST
bits : 18 - 21 (4 bit)
access : read-write
ZQ0CR0 register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZDATA : ZDATA
bits : 0 - 19 (20 bit)
access : read-write
ZDEN : ZDEN
bits : 28 - 28 (1 bit)
access : read-write
ZCALBYP : ZCALBYP
bits : 29 - 29 (1 bit)
access : read-write
ZCAL : ZCAL
bits : 30 - 30 (1 bit)
access : read-write
ZQPD : ZQPD
bits : 31 - 31 (1 bit)
access : read-write
ZQ0CR1 register
address_offset : 0x184 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZPROG : ZPROG
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0x1 : B_0x1
120ohm
0x5 : B_0x5
60ohm
0x8 : B_0x8
40ohm
0xB : B_0xB
40ohm
0xD : B_0xD
34ohm
End of enumeration elements list.
ZQ0SR0 register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ZCTRL : ZCTRL
bits : 0 - 19 (20 bit)
access : read-only
ZERR : ZERR
bits : 30 - 30 (1 bit)
access : read-only
ZDONE : ZDONE
bits : 31 - 31 (1 bit)
access : read-only
ZQ0SR1 register
address_offset : 0x18C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ZPD : ZPD
bits : 0 - 1 (2 bit)
access : read-only
ZPU : ZPU
bits : 2 - 3 (2 bit)
access : read-only
OPD : OPD
bits : 4 - 5 (2 bit)
access : read-only
OPU : OPU
bits : 6 - 7 (2 bit)
access : read-only
PTR1 register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDINIT0 : TDINIT0
bits : 0 - 18 (19 bit)
access : read-write
TDINIT1 : TDINIT1
bits : 19 - 26 (8 bit)
access : read-write
DX 0 GCR register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DXEN : DXEN
bits : 0 - 0 (1 bit)
access : read-write
DQSODT : DQSODT
bits : 1 - 1 (1 bit)
access : read-write
DQODT : DQODT
bits : 2 - 2 (1 bit)
access : read-write
DXIOM : DXIOM
bits : 3 - 3 (1 bit)
access : read-write
DXPDD : DXPDD
bits : 4 - 4 (1 bit)
access : read-write
DXPDR : DXPDR
bits : 5 - 5 (1 bit)
access : read-write
DQSRPD : DQSRPD
bits : 6 - 6 (1 bit)
access : read-write
DSEN : DSEN
bits : 7 - 8 (2 bit)
access : read-write
DQSRTT : DQSRTT
bits : 9 - 9 (1 bit)
access : read-write
DQRTT : DQRTT
bits : 10 - 10 (1 bit)
access : read-write
RTTOH : RTTOH
bits : 11 - 12 (2 bit)
access : read-write
RTTOAL : RTTOAL
bits : 13 - 13 (1 bit)
access : read-write
R0RVSL : R0RVSL
bits : 14 - 16 (3 bit)
access : read-write
DX 0 GSR0 register
address_offset : 0x1C4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTDONE : DTDONE
bits : 0 - 0 (1 bit)
access : read-only
DTERR : DTERR
bits : 4 - 4 (1 bit)
access : read-only
DTIERR : DTIERR
bits : 8 - 8 (1 bit)
access : read-only
DTPASS : DTPASS
bits : 13 - 15 (3 bit)
access : read-only
DX 0 GSR1 register
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DFTERR : DFTERR
bits : 0 - 0 (1 bit)
access : read-only
DQSDFT : DQSDFT
bits : 4 - 5 (2 bit)
access : read-only
RVERR : RVERR
bits : 12 - 12 (1 bit)
access : read-only
RVIERR : RVIERR
bits : 16 - 16 (1 bit)
access : read-only
RVPASS : RVPASS
bits : 20 - 22 (3 bit)
access : read-only
DX 0 DLLCR register
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFBDLY : SFBDLY
bits : 0 - 2 (3 bit)
access : read-write
SFWDLY : SFWDLY
bits : 3 - 5 (3 bit)
access : read-write
MFBDLY : MFBDLY
bits : 6 - 8 (3 bit)
access : read-write
MFWDLY : MFWDLY
bits : 9 - 11 (3 bit)
access : read-write
SSTART : SSTART
bits : 12 - 13 (2 bit)
access : read-write
SDPHASE : SDPHASE
bits : 14 - 17 (4 bit)
access : read-write
ATESTEN : ATESTEN
bits : 18 - 18 (1 bit)
access : read-write
SDLBMODE : SDLBMODE
bits : 19 - 19 (1 bit)
access : read-write
DLLSRST : DLLSRST
bits : 30 - 30 (1 bit)
access : read-write
DLLDIS : DLLDIS
bits : 31 - 31 (1 bit)
access : read-write
DX 0 DQTR register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DQDLY0 : DQDLY0
bits : 0 - 3 (4 bit)
access : read-write
DQDLY1 : DQDLY1
bits : 4 - 7 (4 bit)
access : read-write
DQDLY2 : DQDLY2
bits : 8 - 11 (4 bit)
access : read-write
DQDLY3 : DQDLY3
bits : 12 - 15 (4 bit)
access : read-write
DQDLY4 : DQDLY4
bits : 16 - 19 (4 bit)
access : read-write
DQDLY5 : DQDLY5
bits : 20 - 23 (4 bit)
access : read-write
DQDLY6 : DQDLY6
bits : 24 - 27 (4 bit)
access : read-write
DQDLY7 : DQDLY7
bits : 28 - 31 (4 bit)
access : read-write
DX 0 DQSTR register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R0DGSL : R0DGSL
bits : 0 - 2 (3 bit)
access : read-write
R0DGPS : R0DGPS
bits : 12 - 13 (2 bit)
access : read-write
DQSDLY : DQSDLY
bits : 20 - 22 (3 bit)
access : read-write
DQSNDLY : DQSNDLY
bits : 23 - 25 (3 bit)
access : read-write
DMDLY : DMDLY
bits : 26 - 29 (4 bit)
access : read-write
PTR2 register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDINIT2 : TDINIT2
bits : 0 - 16 (17 bit)
access : read-write
TDINIT3 : TDINIT3
bits : 17 - 26 (10 bit)
access : read-write
DX 1 GCR register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DXEN : DXEN
bits : 0 - 0 (1 bit)
access : read-write
DQSODT : DQSODT
bits : 1 - 1 (1 bit)
access : read-write
DQODT : DQODT
bits : 2 - 2 (1 bit)
access : read-write
DXIOM : DXIOM
bits : 3 - 3 (1 bit)
access : read-write
DXPDD : DXPDD
bits : 4 - 4 (1 bit)
access : read-write
DXPDR : DXPDR
bits : 5 - 5 (1 bit)
access : read-write
DQSRPD : DQSRPD
bits : 6 - 6 (1 bit)
access : read-write
DSEN : DSEN
bits : 7 - 8 (2 bit)
access : read-write
DQSRTT : DQSRTT
bits : 9 - 9 (1 bit)
access : read-write
DQRTT : DQRTT
bits : 10 - 10 (1 bit)
access : read-write
RTTOH : RTTOH
bits : 11 - 12 (2 bit)
access : read-write
RTTOAL : RTTOAL
bits : 13 - 13 (1 bit)
access : read-write
R0RVSL : R0RVSL
bits : 14 - 16 (3 bit)
access : read-write
DX 1 GSR0 register
address_offset : 0x204 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTDONE : DTDONE
bits : 0 - 0 (1 bit)
access : read-only
DTERR : DTERR
bits : 4 - 4 (1 bit)
access : read-only
DTIERR : DTIERR
bits : 8 - 8 (1 bit)
access : read-only
DTPASS : DTPASS
bits : 13 - 15 (3 bit)
access : read-only
DX 1 GSR1 register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DFTERR : DFTERR
bits : 0 - 0 (1 bit)
access : read-only
DQSDFT : DQSDFT
bits : 4 - 5 (2 bit)
access : read-only
RVERR : RVERR
bits : 12 - 12 (1 bit)
access : read-only
RVIERR : RVIERR
bits : 16 - 16 (1 bit)
access : read-only
RVPASS : RVPASS
bits : 20 - 22 (3 bit)
access : read-only
DX 1 DLLCR register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFBDLY : SFBDLY
bits : 0 - 2 (3 bit)
access : read-write
SFWDLY : SFWDLY
bits : 3 - 5 (3 bit)
access : read-write
MFBDLY : MFBDLY
bits : 6 - 8 (3 bit)
access : read-write
MFWDLY : MFWDLY
bits : 9 - 11 (3 bit)
access : read-write
SSTART : SSTART
bits : 12 - 13 (2 bit)
access : read-write
SDPHASE : SDPHASE
bits : 14 - 17 (4 bit)
access : read-write
ATESTEN : ATESTEN
bits : 18 - 18 (1 bit)
access : read-write
SDLBMODE : SDLBMODE
bits : 19 - 19 (1 bit)
access : read-write
DLLSRST : DLLSRST
bits : 30 - 30 (1 bit)
access : read-write
DLLDIS : DLLDIS
bits : 31 - 31 (1 bit)
access : read-write
DX 1 DQTR register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DQDLY0 : DQDLY0
bits : 0 - 3 (4 bit)
access : read-write
DQDLY1 : DQDLY1
bits : 4 - 7 (4 bit)
access : read-write
DQDLY2 : DQDLY2
bits : 8 - 11 (4 bit)
access : read-write
DQDLY3 : DQDLY3
bits : 12 - 15 (4 bit)
access : read-write
DQDLY4 : DQDLY4
bits : 16 - 19 (4 bit)
access : read-write
DQDLY5 : DQDLY5
bits : 20 - 23 (4 bit)
access : read-write
DQDLY6 : DQDLY6
bits : 24 - 27 (4 bit)
access : read-write
DQDLY7 : DQDLY7
bits : 28 - 31 (4 bit)
access : read-write
DX 1 DQSTR register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R0DGSL : R0DGSL
bits : 0 - 2 (3 bit)
access : read-write
R0DGPS : R0DGPS
bits : 12 - 13 (2 bit)
access : read-write
DQSDLY : DQSDLY
bits : 20 - 22 (3 bit)
access : read-write
DQSNDLY : DQSNDLY
bits : 23 - 25 (3 bit)
access : read-write
DMDLY : DMDLY
bits : 26 - 29 (4 bit)
access : read-write
ACIOCR register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACIOM : ACIOM
bits : 0 - 0 (1 bit)
access : read-write
ACOE : ACOE
bits : 1 - 1 (1 bit)
access : read-write
ACODT : ACODT
bits : 2 - 2 (1 bit)
access : read-write
ACPDD : ACPDD
bits : 3 - 3 (1 bit)
access : read-write
ACPDR : ACPDR
bits : 4 - 4 (1 bit)
access : read-write
CKODT : CKODT
bits : 5 - 7 (3 bit)
access : read-write
CKPDD : CKPDD
bits : 8 - 10 (3 bit)
access : read-write
CKPDR : CKPDR
bits : 11 - 13 (3 bit)
access : read-write
RANKODT : RANKODT
bits : 14 - 14 (1 bit)
access : read-write
CSPDD : CSPDD
bits : 18 - 18 (1 bit)
access : read-write
RANKPDR : RANKPDR
bits : 22 - 22 (1 bit)
access : read-write
RSTODT : RSTODT
bits : 26 - 26 (1 bit)
access : read-write
RSTPDD : RSTPDD
bits : 27 - 27 (1 bit)
access : read-write
RSTPDR : RSTPDR
bits : 28 - 28 (1 bit)
access : read-write
RSTIOM : RSTIOM
bits : 29 - 29 (1 bit)
access : read-write
ACSR : ACSR
bits : 30 - 31 (2 bit)
access : read-write
DX 2 GCR register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DXEN : DXEN
bits : 0 - 0 (1 bit)
access : read-write
DQSODT : DQSODT
bits : 1 - 1 (1 bit)
access : read-write
DQODT : DQODT
bits : 2 - 2 (1 bit)
access : read-write
DXIOM : DXIOM
bits : 3 - 3 (1 bit)
access : read-write
DXPDD : DXPDD
bits : 4 - 4 (1 bit)
access : read-write
DXPDR : DXPDR
bits : 5 - 5 (1 bit)
access : read-write
DQSRPD : DQSRPD
bits : 6 - 6 (1 bit)
access : read-write
DSEN : DSEN
bits : 7 - 8 (2 bit)
access : read-write
DQSRTT : DQSRTT
bits : 9 - 9 (1 bit)
access : read-write
DQRTT : DQRTT
bits : 10 - 10 (1 bit)
access : read-write
RTTOH : RTTOH
bits : 11 - 12 (2 bit)
access : read-write
RTTOAL : RTTOAL
bits : 13 - 13 (1 bit)
access : read-write
R0RVSL : R0RVSL
bits : 14 - 16 (3 bit)
access : read-write
DX 2 GSR0 register
address_offset : 0x244 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTDONE : DTDONE
bits : 0 - 0 (1 bit)
access : read-only
DTERR : DTERR
bits : 4 - 4 (1 bit)
access : read-only
DTIERR : DTIERR
bits : 8 - 8 (1 bit)
access : read-only
DTPASS : DTPASS
bits : 13 - 15 (3 bit)
access : read-only
DX 2 GSR1 register
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DFTERR : DFTERR
bits : 0 - 0 (1 bit)
access : read-only
DQSDFT : DQSDFT
bits : 4 - 5 (2 bit)
access : read-only
RVERR : RVERR
bits : 12 - 12 (1 bit)
access : read-only
RVIERR : RVIERR
bits : 16 - 16 (1 bit)
access : read-only
RVPASS : RVPASS
bits : 20 - 22 (3 bit)
access : read-only
DX 2 DLLCR register
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFBDLY : SFBDLY
bits : 0 - 2 (3 bit)
access : read-write
SFWDLY : SFWDLY
bits : 3 - 5 (3 bit)
access : read-write
MFBDLY : MFBDLY
bits : 6 - 8 (3 bit)
access : read-write
MFWDLY : MFWDLY
bits : 9 - 11 (3 bit)
access : read-write
SSTART : SSTART
bits : 12 - 13 (2 bit)
access : read-write
SDPHASE : SDPHASE
bits : 14 - 17 (4 bit)
access : read-write
ATESTEN : ATESTEN
bits : 18 - 18 (1 bit)
access : read-write
SDLBMODE : SDLBMODE
bits : 19 - 19 (1 bit)
access : read-write
DLLSRST : DLLSRST
bits : 30 - 30 (1 bit)
access : read-write
DLLDIS : DLLDIS
bits : 31 - 31 (1 bit)
access : read-write
DX 2 DQTR register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DQDLY0 : DQDLY0
bits : 0 - 3 (4 bit)
access : read-write
DQDLY1 : DQDLY1
bits : 4 - 7 (4 bit)
access : read-write
DQDLY2 : DQDLY2
bits : 8 - 11 (4 bit)
access : read-write
DQDLY3 : DQDLY3
bits : 12 - 15 (4 bit)
access : read-write
DQDLY4 : DQDLY4
bits : 16 - 19 (4 bit)
access : read-write
DQDLY5 : DQDLY5
bits : 20 - 23 (4 bit)
access : read-write
DQDLY6 : DQDLY6
bits : 24 - 27 (4 bit)
access : read-write
DQDLY7 : DQDLY7
bits : 28 - 31 (4 bit)
access : read-write
DX 2 DQSTR register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R0DGSL : R0DGSL
bits : 0 - 2 (3 bit)
access : read-write
R0DGPS : R0DGPS
bits : 12 - 13 (2 bit)
access : read-write
DQSDLY : DQSDLY
bits : 20 - 22 (3 bit)
access : read-write
DQSNDLY : DQSNDLY
bits : 23 - 25 (3 bit)
access : read-write
DMDLY : DMDLY
bits : 26 - 29 (4 bit)
access : read-write
DXCCR register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DXODT : DXODT
bits : 0 - 0 (1 bit)
access : read-write
DXIOM : DXIOM
bits : 1 - 1 (1 bit)
access : read-write
DXPDD : DXPDD
bits : 2 - 2 (1 bit)
access : read-write
DXPDR : DXPDR
bits : 3 - 3 (1 bit)
access : read-write
DQSRES : DQSRES
bits : 4 - 7 (4 bit)
access : read-write
DQSNRES : DQSNRES
bits : 8 - 11 (4 bit)
access : read-write
DQSNRST : DQSNRST
bits : 14 - 14 (1 bit)
access : read-write
RVSEL : RVSEL
bits : 15 - 15 (1 bit)
access : read-write
AWDT : AWDT
bits : 16 - 16 (1 bit)
access : read-write
DX 3 GCR register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DXEN : DXEN
bits : 0 - 0 (1 bit)
access : read-write
DQSODT : DQSODT
bits : 1 - 1 (1 bit)
access : read-write
DQODT : DQODT
bits : 2 - 2 (1 bit)
access : read-write
DXIOM : DXIOM
bits : 3 - 3 (1 bit)
access : read-write
DXPDD : DXPDD
bits : 4 - 4 (1 bit)
access : read-write
DXPDR : DXPDR
bits : 5 - 5 (1 bit)
access : read-write
DQSRPD : DQSRPD
bits : 6 - 6 (1 bit)
access : read-write
DSEN : DSEN
bits : 7 - 8 (2 bit)
access : read-write
DQSRTT : DQSRTT
bits : 9 - 9 (1 bit)
access : read-write
DQRTT : DQRTT
bits : 10 - 10 (1 bit)
access : read-write
RTTOH : RTTOH
bits : 11 - 12 (2 bit)
access : read-write
RTTOAL : RTTOAL
bits : 13 - 13 (1 bit)
access : read-write
R0RVSL : R0RVSL
bits : 14 - 16 (3 bit)
access : read-write
DX 3 GSR0 register
address_offset : 0x284 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTDONE : DTDONE
bits : 0 - 0 (1 bit)
access : read-only
DTERR : DTERR
bits : 4 - 4 (1 bit)
access : read-only
DTIERR : DTIERR
bits : 8 - 8 (1 bit)
access : read-only
DTPASS : DTPASS
bits : 13 - 15 (3 bit)
access : read-only
DX 3 GSR1 register
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DFTERR : DFTERR
bits : 0 - 0 (1 bit)
access : read-only
DQSDFT : DQSDFT
bits : 4 - 5 (2 bit)
access : read-only
RVERR : RVERR
bits : 12 - 12 (1 bit)
access : read-only
RVIERR : RVIERR
bits : 16 - 16 (1 bit)
access : read-only
RVPASS : RVPASS
bits : 20 - 22 (3 bit)
access : read-only
DX 3 DLLCR register
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFBDLY : SFBDLY
bits : 0 - 2 (3 bit)
access : read-write
SFWDLY : SFWDLY
bits : 3 - 5 (3 bit)
access : read-write
MFBDLY : MFBDLY
bits : 6 - 8 (3 bit)
access : read-write
MFWDLY : MFWDLY
bits : 9 - 11 (3 bit)
access : read-write
SSTART : SSTART
bits : 12 - 13 (2 bit)
access : read-write
SDPHASE : SDPHASE
bits : 14 - 17 (4 bit)
access : read-write
ATESTEN : ATESTEN
bits : 18 - 18 (1 bit)
access : read-write
SDLBMODE : SDLBMODE
bits : 19 - 19 (1 bit)
access : read-write
DLLSRST : DLLSRST
bits : 30 - 30 (1 bit)
access : read-write
DLLDIS : DLLDIS
bits : 31 - 31 (1 bit)
access : read-write
DX 3 DQTR register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DQDLY0 : DQDLY0
bits : 0 - 3 (4 bit)
access : read-write
DQDLY1 : DQDLY1
bits : 4 - 7 (4 bit)
access : read-write
DQDLY2 : DQDLY2
bits : 8 - 11 (4 bit)
access : read-write
DQDLY3 : DQDLY3
bits : 12 - 15 (4 bit)
access : read-write
DQDLY4 : DQDLY4
bits : 16 - 19 (4 bit)
access : read-write
DQDLY5 : DQDLY5
bits : 20 - 23 (4 bit)
access : read-write
DQDLY6 : DQDLY6
bits : 24 - 27 (4 bit)
access : read-write
DQDLY7 : DQDLY7
bits : 28 - 31 (4 bit)
access : read-write
DX 3 DQSTR register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R0DGSL : R0DGSL
bits : 0 - 2 (3 bit)
access : read-write
R0DGPS : R0DGPS
bits : 12 - 13 (2 bit)
access : read-write
DQSDLY : DQSDLY
bits : 20 - 22 (3 bit)
access : read-write
DQSNDLY : DQSNDLY
bits : 23 - 25 (3 bit)
access : read-write
DMDLY : DMDLY
bits : 26 - 29 (4 bit)
access : read-write
DSGCR register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUREN : PUREN
bits : 0 - 0 (1 bit)
access : read-write
BDISEN : BDISEN
bits : 1 - 1 (1 bit)
access : read-write
ZUEN : ZUEN
bits : 2 - 2 (1 bit)
access : read-write
LPIOPD : LPIOPD
bits : 3 - 3 (1 bit)
access : read-write
LPDLLPD : LPDLLPD
bits : 4 - 4 (1 bit)
access : read-write
DQSGX : DQSGX
bits : 5 - 7 (3 bit)
access : read-write
DQSGE : DQSGE
bits : 8 - 10 (3 bit)
access : read-write
NOBUB : NOBUB
bits : 11 - 11 (1 bit)
access : read-write
FXDLAT : FXDLAT
bits : 12 - 12 (1 bit)
access : read-write
CKEPDD : CKEPDD
bits : 16 - 16 (1 bit)
access : read-write
ODTPDD : ODTPDD
bits : 20 - 20 (1 bit)
access : read-write
NL2PD : NL2PD
bits : 24 - 24 (1 bit)
access : read-write
NL2OE : NL2OE
bits : 25 - 25 (1 bit)
access : read-write
TPDPD : TPDPD
bits : 26 - 26 (1 bit)
access : read-write
TPDOE : TPDOE
bits : 27 - 27 (1 bit)
access : read-write
CKOE : CKOE
bits : 28 - 28 (1 bit)
access : read-write
ODTOE : ODTOE
bits : 29 - 29 (1 bit)
access : read-write
RSTOE : RSTOE
bits : 30 - 30 (1 bit)
access : read-write
CKEOE : CKEOE
bits : 31 - 31 (1 bit)
access : read-write
DCR register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DDRMD : DDRMD
bits : 0 - 2 (3 bit)
access : read-write
DDR8BNK : DDR8BNK
bits : 3 - 3 (1 bit)
access : read-write
PDQ : PDQ
bits : 4 - 6 (3 bit)
access : read-write
MPRDQ : MPRDQ
bits : 7 - 7 (1 bit)
access : read-write
DDRTYPE : DDRTYPE
bits : 8 - 9 (2 bit)
access : read-write
NOSRA : NOSRA
bits : 27 - 27 (1 bit)
access : read-write
DDR2T : DDR2T
bits : 28 - 28 (1 bit)
access : read-write
UDIMM : UDIMM
bits : 29 - 29 (1 bit)
access : read-write
RDIMM : RDIMM
bits : 30 - 30 (1 bit)
access : read-write
TPD : TPD
bits : 31 - 31 (1 bit)
access : read-write
DTPR0 register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMRD : TMRD
bits : 0 - 1 (2 bit)
access : read-write
TRTP : TRTP
bits : 2 - 4 (3 bit)
access : read-write
TWTR : TWTR
bits : 5 - 7 (3 bit)
access : read-write
TRP : TRP
bits : 8 - 11 (4 bit)
access : read-write
TRCD : TRCD
bits : 12 - 15 (4 bit)
access : read-write
TRAS : TRAS
bits : 16 - 20 (5 bit)
access : read-write
TRRD : TRRD
bits : 21 - 24 (4 bit)
access : read-write
TRC : TRC
bits : 25 - 30 (6 bit)
access : read-write
TCCD : TCCD
bits : 31 - 31 (1 bit)
access : read-write
DTPR1 register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TAOND : TAOND
bits : 0 - 1 (2 bit)
access : read-write
TRTW : TRTW
bits : 2 - 2 (1 bit)
access : read-write
TFAW : TFAW
bits : 3 - 8 (6 bit)
access : read-write
TMOD : TMOD
bits : 9 - 10 (2 bit)
access : read-write
TRTODT : TRTODT
bits : 11 - 11 (1 bit)
access : read-write
TRFC : TRFC
bits : 16 - 23 (8 bit)
access : read-write
TDQSCKMIN : TDQSCKMIN
bits : 24 - 26 (3 bit)
access : read-write
TDQSCKMAX : TDQSCKMAX
bits : 27 - 29 (3 bit)
access : read-write
DTPR2 register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXS : TXS
bits : 0 - 9 (10 bit)
access : read-write
TXP : TXP
bits : 10 - 14 (5 bit)
access : read-write
TCKE : TCKE
bits : 15 - 18 (4 bit)
access : read-write
TDLLK : TDLLK
bits : 19 - 28 (10 bit)
access : read-write
PIR register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : INIT
bits : 0 - 0 (1 bit)
access : write-only
DLLSRST : DLLSRST
bits : 1 - 1 (1 bit)
access : write-only
DLLLOCK : DLLLOCK
bits : 2 - 2 (1 bit)
access : write-only
ZCAL : ZCAL
bits : 3 - 3 (1 bit)
access : write-only
ITMSRST : ITMSRST
bits : 4 - 4 (1 bit)
access : write-only
DRAMRST : DRAMRST
bits : 5 - 5 (1 bit)
access : write-only
DRAMINIT : DRAMINIT
bits : 6 - 6 (1 bit)
access : write-only
QSTRN : QSTRN
bits : 7 - 7 (1 bit)
access : write-only
RVTRN : RVTRN
bits : 8 - 8 (1 bit)
access : write-only
ICPC : ICPC
bits : 16 - 16 (1 bit)
access : write-only
DLLBYP : DLLBYP
bits : 17 - 17 (1 bit)
access : write-only
CTLDINIT : CTLDINIT
bits : 18 - 18 (1 bit)
access : write-only
CLRSR : CLRSR
bits : 28 - 28 (1 bit)
access : write-only
LOCKBYP : LOCKBYP
bits : 29 - 29 (1 bit)
access : write-only
ZCALBYP : ZCALBYP
bits : 30 - 30 (1 bit)
access : write-only
INITBYP : INITBYP
bits : 31 - 31 (1 bit)
access : write-only
MR0 register for DDR3
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BL : BL
bits : 0 - 1 (2 bit)
access : read-write
CL0 : CL0
bits : 2 - 2 (1 bit)
access : read-write
BT : BT
bits : 3 - 3 (1 bit)
access : read-write
CL : CL
bits : 4 - 6 (3 bit)
access : read-write
TM : TM
bits : 7 - 7 (1 bit)
access : read-write
DR : DR
bits : 8 - 8 (1 bit)
access : read-write
WR : WR
bits : 9 - 11 (3 bit)
access : read-write
PD : PD
bits : 12 - 12 (1 bit)
access : read-write
RSVD : RSVD
bits : 13 - 15 (3 bit)
access : read-write
MR1 register for LPDDR2
address_offset : 0x44 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BL : BL
bits : 0 - 2 (3 bit)
access : read-write
BT : BT
bits : 3 - 3 (1 bit)
access : read-write
WC : WC
bits : 4 - 4 (1 bit)
access : read-write
NWR : NWR
bits : 5 - 7 (3 bit)
access : read-write
MR2 register for LPDDR2
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RLWL : RLWL
bits : 0 - 2 (3 bit)
access : read-write
MR3 register for DDR3
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPRLOC : MPRLOC
bits : 0 - 1 (2 bit)
access : read-write
MPR : MPR
bits : 2 - 2 (1 bit)
access : read-write
ODTCR register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDODT0 : RDODT0
bits : 0 - 3 (4 bit)
access : read-write
RDODT1 : RDODT1
bits : 4 - 7 (4 bit)
access : read-write
RDODT2 : RDODT2
bits : 8 - 11 (4 bit)
access : read-write
RDODT3 : RDODT3
bits : 12 - 15 (4 bit)
access : read-write
WRODT0 : WRODT0
bits : 16 - 19 (4 bit)
access : read-write
WRODT1 : WRODT1
bits : 20 - 23 (4 bit)
access : read-write
WRODT2 : WRODT2
bits : 24 - 27 (4 bit)
access : read-write
WRODT3 : WRODT3
bits : 28 - 31 (4 bit)
access : read-write
DTAR register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCOL : DTCOL
bits : 0 - 11 (12 bit)
access : read-write
DTROW : DTROW
bits : 12 - 27 (16 bit)
access : read-write
DTBANK : DTBANK
bits : 28 - 30 (3 bit)
access : read-write
DTMPR : DTMPR
bits : 31 - 31 (1 bit)
access : read-write
DTDR0 register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTBYTE0 : DTBYTE0
bits : 0 - 7 (8 bit)
access : read-write
DTBYTE1 : DTBYTE1
bits : 8 - 15 (8 bit)
access : read-write
DTBYTE2 : DTBYTE2
bits : 16 - 23 (8 bit)
access : read-write
DTBYTE3 : DTBYTE3
bits : 24 - 31 (8 bit)
access : read-write
DTDR1 register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTBYTE4 : DTBYTE4
bits : 0 - 7 (8 bit)
access : read-write
DTBYTE5 : DTBYTE5
bits : 8 - 15 (8 bit)
access : read-write
DTBYTE6 : DTBYTE6
bits : 16 - 23 (8 bit)
access : read-write
DTBYTE7 : DTBYTE7
bits : 24 - 31 (8 bit)
access : read-write
PGCR register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITMDMD : ITMDMD
bits : 0 - 0 (1 bit)
access : read-write
DQSCFG : DQSCFG
bits : 1 - 1 (1 bit)
access : read-write
DFTCMP : DFTCMP
bits : 2 - 2 (1 bit)
access : read-write
DFTLMT : DFTLMT
bits : 3 - 4 (2 bit)
access : read-write
DTOSEL : DTOSEL
bits : 5 - 8 (4 bit)
access : read-write
CKEN : CKEN
bits : 9 - 11 (3 bit)
access : read-write
CKDV : CKDV
bits : 12 - 13 (2 bit)
access : read-write
CKINV : CKINV
bits : 14 - 14 (1 bit)
access : read-write
IOLB : IOLB
bits : 15 - 15 (1 bit)
access : read-write
IODDRM : IODDRM
bits : 16 - 17 (2 bit)
access : read-write
RANKEN : RANKEN
bits : 18 - 21 (4 bit)
access : read-write
ZKSEL : ZKSEL
bits : 22 - 23 (2 bit)
access : read-write
PDDISDX : PDDISDX
bits : 24 - 24 (1 bit)
access : read-write
RFSHDT : RFSHDT
bits : 25 - 28 (4 bit)
access : read-write
LBDQSS : LBDQSS
bits : 29 - 29 (1 bit)
access : read-write
LBGDQS : LBGDQS
bits : 30 - 30 (1 bit)
access : read-write
LBMODE : LBMODE
bits : 31 - 31 (1 bit)
access : read-write
PGSR register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IDONE : IDONE
bits : 0 - 0 (1 bit)
access : read-only
DLDONE : DLDONE
bits : 1 - 1 (1 bit)
access : read-only
ZCDDONE : ZCDDONE
bits : 2 - 2 (1 bit)
access : read-only
DIDONE : DIDONE
bits : 3 - 3 (1 bit)
access : read-only
DTDONE : DTDONE
bits : 4 - 4 (1 bit)
access : read-only
DTERR : DTERR
bits : 5 - 5 (1 bit)
access : read-only
DTIERR : DTIERR
bits : 6 - 6 (1 bit)
access : read-only
DFTERR : DFTERR
bits : 7 - 7 (1 bit)
access : read-only
RVERR : RVERR
bits : 8 - 8 (1 bit)
access : read-only
RVEIRR : RVEIRR
bits : 9 - 9 (1 bit)
access : read-only
TQ : TQ
bits : 31 - 31 (1 bit)
access : read-only
DCUAR register
address_offset : 0xC0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CWADDR : CWADDR
bits : 0 - 3 (4 bit)
access : read-write
CSADDR : CSADDR
bits : 4 - 7 (4 bit)
access : read-write
CSEL : CSEL
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Command cache
0x1 : B_0x1
Expected data cache
0x2 : B_0x2
Read data cache
End of enumeration elements list.
INCA : INCA
bits : 10 - 10 (1 bit)
access : read-write
ATYPE : ATYPE
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Write access
0x1 : B_0x1
Read access
End of enumeration elements list.
DCUDR register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDATA : CDATA
bits : 0 - 31 (32 bit)
access : read-write
DCURR register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DINST : DINST
bits : 0 - 3 (4 bit)
access : read-write
SADDR : SADDR
bits : 4 - 7 (4 bit)
access : read-write
EADDR : EADDR
bits : 8 - 11 (4 bit)
access : read-write
NFAIL : NFAIL
bits : 12 - 19 (8 bit)
access : read-write
SONF : SONF
bits : 20 - 20 (1 bit)
access : read-write
SCOF : SCOF
bits : 21 - 21 (1 bit)
access : read-write
RCEN : RCEN
bits : 22 - 22 (1 bit)
access : read-write
XCEN : XCEN
bits : 23 - 23 (1 bit)
access : read-write
DCULR register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSADDR : LSADDR
bits : 0 - 3 (4 bit)
access : read-write
LEADDR : LEADDR
bits : 4 - 7 (4 bit)
access : read-write
LCNT : LCNT
bits : 8 - 15 (8 bit)
access : read-write
LFINF : LFINF
bits : 16 - 16 (1 bit)
access : read-write
IDA : IDA
bits : 17 - 17 (1 bit)
access : read-write
XLEADDR : XLEADDR
bits : 28 - 31 (4 bit)
access : read-write
DCUGCR register
address_offset : 0xD0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCSW : RCSW
bits : 0 - 15 (16 bit)
access : read-write
DCUTPR register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDCUTO : TDCUTO
bits : 0 - 7 (8 bit)
access : read-write
TDCUT1 : TDCUT1
bits : 8 - 15 (8 bit)
access : read-write
TDCUT2 : TDCUT2
bits : 16 - 23 (8 bit)
access : read-write
TDCUT3 : TDCUT3
bits : 24 - 31 (8 bit)
access : read-write
DCUSR0 register
address_offset : 0xD8 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDONE : RDONE
bits : 0 - 0 (1 bit)
access : read-only
CFAIL : CFAIL
bits : 1 - 1 (1 bit)
access : read-only
CFULL : CFULL
bits : 2 - 2 (1 bit)
access : read-only
DCUSR1 register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDCNT : RDCNT
bits : 0 - 15 (16 bit)
access : read-only
FLCND : FLCND
bits : 16 - 23 (8 bit)
access : read-only
LPCNT : LPCNT
bits : 24 - 31 (8 bit)
access : read-only
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