\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
DMAMUX1 request line multiplexer channel 0 configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write
SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation
disabled
0x1 : B_0x1
event generation
enabled
End of enumeration elements list.
SE : SE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization
disabled
0x1 : B_0x1
synchronization
enabled
End of enumeration elements list.
SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. None synchronization
nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write
DMAMUX1 request line multiplexer channel 4 configuration register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write
SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation
disabled
0x1 : B_0x1
event generation
enabled
End of enumeration elements list.
SE : SE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization
disabled
0x1 : B_0x1
synchronization
enabled
End of enumeration elements list.
SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. None synchronization
nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write
DMAMUX1 request generator channel 0 configuration register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : SIG_ID
bits : 0 - 2 (3 bit)
access : read-write
OIE : OIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt on a trigger overrun event
occurrence is disabled
0x1 : B_0x1
interrupt on a trigger overrun event
occurrence is enabled
End of enumeration elements list.
GE : GE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DMA request generator channel x
disabled
0x1 : B_0x1
DMA request generator channel x
enabled
End of enumeration elements list.
GPOL : GPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. none trigger
detection nor generation.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
GNBREQ : GNBREQ
bits : 19 - 23 (5 bit)
access : read-write
DMAMUX1 request generator channel 1 configuration register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : SIG_ID
bits : 0 - 2 (3 bit)
access : read-write
OIE : OIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt on a trigger overrun event
occurrence is disabled
0x1 : B_0x1
interrupt on a trigger overrun event
occurrence is enabled
End of enumeration elements list.
GE : GE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DMA request generator channel x
disabled
0x1 : B_0x1
DMA request generator channel x
enabled
End of enumeration elements list.
GPOL : GPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. none trigger
detection nor generation.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
GNBREQ : GNBREQ
bits : 19 - 23 (5 bit)
access : read-write
DMAMUX1 request generator channel 2 configuration register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : SIG_ID
bits : 0 - 2 (3 bit)
access : read-write
OIE : OIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt on a trigger overrun event
occurrence is disabled
0x1 : B_0x1
interrupt on a trigger overrun event
occurrence is enabled
End of enumeration elements list.
GE : GE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DMA request generator channel x
disabled
0x1 : B_0x1
DMA request generator channel x
enabled
End of enumeration elements list.
GPOL : GPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. none trigger
detection nor generation.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
GNBREQ : GNBREQ
bits : 19 - 23 (5 bit)
access : read-write
DMAMUX1 request generator channel 3 configuration register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : SIG_ID
bits : 0 - 2 (3 bit)
access : read-write
OIE : OIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt on a trigger overrun event
occurrence is disabled
0x1 : B_0x1
interrupt on a trigger overrun event
occurrence is enabled
End of enumeration elements list.
GE : GE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DMA request generator channel x
disabled
0x1 : B_0x1
DMA request generator channel x
enabled
End of enumeration elements list.
GPOL : GPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. none trigger
detection nor generation.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
GNBREQ : GNBREQ
bits : 19 - 23 (5 bit)
access : read-write
DMAMUX1 request generator channel 4 configuration register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : SIG_ID
bits : 0 - 2 (3 bit)
access : read-write
OIE : OIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt on a trigger overrun event
occurrence is disabled
0x1 : B_0x1
interrupt on a trigger overrun event
occurrence is enabled
End of enumeration elements list.
GE : GE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DMA request generator channel x
disabled
0x1 : B_0x1
DMA request generator channel x
enabled
End of enumeration elements list.
GPOL : GPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. none trigger
detection nor generation.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
GNBREQ : GNBREQ
bits : 19 - 23 (5 bit)
access : read-write
DMAMUX1 request generator channel 5 configuration register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : SIG_ID
bits : 0 - 2 (3 bit)
access : read-write
OIE : OIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt on a trigger overrun event
occurrence is disabled
0x1 : B_0x1
interrupt on a trigger overrun event
occurrence is enabled
End of enumeration elements list.
GE : GE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DMA request generator channel x
disabled
0x1 : B_0x1
DMA request generator channel x
enabled
End of enumeration elements list.
GPOL : GPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. none trigger
detection nor generation.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
GNBREQ : GNBREQ
bits : 19 - 23 (5 bit)
access : read-write
DMAMUX1 request generator channel 6 configuration register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : SIG_ID
bits : 0 - 2 (3 bit)
access : read-write
OIE : OIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt on a trigger overrun event
occurrence is disabled
0x1 : B_0x1
interrupt on a trigger overrun event
occurrence is enabled
End of enumeration elements list.
GE : GE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DMA request generator channel x
disabled
0x1 : B_0x1
DMA request generator channel x
enabled
End of enumeration elements list.
GPOL : GPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. none trigger
detection nor generation.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
GNBREQ : GNBREQ
bits : 19 - 23 (5 bit)
access : read-write
DMAMUX1 request generator channel 7 configuration register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : SIG_ID
bits : 0 - 2 (3 bit)
access : read-write
OIE : OIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt on a trigger overrun event
occurrence is disabled
0x1 : B_0x1
interrupt on a trigger overrun event
occurrence is enabled
End of enumeration elements list.
GE : GE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DMA request generator channel x
disabled
0x1 : B_0x1
DMA request generator channel x
enabled
End of enumeration elements list.
GPOL : GPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. none trigger
detection nor generation.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
GNBREQ : GNBREQ
bits : 19 - 23 (5 bit)
access : read-write
DMAMUX1 request line multiplexer channel 5 configuration register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write
SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation
disabled
0x1 : B_0x1
event generation
enabled
End of enumeration elements list.
SE : SE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization
disabled
0x1 : B_0x1
synchronization
enabled
End of enumeration elements list.
SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. None synchronization
nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write
DMAMUX1 request generator interrupt status register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OF0 : OF0
bits : 0 - 0 (1 bit)
access : read-only
OF1 : OF1
bits : 1 - 1 (1 bit)
access : read-only
OF2 : OF2
bits : 2 - 2 (1 bit)
access : read-only
OF3 : OF3
bits : 3 - 3 (1 bit)
access : read-only
OF4 : OF4
bits : 4 - 4 (1 bit)
access : read-only
OF5 : OF5
bits : 5 - 5 (1 bit)
access : read-only
OF6 : OF6
bits : 6 - 6 (1 bit)
access : read-only
OF7 : OF7
bits : 7 - 7 (1 bit)
access : read-only
DMAMUX1 request generator interrupt clear flag register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COF0 : COF0
bits : 0 - 0 (1 bit)
access : read-only
COF1 : COF1
bits : 1 - 1 (1 bit)
access : read-only
COF2 : COF2
bits : 2 - 2 (1 bit)
access : read-only
COF3 : COF3
bits : 3 - 3 (1 bit)
access : read-only
COF4 : COF4
bits : 4 - 4 (1 bit)
access : read-only
COF5 : COF5
bits : 5 - 5 (1 bit)
access : read-only
COF6 : COF6
bits : 6 - 6 (1 bit)
access : read-only
COF7 : COF7
bits : 7 - 7 (1 bit)
access : read-only
DMAMUX1 request line multiplexer channel 6 configuration register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write
SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation
disabled
0x1 : B_0x1
event generation
enabled
End of enumeration elements list.
SE : SE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization
disabled
0x1 : B_0x1
synchronization
enabled
End of enumeration elements list.
SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. None synchronization
nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write
DMAMUX1 request line multiplexer channel 7 configuration register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write
SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation
disabled
0x1 : B_0x1
event generation
enabled
End of enumeration elements list.
SE : SE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization
disabled
0x1 : B_0x1
synchronization
enabled
End of enumeration elements list.
SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. None synchronization
nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write
DMAMUX1 request line multiplexer channel 8 configuration register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write
SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation
disabled
0x1 : B_0x1
event generation
enabled
End of enumeration elements list.
SE : SE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization
disabled
0x1 : B_0x1
synchronization
enabled
End of enumeration elements list.
SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. None synchronization
nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write
DMAMUX1 request line multiplexer channel 9 configuration register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write
SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation
disabled
0x1 : B_0x1
event generation
enabled
End of enumeration elements list.
SE : SE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization
disabled
0x1 : B_0x1
synchronization
enabled
End of enumeration elements list.
SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. None synchronization
nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write
DMAMUX1 request line multiplexer channel 10 configuration register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write
SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation
disabled
0x1 : B_0x1
event generation
enabled
End of enumeration elements list.
SE : SE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization
disabled
0x1 : B_0x1
synchronization
enabled
End of enumeration elements list.
SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. None synchronization
nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write
DMAMUX1 request line multiplexer channel 11 configuration register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write
SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation
disabled
0x1 : B_0x1
event generation
enabled
End of enumeration elements list.
SE : SE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization
disabled
0x1 : B_0x1
synchronization
enabled
End of enumeration elements list.
SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. None synchronization
nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write
DMAMUX1 request line multiplexer channel 12 configuration register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write
SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation
disabled
0x1 : B_0x1
event generation
enabled
End of enumeration elements list.
SE : SE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization
disabled
0x1 : B_0x1
synchronization
enabled
End of enumeration elements list.
SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. None synchronization
nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write
DMAMUX1 request line multiplexer channel 13 configuration register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write
SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation
disabled
0x1 : B_0x1
event generation
enabled
End of enumeration elements list.
SE : SE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization
disabled
0x1 : B_0x1
synchronization
enabled
End of enumeration elements list.
SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. None synchronization
nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write
DMAMUX1 request line multiplexer channel 14 configuration register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write
SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation
disabled
0x1 : B_0x1
event generation
enabled
End of enumeration elements list.
SE : SE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization
disabled
0x1 : B_0x1
synchronization
enabled
End of enumeration elements list.
SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. None synchronization
nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write
DMAMUX1 request line multiplexer channel 15 configuration register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write
SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation
disabled
0x1 : B_0x1
event generation
enabled
End of enumeration elements list.
SE : SE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization
disabled
0x1 : B_0x1
synchronization
enabled
End of enumeration elements list.
SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. None synchronization
nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write
DMAMUX hardware configuration 2 register
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NUM_DMA_EXT_REQ : NUM_DMA_EXT_REQ
bits : 0 - 7 (8 bit)
DMAMUX hardware configuration 1 register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NUM_DMA_STREAMS : NUM_DMA_STREAMS
bits : 0 - 7 (8 bit)
NUM_DMA_PERIPH_REQ : NUM_DMA_PERIPH_REQ
bits : 8 - 15 (8 bit)
NUM_DMA_TRIG : NUM_DMA_TRIG
bits : 16 - 23 (8 bit)
NUM_DMA_REQGEN : NUM_DMA_REQGEN
bits : 24 - 31 (8 bit)
DMAMUX IP Version Register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINREV : MINREV
bits : 0 - 3 (4 bit)
MAJREV : MAJREV
bits : 4 - 7 (4 bit)
DMAMUX IP Version Register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : ID
bits : 0 - 31 (32 bit)
DMAMUX IP Version Register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SID : SID
bits : 0 - 31 (32 bit)
DMAMUX1 request line multiplexer channel 1 configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write
SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation
disabled
0x1 : B_0x1
event generation
enabled
End of enumeration elements list.
SE : SE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization
disabled
0x1 : B_0x1
synchronization
enabled
End of enumeration elements list.
SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. None synchronization
nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write
DMAMUX1 request line multiplexer channel 2 configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write
SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation
disabled
0x1 : B_0x1
event generation
enabled
End of enumeration elements list.
SE : SE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization
disabled
0x1 : B_0x1
synchronization
enabled
End of enumeration elements list.
SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. None synchronization
nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write
DMAMUX1 request line multiplexer interrupt channel status register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SOF0 : SOF0
bits : 0 - 0 (1 bit)
access : read-only
SOF1 : SOF1
bits : 1 - 1 (1 bit)
access : read-only
SOF2 : SOF2
bits : 2 - 2 (1 bit)
access : read-only
SOF3 : SOF3
bits : 3 - 3 (1 bit)
access : read-only
SOF4 : SOF4
bits : 4 - 4 (1 bit)
access : read-only
SOF5 : SOF5
bits : 5 - 5 (1 bit)
access : read-only
SOF6 : SOF6
bits : 6 - 6 (1 bit)
access : read-only
SOF7 : SOF7
bits : 7 - 7 (1 bit)
access : read-only
SOF8 : SOF8
bits : 8 - 8 (1 bit)
access : read-only
SOF9 : SOF9
bits : 9 - 9 (1 bit)
access : read-only
SOF10 : SOF10
bits : 10 - 10 (1 bit)
access : read-only
SOF11 : SOF11
bits : 11 - 11 (1 bit)
access : read-only
SOF12 : SOF12
bits : 12 - 12 (1 bit)
access : read-only
SOF13 : SOF13
bits : 13 - 13 (1 bit)
access : read-only
SOF14 : SOF14
bits : 14 - 14 (1 bit)
access : read-only
SOF15 : SOF15
bits : 15 - 15 (1 bit)
access : read-only
DMAMUX1 request line multiplexer interrupt clear flag register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSOF0 : CSOF0
bits : 0 - 0 (1 bit)
access : write-only
CSOF1 : CSOF1
bits : 1 - 1 (1 bit)
access : write-only
CSOF2 : CSOF2
bits : 2 - 2 (1 bit)
access : write-only
CSOF3 : CSOF3
bits : 3 - 3 (1 bit)
access : write-only
CSOF4 : CSOF4
bits : 4 - 4 (1 bit)
access : write-only
CSOF5 : CSOF5
bits : 5 - 5 (1 bit)
access : write-only
CSOF6 : CSOF6
bits : 6 - 6 (1 bit)
access : write-only
CSOF7 : CSOF7
bits : 7 - 7 (1 bit)
access : write-only
CSOF8 : CSOF8
bits : 8 - 8 (1 bit)
access : write-only
CSOF9 : CSOF9
bits : 9 - 9 (1 bit)
access : write-only
CSOF10 : CSOF10
bits : 10 - 10 (1 bit)
access : write-only
CSOF11 : CSOF11
bits : 11 - 11 (1 bit)
access : write-only
CSOF12 : CSOF12
bits : 12 - 12 (1 bit)
access : write-only
CSOF13 : CSOF13
bits : 13 - 13 (1 bit)
access : write-only
CSOF14 : CSOF14
bits : 14 - 14 (1 bit)
access : write-only
CSOF15 : CSOF15
bits : 15 - 15 (1 bit)
access : write-only
DMAMUX1 request line multiplexer channel 3 configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMAREQ_ID
bits : 0 - 6 (7 bit)
access : read-write
SOIE : SOIE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
interrupt disabled
0x1 : B_0x1
interrupt enabled
End of enumeration elements list.
EGE : EGE
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
event generation
disabled
0x1 : B_0x1
event generation
enabled
End of enumeration elements list.
SE : SE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
synchronization
disabled
0x1 : B_0x1
synchronization
enabled
End of enumeration elements list.
SPOL : SPOL
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
no event. I.e. None synchronization
nor detection.
0x1 : B_0x1
rising edge
0x2 : B_0x2
falling edge
0x3 : B_0x3
rising and falling
edge
End of enumeration elements list.
NBREQ : NBREQ
bits : 19 - 23 (5 bit)
access : read-write
SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)
access : read-write
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