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address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
RNG control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RNGEN : RNGEN
bits : 2 - 2 (1 bit)
access : read-write
IE : IE
bits : 3 - 3 (1 bit)
access : read-write
CED : CED
bits : 5 - 5 (1 bit)
access : read-write
RNG Version Register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VER : VER
bits : 0 - 7 (8 bit)
access : read-only
RNG Identification
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : ID
bits : 0 - 31 (32 bit)
access : read-only
RNG hardware magic ID
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MID : MID
bits : 0 - 31 (32 bit)
access : read-only
RNG status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRDY : DRDY
bits : 0 - 0 (1 bit)
access : read-only
CECS : CECS
bits : 1 - 1 (1 bit)
access : read-only
SECS : SECS
bits : 2 - 2 (1 bit)
access : read-only
CEIS : CEIS
bits : 5 - 5 (1 bit)
access : read-write
SEIS : SEIS
bits : 6 - 6 (1 bit)
access : read-write
The RNG_DR register is a read-only register that delivers a 32-bit random value when read. After being read this register delivers a new random value after 216 periods of AHB clock if the output FIFO is empty. The content of this register is valid when DRDY, even if RNGEN
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RNDATA : RNDATA
bits : 0 - 31 (32 bit)
access : read-only
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