\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page632 and Reading the calendar on page633. This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be write-protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SU : SU
bits : 0 - 3 (4 bit)
access : read-write
ST : ST
bits : 4 - 6 (3 bit)
access : read-write
MNU : MNU
bits : 8 - 11 (4 bit)
access : read-write
MNT : MNT
bits : 12 - 14 (3 bit)
access : read-write
HU : HU
bits : 16 - 19 (4 bit)
access : read-write
HT : HT
bits : 20 - 21 (2 bit)
access : read-write
PM : PM
bits : 22 - 22 (1 bit)
access : read-write
This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page632. This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be write-protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREDIV_S : PREDIV_S
bits : 0 - 14 (15 bit)
access : read-write
PREDIV_A : PREDIV_A
bits : 16 - 22 (7 bit)
access : read-write
This register can be written only when WUTWF is set to 1 in RTC_ICSR. This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WUT : WUT
bits : 0 - 15 (16 bit)
access : read-write
This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WUCKSEL : WUCKSEL
bits : 0 - 2 (3 bit)
access : read-write
TSEDGE : TSEDGE
bits : 3 - 3 (1 bit)
access : read-write
REFCKON : REFCKON
bits : 4 - 4 (1 bit)
access : read-write
BYPSHAD : BYPSHAD
bits : 5 - 5 (1 bit)
access : read-write
FMT : FMT
bits : 6 - 6 (1 bit)
access : read-write
ALRAE : ALRAE
bits : 8 - 8 (1 bit)
access : read-write
ALRBE : ALRBE
bits : 9 - 9 (1 bit)
access : read-write
WUTE : WUTE
bits : 10 - 10 (1 bit)
access : read-write
TSE : TSE
bits : 11 - 11 (1 bit)
access : read-write
ALRAIE : ALRAIE
bits : 12 - 12 (1 bit)
access : read-write
ALRBIE : ALRBIE
bits : 13 - 13 (1 bit)
access : read-write
WUTIE : WUTIE
bits : 14 - 14 (1 bit)
access : read-write
TSIE : TSIE
bits : 15 - 15 (1 bit)
access : read-write
ADD1H : ADD1H
bits : 16 - 16 (1 bit)
access : write-only
SUB1H : SUB1H
bits : 17 - 17 (1 bit)
access : write-only
BKP : BKP
bits : 18 - 18 (1 bit)
access : read-write
COSEL : COSEL
bits : 19 - 19 (1 bit)
access : read-write
POL : POL
bits : 20 - 20 (1 bit)
access : read-write
OSEL : OSEL
bits : 21 - 22 (2 bit)
access : read-write
COE : COE
bits : 23 - 23 (1 bit)
access : read-write
ITSE : ITSE
bits : 24 - 24 (1 bit)
access : read-write
TAMPTS : TAMPTS
bits : 25 - 25 (1 bit)
access : read-write
TAMPOE : TAMPOE
bits : 26 - 26 (1 bit)
access : read-write
TAMPALRM_PU : TAMPALRM_PU
bits : 29 - 29 (1 bit)
access : read-write
TAMPALRM_TYPE : TAMPALRM_TYPE
bits : 30 - 30 (1 bit)
access : read-write
OUT2EN : OUT2EN
bits : 31 - 31 (1 bit)
access : read-write
This register can be written only when the APB access is secure.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALRADPROT : ALRADPROT
bits : 0 - 0 (1 bit)
access : read-write
ALRBDPROT : ALRBDPROT
bits : 1 - 1 (1 bit)
access : read-write
WUTDPROT : WUTDPROT
bits : 2 - 2 (1 bit)
access : read-write
TSDPROT : TSDPROT
bits : 3 - 3 (1 bit)
access : read-write
CALDPROT : CALDPROT
bits : 13 - 13 (1 bit)
access : read-write
INITDPROT : INITDPROT
bits : 14 - 14 (1 bit)
access : read-write
DECPROT : DECPROT
bits : 15 - 15 (1 bit)
access : read-write
RTC write protection register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : KEY
bits : 0 - 7 (8 bit)
access : write-only
This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be write-protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALM : CALM
bits : 0 - 8 (9 bit)
access : read-write
CALW16 : CALW16
bits : 13 - 13 (1 bit)
access : read-write
CALW8 : CALW8
bits : 14 - 14 (1 bit)
access : read-write
CALP : CALP
bits : 15 - 15 (1 bit)
access : read-write
This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBFS : SUBFS
bits : 0 - 14 (15 bit)
access : write-only
ADD1S : ADD1S
bits : 31 - 31 (1 bit)
access : write-only
The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SU : SU
bits : 0 - 3 (4 bit)
access : read-only
ST : ST
bits : 4 - 6 (3 bit)
access : read-only
MNU : MNU
bits : 8 - 11 (4 bit)
access : read-only
MNT : MNT
bits : 12 - 14 (3 bit)
access : read-only
HU : HU
bits : 16 - 19 (4 bit)
access : read-only
HT : HT
bits : 20 - 21 (2 bit)
access : read-only
PM : PM
bits : 22 - 22 (1 bit)
access : read-only
The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes.
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DU : DU
bits : 0 - 3 (4 bit)
access : read-only
DT : DT
bits : 4 - 5 (2 bit)
access : read-only
MU : MU
bits : 8 - 11 (4 bit)
access : read-only
MT : MT
bits : 12 - 12 (1 bit)
access : read-only
WDU : WDU
bits : 13 - 15 (3 bit)
access : read-only
The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when the TSF bit is reset. This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes.
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SS : SS
bits : 0 - 15 (16 bit)
access : read-only
RTC hardware configuration register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ALARMB : ALARMB
bits : 0 - 3 (4 bit)
access : read-only
WAKEUP : WAKEUP
bits : 4 - 7 (4 bit)
access : read-only
SMOOTH_CALIB : SMOOTH_CALIB
bits : 8 - 11 (4 bit)
access : read-only
TIMESTAMP : TIMESTAMP
bits : 12 - 15 (4 bit)
access : read-only
OPTIONREG_OUT : OPTIONREG_OUT
bits : 16 - 23 (8 bit)
access : read-only
TRUST_ZONE : TRUST_ZONE
bits : 24 - 27 (4 bit)
access : read-only
RTC version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINREV : MINREV
bits : 0 - 3 (4 bit)
access : read-only
MAJREV : MAJREV
bits : 4 - 7 (4 bit)
access : read-only
RTC identification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : ID
bits : 0 - 31 (32 bit)
access : read-only
RTC size identification register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SID : SID
bits : 0 - 31 (32 bit)
access : read-only
The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page632 and Reading the calendar on page633. This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be write-protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DU : DU
bits : 0 - 3 (4 bit)
access : read-write
DT : DT
bits : 4 - 5 (2 bit)
access : read-write
MU : MU
bits : 8 - 11 (4 bit)
access : read-write
MT : MT
bits : 12 - 12 (1 bit)
access : read-write
WDU : WDU
bits : 13 - 15 (3 bit)
access : read-write
YU : YU
bits : 16 - 19 (4 bit)
access : read-write
YT : YT
bits : 20 - 23 (4 bit)
access : read-write
This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes.
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SU : SU
bits : 0 - 3 (4 bit)
access : read-write
ST : ST
bits : 4 - 6 (3 bit)
access : read-write
MSK1 : MSK1
bits : 7 - 7 (1 bit)
access : read-write
MNU : MNU
bits : 8 - 11 (4 bit)
access : read-write
MNT : MNT
bits : 12 - 14 (3 bit)
access : read-write
MSK2 : MSK2
bits : 15 - 15 (1 bit)
access : read-write
HU : HU
bits : 16 - 19 (4 bit)
access : read-write
HT : HT
bits : 20 - 21 (2 bit)
access : read-write
PM : PM
bits : 22 - 22 (1 bit)
access : read-write
MSK3 : MSK3
bits : 23 - 23 (1 bit)
access : read-write
DU : DU
bits : 24 - 27 (4 bit)
access : read-write
DT : DT
bits : 28 - 29 (2 bit)
access : read-write
WDSEL : WDSEL
bits : 30 - 30 (1 bit)
access : read-write
MSK4 : MSK4
bits : 31 - 31 (1 bit)
access : read-write
This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SS : SS
bits : 0 - 14 (15 bit)
access : read-write
MASKSS : MASKSS
bits : 24 - 27 (4 bit)
access : read-write
This register can be written only when ALRBWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes.
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SU : SU
bits : 0 - 3 (4 bit)
access : read-write
ST : ST
bits : 4 - 6 (3 bit)
access : read-write
MSK1 : MSK1
bits : 7 - 7 (1 bit)
access : read-write
MNU : MNU
bits : 8 - 11 (4 bit)
access : read-write
MNT : MNT
bits : 12 - 14 (3 bit)
access : read-write
MSK2 : MSK2
bits : 15 - 15 (1 bit)
access : read-write
HU : HU
bits : 16 - 19 (4 bit)
access : read-write
HT : HT
bits : 20 - 21 (2 bit)
access : read-write
PM : PM
bits : 22 - 22 (1 bit)
access : read-write
MSK3 : MSK3
bits : 23 - 23 (1 bit)
access : read-write
DU : DU
bits : 24 - 27 (4 bit)
access : read-write
DT : DT
bits : 28 - 29 (2 bit)
access : read-write
WDSEL : WDSEL
bits : 30 - 30 (1 bit)
access : read-write
MSK4 : MSK4
bits : 31 - 31 (1 bit)
access : read-write
This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode. This register is write protected.The write access procedure is described in Section: RTC register write protection. This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes.
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SS : SS
bits : 0 - 14 (15 bit)
access : read-write
MASKSS : MASKSS
bits : 24 - 27 (4 bit)
access : read-write
This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ALRAF : ALRAF
bits : 0 - 0 (1 bit)
access : read-only
ALRBF : ALRBF
bits : 1 - 1 (1 bit)
access : read-only
WUTF : WUTF
bits : 2 - 2 (1 bit)
access : read-only
TSF : TSF
bits : 3 - 3 (1 bit)
access : read-only
TSOVF : TSOVF
bits : 4 - 4 (1 bit)
access : read-only
ITSF : ITSF
bits : 5 - 5 (1 bit)
access : read-only
RTC non-secure masked interrupt status register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ALRAMF : ALRAMF
bits : 0 - 0 (1 bit)
access : read-only
ALRBMF : ALRBMF
bits : 1 - 1 (1 bit)
access : read-only
WUTMF : WUTMF
bits : 2 - 2 (1 bit)
access : read-only
TSMF : TSMF
bits : 3 - 3 (1 bit)
access : read-only
TSOVMF : TSOVMF
bits : 4 - 4 (1 bit)
access : read-only
ITSMF : ITSMF
bits : 5 - 5 (1 bit)
access : read-only
This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes.
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ALRAMF : ALRAMF
bits : 0 - 0 (1 bit)
access : read-only
ALRBMF : ALRBMF
bits : 1 - 1 (1 bit)
access : read-only
WUTMF : WUTMF
bits : 2 - 2 (1 bit)
access : read-only
TSMF : TSMF
bits : 3 - 3 (1 bit)
access : read-only
TSOVMF : TSOVMF
bits : 4 - 4 (1 bit)
access : read-only
ITSMF : ITSMF
bits : 5 - 5 (1 bit)
access : read-only
This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes.
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALRAF : CALRAF
bits : 0 - 0 (1 bit)
access : write-only
CALRBF : CALRBF
bits : 1 - 1 (1 bit)
access : write-only
CWUTF : CWUTF
bits : 2 - 2 (1 bit)
access : write-only
CTSF : CTSF
bits : 3 - 3 (1 bit)
access : write-only
CTSOVF : CTSOVF
bits : 4 - 4 (1 bit)
access : write-only
CITSF : CITSF
bits : 5 - 5 (1 bit)
access : write-only
RTC configuration register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT2_RMP : OUT2_RMP
bits : 0 - 0 (1 bit)
access : read-write
LSCOEN : LSCOEN
bits : 1 - 2 (2 bit)
access : read-write
RTC sub second register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SS : SS
bits : 0 - 15 (16 bit)
access : read-only
This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALRAWF : ALRAWF
bits : 0 - 0 (1 bit)
access : read-only
ALRBWF : ALRBWF
bits : 1 - 1 (1 bit)
access : read-only
WUTWF : WUTWF
bits : 2 - 2 (1 bit)
access : read-only
SHPF : SHPF
bits : 3 - 3 (1 bit)
access : read-only
INITS : INITS
bits : 4 - 4 (1 bit)
access : read-only
RSF : RSF
bits : 5 - 5 (1 bit)
access : read-write
INITF : INITF
bits : 6 - 6 (1 bit)
access : read-only
INIT : INIT
bits : 7 - 7 (1 bit)
access : read-write
RECALPF : RECALPF
bits : 16 - 16 (1 bit)
access : read-only
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