\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
GICD control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLEGRP0 : enable group 0 interrupts
bits : 0 - 0 (1 bit)
access : read-write
ENABLEGRP1 : enable group 1 interrupts
bits : 1 - 1 (1 bit)
GICD control (non-secure access) register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : GICD_CTLR
reset_Mask : 0x0
ENABLE : Global enable for forwarding pending group 1 interrupts from the GICD to the CPU interfaces
bits : 0 - 0 (1 bit)
GICD interrupt set-enable register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISENABLER0 : interrupt set-enable
bits : 0 - 31 (32 bit)
GICD interrupt set-enable register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISENABLER1 : interrupt set-enable
bits : 0 - 31 (32 bit)
GICD interrupt set-enable register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISENABLER2 : interrupt set-enable
bits : 0 - 31 (32 bit)
GICD interrupt set-enable register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISENABLER3 : interrupt set-enable
bits : 0 - 31 (32 bit)
GICD interrupt set-enable register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISENABLER4 : interrupt set-enable
bits : 0 - 31 (32 bit)
GICD interrupt set-enable register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISENABLER5 : interrupt set-enable
bits : 0 - 31 (32 bit)
GICD interrupt set-enable register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISENABLER6 : interrupt set-enable
bits : 0 - 31 (32 bit)
GICD interrupt set-enable register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISENABLER7 : interrupt set-enable
bits : 0 - 31 (32 bit)
GICD interrupt set-enable register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISENABLER8 : interrupt set-enable
bits : 0 - 31 (32 bit)
GICD interrupt set-active registers
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISACTIVER0 : interrupt clear-pending
bits : 0 - 31 (32 bit)
GICD interrupt clear-enable register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICENABLER0 : interrupt clear-enable 0
bits : 0 - 31 (32 bit)
GICD interrupt clear-enable register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICENABLER1 : interrupt clear-enable 0
bits : 0 - 31 (32 bit)
GICD interrupt clear-enable register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICENABLER2 : interrupt clear-enable 0
bits : 0 - 31 (32 bit)
GICD interrupt clear-enable register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICENABLER3 : interrupt clear-enable 0
bits : 0 - 31 (32 bit)
GICD interrupt clear-enable register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICENABLER4 : interrupt clear-enable 0
bits : 0 - 31 (32 bit)
GICD interrupt clear-enable register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICENABLER5 : interrupt clear-enable 0
bits : 0 - 31 (32 bit)
GICD interrupt clear-enable register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICENABLER6 : interrupt clear-enable 0
bits : 0 - 31 (32 bit)
GICD interrupt clear-enable register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICENABLER7 : interrupt clear-enable 0
bits : 0 - 31 (32 bit)
GICD interrupt clear-enable register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICENABLER8 : interrupt clear-enable 0
bits : 0 - 31 (32 bit)
GICD interrupt set-pending registers
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPENDR0 : interrupt set-pending
bits : 0 - 31 (32 bit)
GICD interrupt set-pending registers
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPENDR1 : interrupt set-pending
bits : 0 - 31 (32 bit)
GICD interrupt set-pending registers
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPENDR2 : interrupt set-pending
bits : 0 - 31 (32 bit)
GICD interrupt set-pending registers
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPENDR3 : interrupt set-pending
bits : 0 - 31 (32 bit)
GICD interrupt set-pending registers
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPENDR4 : interrupt set-pending
bits : 0 - 31 (32 bit)
GICD interrupt set-pending registers
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPENDR5 : interrupt set-pending
bits : 0 - 31 (32 bit)
GICD interrupt set-pending registers
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPENDR6 : interrupt set-pending
bits : 0 - 31 (32 bit)
GICD interrupt set-pending registers
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPENDR7 : interrupt set-pending
bits : 0 - 31 (32 bit)
GICD interrupt set-pending registers
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPENDR8 : interrupt set-pending
bits : 0 - 31 (32 bit)
GICD interrupt clear-pending registers
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICPENDR0 : interrupt clear-pending
bits : 0 - 31 (32 bit)
GICD interrupt clear-pending registers
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICPENDR1 : interrupt clear-pending
bits : 0 - 31 (32 bit)
GICD interrupt clear-pending registers
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICPENDR2 : interrupt clear-pending
bits : 0 - 31 (32 bit)
GICD interrupt clear-pending registers
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICPENDR3 : interrupt clear-pending
bits : 0 - 31 (32 bit)
GICD interrupt clear-pending registers
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICPENDR4 : interrupt clear-pending
bits : 0 - 31 (32 bit)
GICD interrupt clear-pending registers
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICPENDR5 : interrupt clear-pending
bits : 0 - 31 (32 bit)
GICD interrupt clear-pending registers
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICPENDR6 : interrupt clear-pending
bits : 0 - 31 (32 bit)
GICD interrupt clear-pending registers
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICPENDR7 : interrupt clear-pending
bits : 0 - 31 (32 bit)
GICD interrupt clear-pending registers
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICPENDR8 : interrupt clear-pending
bits : 0 - 31 (32 bit)
GICD interrupt set-active registers
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISACTIVER1 : interrupt clear-pending
bits : 0 - 31 (32 bit)
GICD interrupt set-active registers
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISACTIVER2 : interrupt clear-pending
bits : 0 - 31 (32 bit)
GICD interrupt set-active registers
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISACTIVER3 : interrupt clear-pending
bits : 0 - 31 (32 bit)
GICD interrupt set-active registers
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISACTIVER4 : interrupt clear-pending
bits : 0 - 31 (32 bit)
GICD interrupt set-active registers
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISACTIVER5 : interrupt clear-pending
bits : 0 - 31 (32 bit)
GICD interrupt set-active registers
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISACTIVER6 : interrupt clear-pending
bits : 0 - 31 (32 bit)
GICD interrupt set-active registers
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISACTIVER7 : interrupt clear-pending
bits : 0 - 31 (32 bit)
GICD interrupt set-active registers
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISACTIVER8 : interrupt clear-pending
bits : 0 - 31 (32 bit)
GICD interrupt clear-active registers
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICACTIVER0 : interrupt clear-active
bits : 0 - 31 (32 bit)
GICD interrupt clear-active registers
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICACTIVER1 : interrupt clear-active
bits : 0 - 31 (32 bit)
GICD interrupt clear-active registers
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICACTIVER2 : interrupt clear-active
bits : 0 - 31 (32 bit)
GICD interrupt clear-active registers
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICACTIVER3 : interrupt clear-active
bits : 0 - 31 (32 bit)
GICD interrupt clear-active registers
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICACTIVER4 : interrupt clear-active
bits : 0 - 31 (32 bit)
GICD interrupt clear-active registers
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICACTIVER5 : interrupt clear-active
bits : 0 - 31 (32 bit)
GICD interrupt clear-active registers
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICACTIVER6 : interrupt clear-active
bits : 0 - 31 (32 bit)
GICD interrupt clear-active registers
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICACTIVER7 : interrupt clear-active
bits : 0 - 31 (32 bit)
GICD interrupt clear-active registers
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICACTIVER8 : interrupt clear-active
bits : 0 - 31 (32 bit)
GICD interrupt controller type register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ITLINESNUMBER : number of interrupt lines
bits : 0 - 4 (5 bit)
CPUNUMBER : number of processors interfaces
bits : 5 - 7 (3 bit)
SECURITYEXTN : security extension
bits : 10 - 10 (1 bit)
LSPI : lockable shared peripheral interrupt
bits : 11 - 15 (5 bit)
GICD interrupt priority registers
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x45C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x46C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x47C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x4FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD interrupt priority registers
address_offset : 0x51C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : priority for interrupt
bits : 3 - 7 (5 bit)
PRIORITY1 : priority for interrupt
bits : 11 - 15 (5 bit)
PRIORITY2 : priority for interrupt
bits : 19 - 23 (5 bit)
PRIORITY3 : priority for interrupt
bits : 27 - 31 (5 bit)
GICD implementer identification register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IMPLEMENTER : GIC implementer
bits : 0 - 11 (12 bit)
VARIANT : major revision number of the GIC
bits : 12 - 15 (4 bit)
REVISION : minor revision number of the GIC
bits : 16 - 19 (4 bit)
PRODUCTID : product ID of the GIC
bits : 24 - 31 (8 bit)
GICD interrupt group registers
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IGROUPR0 : group of interrupts
bits : 0 - 31 (32 bit)
GICD interrupt processor target registers
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x814 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x83C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt group registers
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IGROUPR1 : group of interrupts
bits : 0 - 31 (32 bit)
GICD interrupt processor target registers
address_offset : 0x840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x844 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x848 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x84C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x858 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x85C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x864 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x86C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x874 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x878 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x87C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt group registers
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IGROUPR2 : group of interrupts
bits : 0 - 31 (32 bit)
GICD interrupt processor target registers
address_offset : 0x880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x884 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x88C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x894 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x898 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x89C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt group registers
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IGROUPR3 : group of interrupts
bits : 0 - 31 (32 bit)
GICD interrupt processor target registers
address_offset : 0x8C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x8FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt group registers
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IGROUPR4 : group of interrupts
bits : 0 - 31 (32 bit)
GICD interrupt processor target registers
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x908 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x90C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt processor target registers
address_offset : 0x91C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU(s) target for interrupt
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU(s) target for interrupt
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU(s) target for interrupt
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU(s) target for interrupt
bits : 24 - 25 (2 bit)
GICD interrupt group registers
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IGROUPR5 : group of interrupts
bits : 0 - 31 (32 bit)
GICD interrupt group registers
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IGROUPR6 : group of interrupts
bits : 0 - 31 (32 bit)
GICD interrupt group registers
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IGROUPR7 : group of interrupts
bits : 0 - 31 (32 bit)
GICD interrupt group registers
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IGROUPR8 : group of interrupts
bits : 0 - 31 (32 bit)
GICD interrupt configuration register
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)
INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)
INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)
INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)
INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)
INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)
INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)
INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)
INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)
INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)
INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)
INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)
INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)
INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)
INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)
INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)
GICD interrupt configuration register
address_offset : 0xC04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)
INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)
INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)
INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)
INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)
INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)
INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)
INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)
INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)
INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)
INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)
INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)
INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)
INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)
INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)
INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)
GICD interrupt configuration register
address_offset : 0xC08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)
INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)
INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)
INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)
INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)
INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)
INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)
INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)
INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)
INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)
INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)
INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)
INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)
INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)
INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)
INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)
GICD interrupt configuration register
address_offset : 0xC0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)
INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)
INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)
INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)
INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)
INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)
INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)
INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)
INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)
INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)
INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)
INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)
INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)
INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)
INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)
INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)
GICD interrupt configuration register
address_offset : 0xC10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)
INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)
INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)
INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)
INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)
INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)
INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)
INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)
INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)
INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)
INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)
INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)
INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)
INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)
INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)
INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)
GICD interrupt configuration register
address_offset : 0xC14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)
INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)
INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)
INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)
INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)
INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)
INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)
INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)
INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)
INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)
INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)
INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)
INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)
INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)
INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)
INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)
GICD interrupt configuration register
address_offset : 0xC18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)
INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)
INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)
INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)
INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)
INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)
INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)
INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)
INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)
INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)
INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)
INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)
INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)
INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)
INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)
INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)
GICD interrupt configuration register
address_offset : 0xC1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)
INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)
INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)
INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)
INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)
INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)
INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)
INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)
INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)
INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)
INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)
INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)
INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)
INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)
INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)
INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)
GICD interrupt configuration register
address_offset : 0xC20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)
INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)
INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)
INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)
INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)
INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)
INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)
INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)
INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)
INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)
INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)
INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)
INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)
INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)
INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)
INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)
GICD interrupt configuration register
address_offset : 0xC24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)
INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)
INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)
INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)
INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)
INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)
INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)
INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)
INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)
INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)
INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)
INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)
INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)
INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)
INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)
INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)
GICD interrupt configuration register
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)
INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)
INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)
INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)
INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)
INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)
INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)
INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)
INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)
INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)
INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)
INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)
INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)
INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)
INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)
INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)
GICD interrupt configuration register
address_offset : 0xC2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)
INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)
INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)
INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)
INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)
INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)
INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)
INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)
INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)
INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)
INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)
INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)
INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)
INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)
INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)
INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)
GICD interrupt configuration register
address_offset : 0xC30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)
INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)
INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)
INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)
INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)
INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)
INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)
INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)
INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)
INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)
INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)
INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)
INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)
INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)
INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)
INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)
GICD interrupt configuration register
address_offset : 0xC34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)
INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)
INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)
INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)
INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)
INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)
INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)
INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)
INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)
INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)
INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)
INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)
INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)
INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)
INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)
INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)
GICD interrupt configuration register
address_offset : 0xC38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)
INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)
INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)
INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)
INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)
INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)
INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)
INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)
INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)
INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)
INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)
INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)
INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)
INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)
INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)
INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)
GICD interrupt configuration register
address_offset : 0xC3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)
INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)
INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)
INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)
INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)
INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)
INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)
INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)
INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)
INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)
INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)
INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)
INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)
INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)
INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)
INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)
GICD interrupt configuration register
address_offset : 0xC40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)
INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)
INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)
INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)
INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)
INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)
INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)
INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)
INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)
INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)
INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)
INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)
INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)
INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)
INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)
INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)
GICD interrupt configuration register
address_offset : 0xC44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : interrupt config for interrupt
bits : 0 - 1 (2 bit)
INT_CONFIG1 : interrupt config for interrupt
bits : 2 - 3 (2 bit)
INT_CONFIG2 : interrupt config for interrupt
bits : 4 - 5 (2 bit)
INT_CONFIG3 : interrupt config for interrupt
bits : 6 - 7 (2 bit)
INT_CONFIG4 : interrupt config for interrupt
bits : 8 - 9 (2 bit)
INT_CONFIG5 : interrupt config for interrupt
bits : 10 - 11 (2 bit)
INT_CONFIG6 : interrupt config for interrupt
bits : 12 - 13 (2 bit)
INT_CONFIG7 : interrupt config for interrupt
bits : 14 - 15 (2 bit)
INT_CONFIG8 : interrupt config for interrupt
bits : 16 - 17 (2 bit)
INT_CONFIG9 : interrupt config for interrupt
bits : 18 - 19 (2 bit)
INT_CONFIG10 : interrupt config for interrupt
bits : 20 - 21 (2 bit)
INT_CONFIG11 : interrupt config for interrupt
bits : 22 - 23 (2 bit)
INT_CONFIG12 : interrupt config for interrupt
bits : 24 - 25 (2 bit)
INT_CONFIG13 : interrupt config for interrupt
bits : 26 - 27 (2 bit)
INT_CONFIG14 : interrupt config for interrupt
bits : 28 - 29 (2 bit)
INT_CONFIG15 : interrupt config for interrupt
bits : 30 - 31 (2 bit)
GICD private peripheral interrupt status register
address_offset : 0xD00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PPI6 : virtual maintenance interrupt
bits : 9 - 9 (1 bit)
PPI5 : hypervisor timer event
bits : 10 - 10 (1 bit)
PPI4 : virtual timer event
bits : 11 - 11 (1 bit)
PPI0 : nFIQ (not used)
bits : 12 - 12 (1 bit)
PPI1 : secure physical timer event
bits : 13 - 13 (1 bit)
PPI2 : secure physical timer event
bits : 14 - 14 (1 bit)
PPI3 : nIRQ (not used)
bits : 15 - 15 (1 bit)
GICD shared peripheral interrupt registers
address_offset : 0xD04 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPISR0 : shared peripheral interrupt
bits : 0 - 31 (32 bit)
GICD shared peripheral interrupt registers
address_offset : 0xD08 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPISR1 : shared peripheral interrupt
bits : 0 - 31 (32 bit)
GICD shared peripheral interrupt registers
address_offset : 0xD0C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPISR2 : shared peripheral interrupt
bits : 0 - 31 (32 bit)
GICD shared peripheral interrupt registers
address_offset : 0xD10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPISR3 : shared peripheral interrupt
bits : 0 - 31 (32 bit)
GICD shared peripheral interrupt registers
address_offset : 0xD14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPISR4 : shared peripheral interrupt
bits : 0 - 31 (32 bit)
GICD shared peripheral interrupt registers
address_offset : 0xD18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPISR5 : shared peripheral interrupt
bits : 0 - 31 (32 bit)
GICD shared peripheral interrupt registers
address_offset : 0xD1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPISR6 : shared peripheral interrupt
bits : 0 - 31 (32 bit)
GICD shared peripheral interrupt registers
address_offset : 0xD20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPISR7 : shared peripheral interrupt
bits : 0 - 31 (32 bit)
GICD software generated interrupt register
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SGIINTID : SGI interrupt ID
bits : 0 - 3 (4 bit)
NSATT : non-secure attribute
bits : 15 - 15 (1 bit)
CPUTARGETLIST : CPU target list
bits : 16 - 17 (2 bit)
TARGETLISTFILTER : target list filter
bits : 24 - 25 (2 bit)
GICD SGI clear-pending registers
address_offset : 0xF10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SGI_CLEAR_PENDING0 : clear-pending state for SGI
bits : 0 - 1 (2 bit)
SGI_CLEAR_PENDING1 : clear-pending state for SGI
bits : 8 - 9 (2 bit)
SGI_CLEAR_PENDING2 : clear-pending state for SGI
bits : 16 - 17 (2 bit)
SGI_CLEAR_PENDING3 : clear-pending state for SGI
bits : 24 - 25 (2 bit)
GICD SGI clear-pending registers
address_offset : 0xF14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SGI_CLEAR_PENDING0 : clear-pending state for SGI
bits : 0 - 1 (2 bit)
SGI_CLEAR_PENDING1 : clear-pending state for SGI
bits : 8 - 9 (2 bit)
SGI_CLEAR_PENDING2 : clear-pending state for SGI
bits : 16 - 17 (2 bit)
SGI_CLEAR_PENDING3 : clear-pending state for SGI
bits : 24 - 25 (2 bit)
GICD SGI clear-pending registers
address_offset : 0xF18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SGI_CLEAR_PENDING0 : clear-pending state for SGI
bits : 0 - 1 (2 bit)
SGI_CLEAR_PENDING1 : clear-pending state for SGI
bits : 8 - 9 (2 bit)
SGI_CLEAR_PENDING2 : clear-pending state for SGI
bits : 16 - 17 (2 bit)
SGI_CLEAR_PENDING3 : clear-pending state for SGI
bits : 24 - 25 (2 bit)
GICD SGI clear-pending registers
address_offset : 0xF1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SGI_CLEAR_PENDING0 : clear-pending state for SGI
bits : 0 - 1 (2 bit)
SGI_CLEAR_PENDING1 : clear-pending state for SGI
bits : 8 - 9 (2 bit)
SGI_CLEAR_PENDING2 : clear-pending state for SGI
bits : 16 - 17 (2 bit)
SGI_CLEAR_PENDING3 : clear-pending state for SGI
bits : 24 - 25 (2 bit)
GICD SGI set-pending registers
address_offset : 0xF20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SGI_SET_PENDING0 : clear-pending state for SGI
bits : 0 - 1 (2 bit)
SGI_SET_PENDING1 : clear-pending state for SGI
bits : 8 - 9 (2 bit)
SGI_SET_PENDING2 : clear-pending state for SGI
bits : 16 - 17 (2 bit)
SGI_SET_PENDING3 : clear-pending state for SGI
bits : 24 - 25 (2 bit)
GICD SGI set-pending registers
address_offset : 0xF24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SGI_SET_PENDING0 : clear-pending state for SGI
bits : 0 - 1 (2 bit)
SGI_SET_PENDING1 : clear-pending state for SGI
bits : 8 - 9 (2 bit)
SGI_SET_PENDING2 : clear-pending state for SGI
bits : 16 - 17 (2 bit)
SGI_SET_PENDING3 : clear-pending state for SGI
bits : 24 - 25 (2 bit)
GICD SGI set-pending registers
address_offset : 0xF28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SGI_SET_PENDING0 : clear-pending state for SGI
bits : 0 - 1 (2 bit)
SGI_SET_PENDING1 : clear-pending state for SGI
bits : 8 - 9 (2 bit)
SGI_SET_PENDING2 : clear-pending state for SGI
bits : 16 - 17 (2 bit)
SGI_SET_PENDING3 : clear-pending state for SGI
bits : 24 - 25 (2 bit)
GICD SGI set-pending registers
address_offset : 0xF2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SGI_SET_PENDING0 : clear-pending state for SGI
bits : 0 - 1 (2 bit)
SGI_SET_PENDING1 : clear-pending state for SGI
bits : 8 - 9 (2 bit)
SGI_SET_PENDING2 : clear-pending state for SGI
bits : 16 - 17 (2 bit)
SGI_SET_PENDING3 : clear-pending state for SGI
bits : 24 - 25 (2 bit)
GICD peripheral ID4 register
address_offset : 0xFD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIDR4 : peripheral ID4
bits : 0 - 31 (32 bit)
GICD peripheral ID5 register
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIDR5 : peripheral ID5
bits : 0 - 31 (32 bit)
GICD peripheral ID6 register
address_offset : 0xFD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIDR6 : peripheral ID6
bits : 0 - 31 (32 bit)
GICD peripheral ID7 register
address_offset : 0xFDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIDR7 : peripheral ID7
bits : 0 - 31 (32 bit)
GICD peripheral ID0 register
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIDR0 : peripheral ID0
bits : 0 - 31 (32 bit)
GICD peripheral ID1 register
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIDR1 : peripheral ID1
bits : 0 - 31 (32 bit)
GICD peripheral ID2 register
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIDR2 : peripheral ID2
bits : 0 - 31 (32 bit)
GICD peripheral ID3 register
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIDR3 : peripheral ID3
bits : 0 - 31 (32 bit)
GICD component ID0 register
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CIDR0 : component ID0
bits : 0 - 31 (32 bit)
GICD component ID1 register
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CIDR1 : component ID1
bits : 0 - 31 (32 bit)
GICD component ID2 register
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CIDR2 : component ID2
bits : 0 - 31 (32 bit)
GICD component ID3 register
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CIDR3 : component ID3
bits : 0 - 31 (32 bit)
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