\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
TZC configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NO_OF_REGIONS : Number fo regions
bits : 0 - 4 (5 bit)
ADDRESS_WIDTH : ADDRESS WIDTH
bits : 8 - 13 (6 bit)
NO_OF_FILTERS : Number of filters
bits : 24 - 25 (2 bit)
TZC interrupt status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATUS : Interrupt status for each filter
bits : 0 - 0 (1 bit)
OVERRUN : Permission failure overrun
bits : 8 - 9 (2 bit)
OVERLAP : Overlap violation for each filter
bits : 16 - 17 (2 bit)
TZC region 0 base address low register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BASE_ADDRESS_LOW : base address bits
bits : 12 - 31 (20 bit)
TZC region 0 top address low register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TOP_ADDRESS_LOW : Top address bits
bits : 12 - 31 (20 bit)
TZC region 0 attribute register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTER_EN : Region enable for each filter
bits : 0 - 1 (2 bit)
S_RD_EN : Secure global read enable
bits : 30 - 30 (1 bit)
S_WR_EN : Secure global write enable
bits : 31 - 31 (1 bit)
TZC region 0 ID access register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NSAID_RD_EN : Region enable for each filter
bits : 0 - 15 (16 bit)
NSAID_WR_EN : Secure global write enable
bits : 16 - 31 (16 bit)
TZC region 1 ID access register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)
TZC regions 1 top address low register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOP_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)
TZC region 2 attribute register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTER_EN : Region enable for each filter
bits : 0 - 1 (2 bit)
S_RD_EN : Secure global read enable
bits : 30 - 30 (1 bit)
S_WR_EN : Secure global write enable
bits : 31 - 31 (1 bit)
TZC region 1 ID access register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NSAID_RD_EN : Region enable for each filter
bits : 0 - 15 (16 bit)
NSAID_WR_EN : Secure global write enable
bits : 16 - 31 (16 bit)
TZC interrupt clear register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLEAR : Filter interrupt clear
bits : 0 - 1 (2 bit)
TZC region 2 ID access register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)
TZC regions 2 top address low register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOP_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)
TZC region 2 attribute register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTER_EN : Region enable for each filter
bits : 0 - 1 (2 bit)
S_RD_EN : Secure global read enable
bits : 30 - 30 (1 bit)
S_WR_EN : Secure global write enable
bits : 31 - 31 (1 bit)
TZC region 2 ID access register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NSAID_RD_EN : Region enable for each filter
bits : 0 - 15 (16 bit)
NSAID_WR_EN : Secure global write enable
bits : 16 - 31 (16 bit)
TZC region 3 ID access register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)
TZC regions 3 top address low register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOP_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)
TZC region 3 attribute register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTER_EN : Region enable for each filter
bits : 0 - 1 (2 bit)
S_RD_EN : Secure global read enable
bits : 30 - 30 (1 bit)
S_WR_EN : Secure global write enable
bits : 31 - 31 (1 bit)
TZC region 3 ID access register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NSAID_RD_EN : Region enable for each filter
bits : 0 - 15 (16 bit)
NSAID_WR_EN : Secure global write enable
bits : 16 - 31 (16 bit)
TZC region 4 ID access register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)
TZC regions 4 top address low register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOP_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)
TZC region 4 attribute register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTER_EN : Region enable for each filter
bits : 0 - 1 (2 bit)
S_RD_EN : Secure global read enable
bits : 30 - 30 (1 bit)
S_WR_EN : Secure global write enable
bits : 31 - 31 (1 bit)
TZC region 4 ID access register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NSAID_RD_EN : Region enable for each filter
bits : 0 - 15 (16 bit)
NSAID_WR_EN : Secure global write enable
bits : 16 - 31 (16 bit)
TZC region 5 ID access register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)
TZC regions 5 top address low register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOP_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)
TZC region 5 attribute register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTER_EN : Region enable for each filter
bits : 0 - 1 (2 bit)
S_RD_EN : Secure global read enable
bits : 30 - 30 (1 bit)
S_WR_EN : Secure global write enable
bits : 31 - 31 (1 bit)
TZC region 5 ID access register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NSAID_RD_EN : Region enable for each filter
bits : 0 - 15 (16 bit)
NSAID_WR_EN : Secure global write enable
bits : 16 - 31 (16 bit)
TZC region 6 ID access register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)
TZC regions 6 top address low register
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOP_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)
TZC region 6 attribute register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTER_EN : Region enable for each filter
bits : 0 - 1 (2 bit)
S_RD_EN : Secure global read enable
bits : 30 - 30 (1 bit)
S_WR_EN : Secure global write enable
bits : 31 - 31 (1 bit)
TZC region 6 ID access register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NSAID_RD_EN : Region enable for each filter
bits : 0 - 15 (16 bit)
NSAID_WR_EN : Secure global write enable
bits : 16 - 31 (16 bit)
TZC region 7 ID access register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)
TZC regions 7 top address low register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOP_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)
TZC region 7 attribute register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTER_EN : Region enable for each filter
bits : 0 - 1 (2 bit)
S_RD_EN : Secure global read enable
bits : 30 - 30 (1 bit)
S_WR_EN : Secure global write enable
bits : 31 - 31 (1 bit)
TZC region 7 ID access register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NSAID_RD_EN : Region enable for each filter
bits : 0 - 15 (16 bit)
NSAID_WR_EN : Secure global write enable
bits : 16 - 31 (16 bit)
TZC fail address low register0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR_STATUS_LOW : Fail address low bits
bits : 0 - 31 (32 bit)
TZC region 8 ID access register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)
TZC regions 8 top address low register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOP_ADDRESS_LOW : Base address bits[31:12] for region
bits : 12 - 31 (20 bit)
TZC region 8 attribute register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTER_EN : Region enable for each filter
bits : 0 - 1 (2 bit)
S_RD_EN : Secure global read enable
bits : 30 - 30 (1 bit)
S_WR_EN : Secure global write enable
bits : 31 - 31 (1 bit)
TZC region 8 ID access register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NSAID_RD_EN : Region enable for each filter
bits : 0 - 15 (16 bit)
NSAID_WR_EN : Secure global write enable
bits : 16 - 31 (16 bit)
TZC fail control register 0
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PRIVILEGE : Privilege access failure
bits : 20 - 20 (1 bit)
NON_SECURE : Non-secure access failure
bits : 21 - 21 (1 bit)
DIRECTION : Access failure direction
bits : 24 - 24 (1 bit)
TZC fail ID register 0
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : AXI fail ID
bits : 0 - 10 (11 bit)
TZC fail address low register1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR_STATUS_LOW : Fail address low bits
bits : 0 - 31 (32 bit)
TZC fail control register 1
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PRIVILEGE : Privilege access failure
bits : 20 - 20 (1 bit)
NON_SECURE : Non-secure access failure
bits : 21 - 21 (1 bit)
DIRECTION : Access failure direction
bits : 24 - 24 (1 bit)
TZC fail ID register 1
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : AXI fail ID
bits : 0 - 10 (11 bit)
TZC action register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REACTION_VALUE : Permission failure reaction
bits : 0 - 1 (2 bit)
TZC gate keeper register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPENREQ : Gate keeper open request
bits : 0 - 1 (2 bit)
OPENSTAT : Gate keeper status for each filter
bits : 16 - 17 (2 bit)
TZC speculation control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READSPEC_DISABLE : Read access speculation disable
bits : 0 - 0 (1 bit)
WRITESPEC_DISABLE : Write access speculation disable
bits : 1 - 1 (1 bit)
TZC peripheral ID 4 register
address_offset : 0xFD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PER_ID_4 : Peripheral ID 4
bits : 0 - 7 (8 bit)
TZC peripheral ID 5 register
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PER_ID_5 : Peripheral ID 5
bits : 0 - 7 (8 bit)
TZC peripheral ID 6 register
address_offset : 0xFD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PER_ID_6 : Peripheral ID 6
bits : 0 - 7 (8 bit)
TZC peripheral ID 7 register
address_offset : 0xFDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PER_ID_7 : Peripheral ID 7
bits : 0 - 7 (8 bit)
TZC peripheral ID 0 register
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PER_ID_0 : Peripheral ID 0
bits : 0 - 7 (8 bit)
TZC peripheral ID 1 register
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PER_ID_1 : Peripheral ID 1
bits : 0 - 7 (8 bit)
TZC peripheral ID 2 register
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PER_ID_2 : Peripheral ID 2
bits : 0 - 7 (8 bit)
TZC peripheral ID 3 register
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PER_ID_3 : Peripheral ID 3
bits : 0 - 7 (8 bit)
TZC component ID 0 register
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMP_ID_0 : Component ID 0
bits : 0 - 7 (8 bit)
TZC component ID 1 register
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMP_ID_1 : Component ID 1
bits : 0 - 7 (8 bit)
TZC component ID 2 register
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMP_ID_2 : Component ID 2
bits : 0 - 7 (8 bit)
TZC component ID 3 register
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMP_ID_3 : Component ID 3
bits : 0 - 7 (8 bit)
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