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address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected
Control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLEGRP0 : Enable group 0 interrupts
bits : 0 - 0 (1 bit)
ENABLEGRP1 : Enable group 1 interrupts
bits : 1 - 1 (1 bit)
ACKCTL : Acknowledge control
bits : 2 - 2 (1 bit)
FIQEN : FIQ enable for group 0 interrupts
bits : 3 - 3 (1 bit)
CBPR : BPR control
bits : 4 - 4 (1 bit)
FIQBYPDISGRP0 : FIQ bypass disable for group 0 interrupts
bits : 5 - 5 (1 bit)
IRQBYPDISGRP0 : IRQ bypass disable for group 0 interrupts
bits : 6 - 6 (1 bit)
FIQBYPDISGRP1 : Alias of FIQBYPDISGRP1 from the non-secure copy of this register.
bits : 7 - 7 (1 bit)
IRQBYPDISGRP1 : Alias of IRQBYPDISGRP1 from the non-secure copy of this register
bits : 8 - 8 (1 bit)
EOIMODES : EOI mode for secure accesses
bits : 9 - 9 (1 bit)
EOIMODENS : Alias of EOIMODENS from the non-secure copy of this register
bits : 10 - 10 (1 bit)
GICC control (non-secure access) register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CTLR
reset_Mask : 0x0
ENABLEGRP1 : Enable group1 interrupts
bits : 0 - 0 (1 bit)
FIQBYPDISGRP1 : FIQ bypass disable for group 1 interrupts
bits : 5 - 5 (1 bit)
IRQBYPDISGRP1 : IRQ bypass for group 1 interrupts
bits : 6 - 6 (1 bit)
EOIMODENS : EOI mode for non- secure accesses
bits : 9 - 9 (1 bit)
GICC end of interrupt register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EOIINTID : EOIINTID
bits : 0 - 9 (10 bit)
CPUID : CPUID
bits : 10 - 10 (1 bit)
GICC deactivate interrupt register
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTERRUPT_ID : INTERRUPT_ID
bits : 0 - 9 (10 bit)
CPUID : CPUID
bits : 10 - 10 (1 bit)
GICC running priority register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PRIORITY : current running priority on the CPU interface
bits : 3 - 7 (5 bit)
GICC highest priority pending interrupt register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PENDINTID : PENDINTID
bits : 0 - 9 (10 bit)
CPUID : CPUID
bits : 10 - 10 (1 bit)
GICC aliased binary point register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BINARY_POINT : BINARY_POINT
bits : 0 - 2 (3 bit)
GICC aliased interrupt acknowledge register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTERRUPT_ID : INTERRUPT_ID
bits : 0 - 9 (10 bit)
CPUID : CPUID
bits : 10 - 10 (1 bit)
GICC aliased end of interrupt register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EOIINTID : EOIINTID
bits : 0 - 9 (10 bit)
CPUID : CPUID
bits : 10 - 10 (1 bit)
GICC aliased highest priority pending interrupt register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PENDINTID : PENDINTID
bits : 0 - 9 (10 bit)
CPUID : CPUID
bits : 10 - 10 (1 bit)
GICC input priority mask register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY : priority mask level for the CPU interface
bits : 3 - 7 (5 bit)
GICC binary point register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BINARY_POINT : BINARY_POINT
bits : 0 - 2 (3 bit)
GICC binary point (non-secure access) register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : BPR
reset_Mask : 0x0
BINARY_POINT : BINARY_POINT
bits : 0 - 2 (3 bit)
GICC interrupt acknowledge register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTERRUPT_ID : The interrupt ID
bits : 0 - 9 (10 bit)
CPUID : CPUID
bits : 10 - 10 (1 bit)
GICC active priority register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APR0 : APR0
bits : 0 - 31 (32 bit)
GICC non-secure active priority register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NSAPR0 : NSAPR0
bits : 0 - 31 (32 bit)
GICC interface identification register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IMPLEMENTER : IMPLEMENTER
bits : 0 - 11 (12 bit)
REVISION : REVISION
bits : 12 - 15 (4 bit)
ARCH : ARCH
bits : 16 - 19 (4 bit)
PRODUCTID : PRODUCTID
bits : 20 - 31 (12 bit)
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