\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
ETZPC ROM secure size definition
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
r0size : r0size
bits : 0 - 9 (10 bit)
access : read-write
lock : lock
bits : 31 - 31 (1 bit)
access : read-write
ETZPC securable peripheral definition register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
decprot0 : decprot0
bits : 0 - 1 (2 bit)
access : read-write
decprot1 : decprot1
bits : 2 - 3 (2 bit)
access : read-write
decprot2 : decprot2
bits : 4 - 5 (2 bit)
access : read-write
decprot3 : decprot3
bits : 6 - 7 (2 bit)
access : read-write
decprot4 : decprot4
bits : 8 - 9 (2 bit)
access : read-write
decprot5 : decprot5
bits : 10 - 11 (2 bit)
access : read-write
decprot6 : decprot6
bits : 12 - 13 (2 bit)
access : read-write
decprot7 : decprot7
bits : 14 - 15 (2 bit)
access : read-write
decprot8 : decprot8
bits : 16 - 17 (2 bit)
access : read-write
decprot9 : decprot9
bits : 18 - 19 (2 bit)
access : read-write
decprot10 : decprot10
bits : 20 - 21 (2 bit)
access : read-write
decprot11 : decprot11
bits : 22 - 23 (2 bit)
access : read-write
decprot12 : decprot12
bits : 24 - 25 (2 bit)
access : read-write
ETZPC securable peripheral definition register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK0 : LOCK0
bits : 0 - 0 (1 bit)
access : read-write
LOCK1 : LOCK1
bits : 1 - 1 (1 bit)
access : read-write
LOCK2 : LOCK2
bits : 2 - 2 (1 bit)
access : read-write
LOCK3 : LOCK3
bits : 3 - 3 (1 bit)
access : read-write
LOCK4 : LOCK4
bits : 4 - 4 (1 bit)
access : read-write
LOCK5 : LOCK5
bits : 5 - 5 (1 bit)
access : read-write
LOCK6 : LOCK6
bits : 6 - 6 (1 bit)
access : read-write
LOCK7 : LOCK7
bits : 7 - 7 (1 bit)
access : read-write
LOCK8 : LOCK8
bits : 8 - 8 (1 bit)
access : read-write
LOCK9 : LOCK9
bits : 9 - 9 (1 bit)
access : read-write
LOCK10 : LOCK10
bits : 10 - 10 (1 bit)
access : read-write
LOCK11 : LOCK11
bits : 11 - 11 (1 bit)
access : read-write
LOCK12 : LOCK12
bits : 12 - 12 (1 bit)
access : read-write
ETZPC IP hardware configuration register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NUM_TZMA : NUM_TZMA
bits : 0 - 7 (8 bit)
access : read-only
NUM_PER_SEC : NUM_PER_SEC
bits : 8 - 15 (8 bit)
access : read-only
NUM_AHB_SEC : NUM_AHB_SEC
bits : 16 - 23 (8 bit)
access : read-only
CHUNKS1N4 : CHUNKS1N4
bits : 24 - 31 (8 bit)
access : read-only
ETZPC IP version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINREV : MINREV
bits : 0 - 3 (4 bit)
access : read-only
MAJREV : MAJREV
bits : 4 - 7 (4 bit)
access : read-only
ETZPC IP version register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : ID
bits : 0 - 31 (32 bit)
access : read-only
ETZPC IP version register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SID : SID
bits : 0 - 31 (32 bit)
access : read-only
ETZPC RAM secure size definition
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
r0size : r0size
bits : 0 - 9 (10 bit)
access : read-write
lock : lock
bits : 31 - 31 (1 bit)
access : read-write
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