\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Write-only register. A read request returns all zeros.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : START
bits : 0 - 0 (1 bit)
access : write-only
STOP : STOP
bits : 1 - 1 (1 bit)
access : write-only
DDRPERFM interrupt enable register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVFIE : OVFIE
bits : 0 - 0 (1 bit)
access : read-write
DDRPERFM interrupt status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OVFF : OVFF
bits : 0 - 0 (1 bit)
access : read-only
Write-only register. A read request returns all zeros
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : OVF
bits : 0 - 0 (1 bit)
access : write-only
DDRPERFM time counter register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : CNT
bits : 0 - 31 (32 bit)
access : read-only
DDRPERFM hardware configuration register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NCNT : NCNT
bits : 0 - 3 (4 bit)
access : read-only
DDRPERFM version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINREV : MINREV
bits : 0 - 3 (4 bit)
access : read-only
MAJREV : MAJREV
bits : 4 - 7 (4 bit)
access : read-only
DDRPERFM ID register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : ID
bits : 0 - 31 (32 bit)
access : read-only
DDRPERFM magic ID register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SID : SID
bits : 0 - 31 (32 bit)
access : read-only
DDRPERFM configurationl register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 3 (4 bit)
access : read-write
SEL : SEL
bits : 16 - 17 (2 bit)
access : read-write
DDRPERFM event counter 0 register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : CNT
bits : 0 - 31 (32 bit)
access : read-only
DDRPERFM event counter 1 register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : CNT
bits : 0 - 31 (32 bit)
access : read-only
DDRPERFM event counter 2 register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : CNT
bits : 0 - 31 (32 bit)
access : read-only
DDRPERFM event counter 3 register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : CNT
bits : 0 - 31 (32 bit)
access : read-only
DDRPERFM status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVF : COVF
bits : 0 - 3 (4 bit)
access : read-only
BUSY : BUSY
bits : 16 - 16 (1 bit)
access : read-only
TOVF : TOVF
bits : 31 - 31 (1 bit)
access : read-only
Write-only register. A read request returns all zeros
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCLR : CCLR
bits : 0 - 3 (4 bit)
access : write-only
TCLR : TCLR
bits : 31 - 31 (1 bit)
access : write-only
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