\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALGODIR : Algorithm direction
bits : 2 - 2 (1 bit)
access : read-write
ALGOMODE0 : Algorithm mode
bits : 3 - 5 (3 bit)
access : read-write
DATATYPE : Data type selection
bits : 6 - 7 (2 bit)
access : read-write
KEYSIZE : Key size selection (AES mode only)
bits : 8 - 9 (2 bit)
access : read-write
FFLUSH : FIFO flush
bits : 14 - 14 (1 bit)
access : write-only
CRYPEN : Cryptographic processor enable
bits : 15 - 15 (1 bit)
access : read-write
GCM_CCMPH : GCM_CCMPH
bits : 16 - 17 (2 bit)
access : read-write
ALGOMODE3 : ALGOMODE
bits : 19 - 19 (1 bit)
access : read-write
NPBLB : NPBLB
bits : 20 - 23 (4 bit)
access : read-write
CRYP DMA control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIEN : DIEN
bits : 0 - 0 (1 bit)
access : read-write
DOEN : DOEN
bits : 1 - 1 (1 bit)
access : read-write
The CRYP_IMSCR register is the interrupt mask set or clear register. It is a read/write register. When a read operation is performed, this register gives the current value of the mask applied to the relevant interrupt. Writing 1 to the particular bit sets the mask, thus enabling the interrupt to be read. Writing 0 to this bit clears the corresponding mask. All the bits are cleared to 0 when the peripheral is reset.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIM : INIM
bits : 0 - 0 (1 bit)
access : read-write
OUTIM : OUTIM
bits : 1 - 1 (1 bit)
access : read-write
The CRYP_RISR register is the raw interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current raw status of the corresponding interrupt, i.e. the interrupt information without taking CRYP_IMSCR mask into account. Write operations have no effect.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INRIS : INRIS
bits : 0 - 0 (1 bit)
access : read-only
OUTRIS : OUTRIS
bits : 1 - 1 (1 bit)
access : read-only
The CRYP_MISR register is the masked interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current masked status of the corresponding interrupt, i.e. the interrupt information taking CRYP_IMSCR mask into account. Write operations have no effect.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INMIS : INMIS
bits : 0 - 0 (1 bit)
access : read-only
OUTMIS : OUTMIS
bits : 1 - 1 (1 bit)
access : read-only
CRYP key registers contain the cryptographic keys. In DES/TDES mode, the keys are 64-bit binary values (number from left to right, that is the leftmost bit is bit 1) and named K1, K2 and K3 (K0 is not used). Each key consists of 56 information bits and 8 parity bits. In AES mode, the key is considered as a single 128, 192 or 256 bits long sequence K0K1K2...K127/191/255. The AES key is entered into the registers as follows: for AES-128: K0..K127 corresponds to b127..b0 (b255..b128 are not used), for AES-192: K0..K191 corresponds to b191..b0 (b255..b192 are not used), for AES-256: K0..K255 corresponds to b255..b0. In all cases key bit K0 is the leftmost bit in CRYP inner memory and register bit b0 is the rightmost bit in corresponding CRYP_KxLR key register. For more information refer to Section23.3.17: CRYP key registers. Write accesses to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
K224 : K224
bits : 0 - 0 (1 bit)
access : write-only
K225 : K225
bits : 1 - 1 (1 bit)
access : write-only
K226 : K226
bits : 2 - 2 (1 bit)
access : write-only
K227 : K227
bits : 3 - 3 (1 bit)
access : write-only
K228 : K228
bits : 4 - 4 (1 bit)
access : write-only
K229 : K229
bits : 5 - 5 (1 bit)
access : write-only
K230 : K230
bits : 6 - 6 (1 bit)
access : write-only
K231 : K231
bits : 7 - 7 (1 bit)
access : write-only
K232 : K232
bits : 8 - 8 (1 bit)
access : write-only
K233 : K233
bits : 9 - 9 (1 bit)
access : write-only
K234 : K234
bits : 10 - 10 (1 bit)
access : write-only
K235 : K235
bits : 11 - 11 (1 bit)
access : write-only
K236 : K236
bits : 12 - 12 (1 bit)
access : write-only
K237 : K237
bits : 13 - 13 (1 bit)
access : write-only
K238 : K238
bits : 14 - 14 (1 bit)
access : write-only
K239 : K239
bits : 15 - 15 (1 bit)
access : write-only
K240 : K240
bits : 16 - 16 (1 bit)
access : write-only
K241 : K241
bits : 17 - 17 (1 bit)
access : write-only
K242 : K242
bits : 18 - 18 (1 bit)
access : write-only
K243 : K243
bits : 19 - 19 (1 bit)
access : write-only
K244 : K244
bits : 20 - 20 (1 bit)
access : write-only
K245 : K245
bits : 21 - 21 (1 bit)
access : write-only
K246 : K246
bits : 22 - 22 (1 bit)
access : write-only
K247 : K247
bits : 23 - 23 (1 bit)
access : write-only
K248 : K248
bits : 24 - 24 (1 bit)
access : write-only
K249 : K249
bits : 25 - 25 (1 bit)
access : write-only
K250 : K250
bits : 26 - 26 (1 bit)
access : write-only
K251 : K251
bits : 27 - 27 (1 bit)
access : write-only
K252 : K252
bits : 28 - 28 (1 bit)
access : write-only
K253 : K253
bits : 29 - 29 (1 bit)
access : write-only
K254 : K254
bits : 30 - 30 (1 bit)
access : write-only
K255 : K255
bits : 31 - 31 (1 bit)
access : write-only
Refer to Section23.6.9: CRYP key register 0L (CRYP_K0LR) for details.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
K192 : K192
bits : 0 - 0 (1 bit)
access : write-only
K193 : K193
bits : 1 - 1 (1 bit)
access : write-only
K194 : K194
bits : 2 - 2 (1 bit)
access : write-only
K195 : K195
bits : 3 - 3 (1 bit)
access : write-only
K196 : K196
bits : 4 - 4 (1 bit)
access : write-only
K197 : K197
bits : 5 - 5 (1 bit)
access : write-only
K198 : K198
bits : 6 - 6 (1 bit)
access : write-only
K199 : K199
bits : 7 - 7 (1 bit)
access : write-only
K200 : K200
bits : 8 - 8 (1 bit)
access : write-only
K201 : K201
bits : 9 - 9 (1 bit)
access : write-only
K202 : K202
bits : 10 - 10 (1 bit)
access : write-only
K203 : K203
bits : 11 - 11 (1 bit)
access : write-only
K204 : K204
bits : 12 - 12 (1 bit)
access : write-only
K205 : K205
bits : 13 - 13 (1 bit)
access : write-only
K206 : K206
bits : 14 - 14 (1 bit)
access : write-only
K207 : K207
bits : 15 - 15 (1 bit)
access : write-only
K208 : K208
bits : 16 - 16 (1 bit)
access : write-only
K209 : K209
bits : 17 - 17 (1 bit)
access : write-only
K210 : K210
bits : 18 - 18 (1 bit)
access : write-only
K211 : K211
bits : 19 - 19 (1 bit)
access : write-only
K212 : K212
bits : 20 - 20 (1 bit)
access : write-only
K213 : K213
bits : 21 - 21 (1 bit)
access : write-only
K214 : K214
bits : 22 - 22 (1 bit)
access : write-only
K215 : K215
bits : 23 - 23 (1 bit)
access : write-only
K216 : K216
bits : 24 - 24 (1 bit)
access : write-only
K217 : K217
bits : 25 - 25 (1 bit)
access : write-only
K218 : K218
bits : 26 - 26 (1 bit)
access : write-only
K219 : K219
bits : 27 - 27 (1 bit)
access : write-only
K220 : K220
bits : 28 - 28 (1 bit)
access : write-only
K221 : K221
bits : 29 - 29 (1 bit)
access : write-only
K222 : K222
bits : 30 - 30 (1 bit)
access : write-only
K223 : K223
bits : 31 - 31 (1 bit)
access : write-only
Refer to Section23.6.9: CRYP key register 0L (CRYP_K0LR) for details.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
K160 : K160
bits : 0 - 0 (1 bit)
access : write-only
K161 : K161
bits : 1 - 1 (1 bit)
access : write-only
K162 : K162
bits : 2 - 2 (1 bit)
access : write-only
K163 : K163
bits : 3 - 3 (1 bit)
access : write-only
K164 : K164
bits : 4 - 4 (1 bit)
access : write-only
K165 : K165
bits : 5 - 5 (1 bit)
access : write-only
K166 : K166
bits : 6 - 6 (1 bit)
access : write-only
K167 : K167
bits : 7 - 7 (1 bit)
access : write-only
K168 : K168
bits : 8 - 8 (1 bit)
access : write-only
K169 : K169
bits : 9 - 9 (1 bit)
access : write-only
K170 : K170
bits : 10 - 10 (1 bit)
access : write-only
K171 : K171
bits : 11 - 11 (1 bit)
access : write-only
K172 : K172
bits : 12 - 12 (1 bit)
access : write-only
K173 : K173
bits : 13 - 13 (1 bit)
access : write-only
K174 : K174
bits : 14 - 14 (1 bit)
access : write-only
K175 : K175
bits : 15 - 15 (1 bit)
access : write-only
K176 : K176
bits : 16 - 16 (1 bit)
access : write-only
K177 : K177
bits : 17 - 17 (1 bit)
access : write-only
K178 : K178
bits : 18 - 18 (1 bit)
access : write-only
K179 : K179
bits : 19 - 19 (1 bit)
access : write-only
K180 : K180
bits : 20 - 20 (1 bit)
access : write-only
K181 : K181
bits : 21 - 21 (1 bit)
access : write-only
K182 : K182
bits : 22 - 22 (1 bit)
access : write-only
K183 : K183
bits : 23 - 23 (1 bit)
access : write-only
K184 : K184
bits : 24 - 24 (1 bit)
access : write-only
K185 : K185
bits : 25 - 25 (1 bit)
access : write-only
K186 : K186
bits : 26 - 26 (1 bit)
access : write-only
K187 : K187
bits : 27 - 27 (1 bit)
access : write-only
K188 : K188
bits : 28 - 28 (1 bit)
access : write-only
K189 : K189
bits : 29 - 29 (1 bit)
access : write-only
K190 : K190
bits : 30 - 30 (1 bit)
access : write-only
K191 : K191
bits : 31 - 31 (1 bit)
access : write-only
Refer to Section23.6.9: CRYP key register 0L (CRYP_K0LR) for details.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
K128 : K128
bits : 0 - 0 (1 bit)
access : write-only
K129 : K129
bits : 1 - 1 (1 bit)
access : write-only
K130 : K130
bits : 2 - 2 (1 bit)
access : write-only
K131 : K131
bits : 3 - 3 (1 bit)
access : write-only
K132 : K132
bits : 4 - 4 (1 bit)
access : write-only
K133 : K133
bits : 5 - 5 (1 bit)
access : write-only
K134 : K134
bits : 6 - 6 (1 bit)
access : write-only
K135 : K135
bits : 7 - 7 (1 bit)
access : write-only
K136 : K136
bits : 8 - 8 (1 bit)
access : write-only
K137 : K137
bits : 9 - 9 (1 bit)
access : write-only
K138 : K138
bits : 10 - 10 (1 bit)
access : write-only
K139 : K139
bits : 11 - 11 (1 bit)
access : write-only
K140 : K140
bits : 12 - 12 (1 bit)
access : write-only
K141 : K141
bits : 13 - 13 (1 bit)
access : write-only
K142 : K142
bits : 14 - 14 (1 bit)
access : write-only
K143 : K143
bits : 15 - 15 (1 bit)
access : write-only
K144 : K144
bits : 16 - 16 (1 bit)
access : write-only
K145 : K145
bits : 17 - 17 (1 bit)
access : write-only
K146 : K146
bits : 18 - 18 (1 bit)
access : write-only
K147 : K147
bits : 19 - 19 (1 bit)
access : write-only
K148 : K148
bits : 20 - 20 (1 bit)
access : write-only
K149 : K149
bits : 21 - 21 (1 bit)
access : write-only
K150 : K150
bits : 22 - 22 (1 bit)
access : write-only
K151 : K151
bits : 23 - 23 (1 bit)
access : write-only
K152 : K152
bits : 24 - 24 (1 bit)
access : write-only
K153 : K153
bits : 25 - 25 (1 bit)
access : write-only
K154 : K154
bits : 26 - 26 (1 bit)
access : write-only
K155 : K155
bits : 27 - 27 (1 bit)
access : write-only
K156 : K156
bits : 28 - 28 (1 bit)
access : write-only
K157 : K157
bits : 29 - 29 (1 bit)
access : write-only
K158 : K158
bits : 30 - 30 (1 bit)
access : write-only
K159 : K159
bits : 31 - 31 (1 bit)
access : write-only
Refer to Section23.6.9: CRYP key register 0L (CRYP_K0LR) for details.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
K96 : K96
bits : 0 - 0 (1 bit)
access : write-only
K97 : K97
bits : 1 - 1 (1 bit)
access : write-only
K98 : K98
bits : 2 - 2 (1 bit)
access : write-only
K99 : K99
bits : 3 - 3 (1 bit)
access : write-only
K100 : K100
bits : 4 - 4 (1 bit)
access : write-only
K101 : K101
bits : 5 - 5 (1 bit)
access : write-only
K102 : K102
bits : 6 - 6 (1 bit)
access : write-only
K103 : K103
bits : 7 - 7 (1 bit)
access : write-only
K104 : K104
bits : 8 - 8 (1 bit)
access : write-only
K105 : K105
bits : 9 - 9 (1 bit)
access : write-only
K106 : K106
bits : 10 - 10 (1 bit)
access : write-only
K107 : K107
bits : 11 - 11 (1 bit)
access : write-only
K108 : K108
bits : 12 - 12 (1 bit)
access : write-only
K109 : K109
bits : 13 - 13 (1 bit)
access : write-only
K110 : K110
bits : 14 - 14 (1 bit)
access : write-only
K111 : K111
bits : 15 - 15 (1 bit)
access : write-only
K112 : K112
bits : 16 - 16 (1 bit)
access : write-only
K113 : K113
bits : 17 - 17 (1 bit)
access : write-only
K114 : K114
bits : 18 - 18 (1 bit)
access : write-only
K115 : K115
bits : 19 - 19 (1 bit)
access : write-only
K116 : K116
bits : 20 - 20 (1 bit)
access : write-only
K117 : K117
bits : 21 - 21 (1 bit)
access : write-only
K118 : K118
bits : 22 - 22 (1 bit)
access : write-only
K119 : K119
bits : 23 - 23 (1 bit)
access : write-only
K120 : K120
bits : 24 - 24 (1 bit)
access : write-only
K121 : K121
bits : 25 - 25 (1 bit)
access : write-only
K122 : K122
bits : 26 - 26 (1 bit)
access : write-only
K123 : K123
bits : 27 - 27 (1 bit)
access : write-only
K124 : K124
bits : 28 - 28 (1 bit)
access : write-only
K125 : K125
bits : 29 - 29 (1 bit)
access : write-only
K126 : K126
bits : 30 - 30 (1 bit)
access : write-only
K127 : K127
bits : 31 - 31 (1 bit)
access : write-only
Refer to Section23.6.9: CRYP key register 0L (CRYP_K0LR) for details.
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
K64 : K64
bits : 0 - 0 (1 bit)
access : write-only
K65 : K65
bits : 1 - 1 (1 bit)
access : write-only
K66 : K66
bits : 2 - 2 (1 bit)
access : write-only
K67 : K67
bits : 3 - 3 (1 bit)
access : write-only
K68 : K68
bits : 4 - 4 (1 bit)
access : write-only
K69 : K69
bits : 5 - 5 (1 bit)
access : write-only
K70 : K70
bits : 6 - 6 (1 bit)
access : write-only
K71 : K71
bits : 7 - 7 (1 bit)
access : write-only
K72 : K72
bits : 8 - 8 (1 bit)
access : write-only
K73 : K73
bits : 9 - 9 (1 bit)
access : write-only
K74 : K74
bits : 10 - 10 (1 bit)
access : write-only
K75 : K75
bits : 11 - 11 (1 bit)
access : write-only
K76 : K76
bits : 12 - 12 (1 bit)
access : write-only
K77 : K77
bits : 13 - 13 (1 bit)
access : write-only
K78 : K78
bits : 14 - 14 (1 bit)
access : write-only
K79 : K79
bits : 15 - 15 (1 bit)
access : write-only
K80 : K80
bits : 16 - 16 (1 bit)
access : write-only
K81 : K81
bits : 17 - 17 (1 bit)
access : write-only
K82 : K82
bits : 18 - 18 (1 bit)
access : write-only
K83 : K83
bits : 19 - 19 (1 bit)
access : write-only
K84 : K84
bits : 20 - 20 (1 bit)
access : write-only
K85 : K85
bits : 21 - 21 (1 bit)
access : write-only
K86 : K86
bits : 22 - 22 (1 bit)
access : write-only
K87 : K87
bits : 23 - 23 (1 bit)
access : write-only
K88 : K88
bits : 24 - 24 (1 bit)
access : write-only
K89 : K89
bits : 25 - 25 (1 bit)
access : write-only
K90 : K90
bits : 26 - 26 (1 bit)
access : write-only
K91 : K91
bits : 27 - 27 (1 bit)
access : write-only
K92 : K92
bits : 28 - 28 (1 bit)
access : write-only
K93 : K93
bits : 29 - 29 (1 bit)
access : write-only
K94 : K94
bits : 30 - 30 (1 bit)
access : write-only
K95 : K95
bits : 31 - 31 (1 bit)
access : write-only
Refer to Section23.6.9: CRYP key register 0L (CRYP_K0LR) for details.
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
K32 : K32
bits : 0 - 0 (1 bit)
access : write-only
K33 : K33
bits : 1 - 1 (1 bit)
access : write-only
K34 : K34
bits : 2 - 2 (1 bit)
access : write-only
K35 : K35
bits : 3 - 3 (1 bit)
access : write-only
K36 : K36
bits : 4 - 4 (1 bit)
access : write-only
K37 : K37
bits : 5 - 5 (1 bit)
access : write-only
K38 : K38
bits : 6 - 6 (1 bit)
access : write-only
K39 : K39
bits : 7 - 7 (1 bit)
access : write-only
K40 : K40
bits : 8 - 8 (1 bit)
access : write-only
K41 : K41
bits : 9 - 9 (1 bit)
access : write-only
K42 : K42
bits : 10 - 10 (1 bit)
access : write-only
K43 : K43
bits : 11 - 11 (1 bit)
access : write-only
K44 : K44
bits : 12 - 12 (1 bit)
access : write-only
K45 : K45
bits : 13 - 13 (1 bit)
access : write-only
K46 : K46
bits : 14 - 14 (1 bit)
access : write-only
K47 : K47
bits : 15 - 15 (1 bit)
access : write-only
K48 : K48
bits : 16 - 16 (1 bit)
access : write-only
K49 : K49
bits : 17 - 17 (1 bit)
access : write-only
K50 : K50
bits : 18 - 18 (1 bit)
access : write-only
K51 : K51
bits : 19 - 19 (1 bit)
access : write-only
K52 : K52
bits : 20 - 20 (1 bit)
access : write-only
K53 : K53
bits : 21 - 21 (1 bit)
access : write-only
K54 : K54
bits : 22 - 22 (1 bit)
access : write-only
K55 : K55
bits : 23 - 23 (1 bit)
access : write-only
K56 : K56
bits : 24 - 24 (1 bit)
access : write-only
K57 : K57
bits : 25 - 25 (1 bit)
access : write-only
K58 : K58
bits : 26 - 26 (1 bit)
access : write-only
K59 : K59
bits : 27 - 27 (1 bit)
access : write-only
K60 : K60
bits : 28 - 28 (1 bit)
access : write-only
K61 : K61
bits : 29 - 29 (1 bit)
access : write-only
K62 : K62
bits : 30 - 30 (1 bit)
access : write-only
K63 : K63
bits : 31 - 31 (1 bit)
access : write-only
Refer to Section23.6.9: CRYP key register 0L (CRYP_K0LR) for details.
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
K0 : K0
bits : 0 - 0 (1 bit)
access : write-only
K1 : K1
bits : 1 - 1 (1 bit)
access : write-only
K2 : K2
bits : 2 - 2 (1 bit)
access : write-only
K3 : K3
bits : 3 - 3 (1 bit)
access : write-only
K4 : K4
bits : 4 - 4 (1 bit)
access : write-only
K5 : K5
bits : 5 - 5 (1 bit)
access : write-only
K6 : K6
bits : 6 - 6 (1 bit)
access : write-only
K7 : K7
bits : 7 - 7 (1 bit)
access : write-only
K8 : K8
bits : 8 - 8 (1 bit)
access : write-only
K9 : K9
bits : 9 - 9 (1 bit)
access : write-only
K10 : K10
bits : 10 - 10 (1 bit)
access : write-only
K11 : K11
bits : 11 - 11 (1 bit)
access : write-only
K12 : K12
bits : 12 - 12 (1 bit)
access : write-only
K13 : K13
bits : 13 - 13 (1 bit)
access : write-only
K14 : K14
bits : 14 - 14 (1 bit)
access : write-only
K15 : K15
bits : 15 - 15 (1 bit)
access : write-only
K16 : K16
bits : 16 - 16 (1 bit)
access : write-only
K17 : K17
bits : 17 - 17 (1 bit)
access : write-only
K18 : K18
bits : 18 - 18 (1 bit)
access : write-only
K19 : K19
bits : 19 - 19 (1 bit)
access : write-only
K20 : K20
bits : 20 - 20 (1 bit)
access : write-only
K21 : K21
bits : 21 - 21 (1 bit)
access : write-only
K22 : K22
bits : 22 - 22 (1 bit)
access : write-only
K23 : K23
bits : 23 - 23 (1 bit)
access : write-only
K24 : K24
bits : 24 - 24 (1 bit)
access : write-only
K25 : K25
bits : 25 - 25 (1 bit)
access : write-only
K26 : K26
bits : 26 - 26 (1 bit)
access : write-only
K27 : K27
bits : 27 - 27 (1 bit)
access : write-only
K28 : K28
bits : 28 - 28 (1 bit)
access : write-only
K29 : K29
bits : 29 - 29 (1 bit)
access : write-only
K30 : K30
bits : 30 - 30 (1 bit)
access : write-only
K31 : K31
bits : 31 - 31 (1 bit)
access : write-only
CRYP hardware configuration register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFG1 : CFG1
bits : 0 - 3 (4 bit)
access : read-only
CFG2 : CFG2
bits : 4 - 7 (4 bit)
access : read-only
CFG3 : CFG3
bits : 8 - 11 (4 bit)
access : read-only
CFG4 : CFG4
bits : 12 - 15 (4 bit)
access : read-only
CRYP HW Version Register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VER : VER
bits : 0 - 7 (8 bit)
access : read-only
CRYP Identification
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : ID
bits : 0 - 31 (32 bit)
access : read-only
CRYP HW Magic ID
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MID : MID
bits : 0 - 31 (32 bit)
access : read-only
CRYP status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IFEM : IFEM
bits : 0 - 0 (1 bit)
access : read-only
IFNF : IFNF
bits : 1 - 1 (1 bit)
access : read-only
OFNE : OFNE
bits : 2 - 2 (1 bit)
access : read-only
OFFU : OFFU
bits : 3 - 3 (1 bit)
access : read-only
BUSY : BUSY
bits : 4 - 4 (1 bit)
access : read-only
The CRYP_IV0...1(L/R)R are the left-word and right-word registers for the initialization vector (64 bits for DES/TDES and 128 bits for AES). For more information refer to Section23.3.18: CRYP initialization vector registers. IV0 is the leftmost bit whereas IV63 (DES, TDES) or IV127 (AES) are the rightmost bits of the initialization vector. IV1(L/R)R is used only in the AES. Only CRYP_IV0(L/R) is used in DES/TDES. Write access to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register).
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IV31 : IV31
bits : 0 - 0 (1 bit)
access : read-write
IV30 : IV30
bits : 1 - 1 (1 bit)
access : read-write
IV29 : IV29
bits : 2 - 2 (1 bit)
access : read-write
IV28 : IV28
bits : 3 - 3 (1 bit)
access : read-write
IV27 : IV27
bits : 4 - 4 (1 bit)
access : read-write
IV26 : IV26
bits : 5 - 5 (1 bit)
access : read-write
IV25 : IV25
bits : 6 - 6 (1 bit)
access : read-write
IV24 : IV24
bits : 7 - 7 (1 bit)
access : read-write
IV23 : IV23
bits : 8 - 8 (1 bit)
access : read-write
IV22 : IV22
bits : 9 - 9 (1 bit)
access : read-write
IV21 : IV21
bits : 10 - 10 (1 bit)
access : read-write
IV20 : IV20
bits : 11 - 11 (1 bit)
access : read-write
IV19 : IV19
bits : 12 - 12 (1 bit)
access : read-write
IV18 : IV18
bits : 13 - 13 (1 bit)
access : read-write
IV17 : IV17
bits : 14 - 14 (1 bit)
access : read-write
IV16 : IV16
bits : 15 - 15 (1 bit)
access : read-write
IV15 : IV15
bits : 16 - 16 (1 bit)
access : read-write
IV14 : IV14
bits : 17 - 17 (1 bit)
access : read-write
IV13 : IV13
bits : 18 - 18 (1 bit)
access : read-write
IV12 : IV12
bits : 19 - 19 (1 bit)
access : read-write
IV11 : IV11
bits : 20 - 20 (1 bit)
access : read-write
IV10 : IV10
bits : 21 - 21 (1 bit)
access : read-write
IV9 : IV9
bits : 22 - 22 (1 bit)
access : read-write
IV8 : IV8
bits : 23 - 23 (1 bit)
access : read-write
IV7 : IV7
bits : 24 - 24 (1 bit)
access : read-write
IV6 : IV6
bits : 25 - 25 (1 bit)
access : read-write
IV5 : IV5
bits : 26 - 26 (1 bit)
access : read-write
IV4 : IV4
bits : 27 - 27 (1 bit)
access : read-write
IV3 : IV3
bits : 28 - 28 (1 bit)
access : read-write
IV2 : IV2
bits : 29 - 29 (1 bit)
access : read-write
IV1 : IV1
bits : 30 - 30 (1 bit)
access : read-write
IV0 : IV0
bits : 31 - 31 (1 bit)
access : read-write
Refer to Section23.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IV63 : IV63
bits : 0 - 0 (1 bit)
access : read-write
IV62 : IV62
bits : 1 - 1 (1 bit)
access : read-write
IV61 : IV61
bits : 2 - 2 (1 bit)
access : read-write
IV60 : IV60
bits : 3 - 3 (1 bit)
access : read-write
IV59 : IV59
bits : 4 - 4 (1 bit)
access : read-write
IV58 : IV58
bits : 5 - 5 (1 bit)
access : read-write
IV57 : IV57
bits : 6 - 6 (1 bit)
access : read-write
IV56 : IV56
bits : 7 - 7 (1 bit)
access : read-write
IV55 : IV55
bits : 8 - 8 (1 bit)
access : read-write
IV54 : IV54
bits : 9 - 9 (1 bit)
access : read-write
IV53 : IV53
bits : 10 - 10 (1 bit)
access : read-write
IV52 : IV52
bits : 11 - 11 (1 bit)
access : read-write
IV51 : IV51
bits : 12 - 12 (1 bit)
access : read-write
IV50 : IV50
bits : 13 - 13 (1 bit)
access : read-write
IV49 : IV49
bits : 14 - 14 (1 bit)
access : read-write
IV48 : IV48
bits : 15 - 15 (1 bit)
access : read-write
IV47 : IV47
bits : 16 - 16 (1 bit)
access : read-write
IV46 : IV46
bits : 17 - 17 (1 bit)
access : read-write
IV45 : IV45
bits : 18 - 18 (1 bit)
access : read-write
IV44 : IV44
bits : 19 - 19 (1 bit)
access : read-write
IV43 : IV43
bits : 20 - 20 (1 bit)
access : read-write
IV42 : IV42
bits : 21 - 21 (1 bit)
access : read-write
IV41 : IV41
bits : 22 - 22 (1 bit)
access : read-write
IV40 : IV40
bits : 23 - 23 (1 bit)
access : read-write
IV39 : IV39
bits : 24 - 24 (1 bit)
access : read-write
IV38 : IV38
bits : 25 - 25 (1 bit)
access : read-write
IV37 : IV37
bits : 26 - 26 (1 bit)
access : read-write
IV36 : IV36
bits : 27 - 27 (1 bit)
access : read-write
IV35 : IV35
bits : 28 - 28 (1 bit)
access : read-write
IV34 : IV34
bits : 29 - 29 (1 bit)
access : read-write
IV33 : IV33
bits : 30 - 30 (1 bit)
access : read-write
IV32 : IV32
bits : 31 - 31 (1 bit)
access : read-write
Refer to Section23.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details.
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IV95 : IV95
bits : 0 - 0 (1 bit)
access : read-write
IV94 : IV94
bits : 1 - 1 (1 bit)
access : read-write
IV93 : IV93
bits : 2 - 2 (1 bit)
access : read-write
IV92 : IV92
bits : 3 - 3 (1 bit)
access : read-write
IV91 : IV91
bits : 4 - 4 (1 bit)
access : read-write
IV90 : IV90
bits : 5 - 5 (1 bit)
access : read-write
IV89 : IV89
bits : 6 - 6 (1 bit)
access : read-write
IV88 : IV88
bits : 7 - 7 (1 bit)
access : read-write
IV87 : IV87
bits : 8 - 8 (1 bit)
access : read-write
IV86 : IV86
bits : 9 - 9 (1 bit)
access : read-write
IV85 : IV85
bits : 10 - 10 (1 bit)
access : read-write
IV84 : IV84
bits : 11 - 11 (1 bit)
access : read-write
IV83 : IV83
bits : 12 - 12 (1 bit)
access : read-write
IV82 : IV82
bits : 13 - 13 (1 bit)
access : read-write
IV81 : IV81
bits : 14 - 14 (1 bit)
access : read-write
IV80 : IV80
bits : 15 - 15 (1 bit)
access : read-write
IV79 : IV79
bits : 16 - 16 (1 bit)
access : read-write
IV78 : IV78
bits : 17 - 17 (1 bit)
access : read-write
IV77 : IV77
bits : 18 - 18 (1 bit)
access : read-write
IV76 : IV76
bits : 19 - 19 (1 bit)
access : read-write
IV75 : IV75
bits : 20 - 20 (1 bit)
access : read-write
IV74 : IV74
bits : 21 - 21 (1 bit)
access : read-write
IV73 : IV73
bits : 22 - 22 (1 bit)
access : read-write
IV72 : IV72
bits : 23 - 23 (1 bit)
access : read-write
IV71 : IV71
bits : 24 - 24 (1 bit)
access : read-write
IV70 : IV70
bits : 25 - 25 (1 bit)
access : read-write
IV69 : IV69
bits : 26 - 26 (1 bit)
access : read-write
IV68 : IV68
bits : 27 - 27 (1 bit)
access : read-write
IV67 : IV67
bits : 28 - 28 (1 bit)
access : read-write
IV66 : IV66
bits : 29 - 29 (1 bit)
access : read-write
IV65 : IV65
bits : 30 - 30 (1 bit)
access : read-write
IV64 : IV64
bits : 31 - 31 (1 bit)
access : read-write
Refer to Section23.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details.
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IV127 : IV127
bits : 0 - 0 (1 bit)
access : read-write
IV126 : IV126
bits : 1 - 1 (1 bit)
access : read-write
IV125 : IV125
bits : 2 - 2 (1 bit)
access : read-write
IV124 : IV124
bits : 3 - 3 (1 bit)
access : read-write
IV123 : IV123
bits : 4 - 4 (1 bit)
access : read-write
IV122 : IV122
bits : 5 - 5 (1 bit)
access : read-write
IV121 : IV121
bits : 6 - 6 (1 bit)
access : read-write
IV120 : IV120
bits : 7 - 7 (1 bit)
access : read-write
IV119 : IV119
bits : 8 - 8 (1 bit)
access : read-write
IV118 : IV118
bits : 9 - 9 (1 bit)
access : read-write
IV117 : IV117
bits : 10 - 10 (1 bit)
access : read-write
IV116 : IV116
bits : 11 - 11 (1 bit)
access : read-write
IV115 : IV115
bits : 12 - 12 (1 bit)
access : read-write
IV114 : IV114
bits : 13 - 13 (1 bit)
access : read-write
IV113 : IV113
bits : 14 - 14 (1 bit)
access : read-write
IV112 : IV112
bits : 15 - 15 (1 bit)
access : read-write
IV111 : IV111
bits : 16 - 16 (1 bit)
access : read-write
IV110 : IV110
bits : 17 - 17 (1 bit)
access : read-write
IV109 : IV109
bits : 18 - 18 (1 bit)
access : read-write
IV108 : IV108
bits : 19 - 19 (1 bit)
access : read-write
IV107 : IV107
bits : 20 - 20 (1 bit)
access : read-write
IV106 : IV106
bits : 21 - 21 (1 bit)
access : read-write
IV105 : IV105
bits : 22 - 22 (1 bit)
access : read-write
IV104 : IV104
bits : 23 - 23 (1 bit)
access : read-write
IV103 : IV103
bits : 24 - 24 (1 bit)
access : read-write
IV102 : IV102
bits : 25 - 25 (1 bit)
access : read-write
IV101 : IV101
bits : 26 - 26 (1 bit)
access : read-write
IV100 : IV100
bits : 27 - 27 (1 bit)
access : read-write
IV99 : IV99
bits : 28 - 28 (1 bit)
access : read-write
IV98 : IV98
bits : 29 - 29 (1 bit)
access : read-write
IV97 : IV97
bits : 30 - 30 (1 bit)
access : read-write
IV96 : IV96
bits : 31 - 31 (1 bit)
access : read-write
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRYP_CSGCMCCM0R : CRYP_CSGCMCCM0R
bits : 0 - 31 (32 bit)
access : read-write
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRYP_CSGCMCCM1R : CRYP_CSGCMCCM1R
bits : 0 - 31 (32 bit)
access : read-write
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRYP_CSGCMCCM2R : CRYP_CSGCMCCM2R
bits : 0 - 31 (32 bit)
access : read-write
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRYP_CSGCMCCM3R : CRYP_CSGCMCCM3R
bits : 0 - 31 (32 bit)
access : read-write
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRYP_CSGCMCCM4R : CRYP_CSGCMCCM4R
bits : 0 - 31 (32 bit)
access : read-write
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRYP_CSGCMCCM5R : CRYP_CSGCMCCM5R
bits : 0 - 31 (32 bit)
access : read-write
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRYP_CSGCMCCM6R : CRYP_CSGCMCCM6R
bits : 0 - 31 (32 bit)
access : read-write
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRYP_CSGCMCCM7R : CRYP_CSGCMCCM7R
bits : 0 - 31 (32 bit)
access : read-write
Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRYP_CSGCM0R : CRYP_CSGCM0R
bits : 0 - 31 (32 bit)
access : read-write
Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRYP_CSGCM1R : CRYP_CSGCM1R
bits : 0 - 31 (32 bit)
access : read-write
Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRYP_CSGCM2R : CRYP_CSGCM2R
bits : 0 - 31 (32 bit)
access : read-write
Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRYP_CSGCM3R : CRYP_CSGCM3R
bits : 0 - 31 (32 bit)
access : read-write
The CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter into the input FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section23.3.16: CRYP data registers and data swapping for more details. When CRYP_DIN register is written to the data are pushed into the input FIFO. If CRYPEN = 1, when at least two 32-bit words in the DES/TDES mode have been pushed into the input FIFO (four words in the AES mode), and when at least two words are free in the output FIFO (four words in the AES mode), the CRYP engine starts an encrypting or decrypting process. When CRYP_DIN register is read: If CRYPEN = 0, the FIFO is popped, and then the data present in the Input FIFO are returned, from the oldest one (first reading) to the newest one (last reading). The IFEM flag must be checked before each read operation to make sure that the FIFO is not empty. if CRYPEN = 1, an undefined value is returned. After the CRYP_DIN register has been read once or several times, the FIFO must be flushed by setting the FFLUSH bit prior to processing new data.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAIN : DATAIN
bits : 0 - 31 (32 bit)
access : read-write
Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRYP_CSGCM4R : CRYP_CSGCM4R
bits : 0 - 31 (32 bit)
access : read-write
Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRYP_CSGCM5R : CRYP_CSGCM5R
bits : 0 - 31 (32 bit)
access : read-write
Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRYP_CSGCM6R : CRYP_CSGCM6R
bits : 0 - 31 (32 bit)
access : read-write
Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRYP_CSGCM7R : CRYP_CSGCM7R
bits : 0 - 31 (32 bit)
access : read-write
The CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is used to retrieve from the output FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section23.3.16: CRYP data registers and data swapping for more details. When CRYP_DOUT register is read, the last data entered into the output FIFO (pointed to by the read pointer) is returned.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATAOUT : DATAOUT
bits : 0 - 31 (32 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.