\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
EXTI rising trigger selection register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR0 : Rising trigger event configuration bit of Configurable Event input
bits : 0 - 0 (1 bit)
TR1 : Rising trigger event configuration bit of Configurable Event input
bits : 1 - 1 (1 bit)
TR2 : Rising trigger event configuration bit of Configurable Event input
bits : 2 - 2 (1 bit)
TR3 : Rising trigger event configuration bit of Configurable Event input
bits : 3 - 3 (1 bit)
TR4 : Rising trigger event configuration bit of Configurable Event input
bits : 4 - 4 (1 bit)
TR5 : Rising trigger event configuration bit of Configurable Event input
bits : 5 - 5 (1 bit)
TR6 : Rising trigger event configuration bit of Configurable Event input
bits : 6 - 6 (1 bit)
TR7 : Rising trigger event configuration bit of Configurable Event input
bits : 7 - 7 (1 bit)
TR8 : Rising trigger event configuration bit of Configurable Event input
bits : 8 - 8 (1 bit)
TR9 : Rising trigger event configuration bit of Configurable Event input
bits : 9 - 9 (1 bit)
TR10 : Rising trigger event configuration bit of Configurable Event input
bits : 10 - 10 (1 bit)
TR11 : Rising trigger event configuration bit of Configurable Event input
bits : 11 - 11 (1 bit)
TR12 : Rising trigger event configuration bit of Configurable Event input
bits : 12 - 12 (1 bit)
TR13 : Rising trigger event configuration bit of Configurable Event input
bits : 13 - 13 (1 bit)
TR14 : Rising trigger event configuration bit of Configurable Event input
bits : 14 - 14 (1 bit)
TR15 : Rising trigger event configuration bit of Configurable Event input
bits : 15 - 15 (1 bit)
TR16 : Rising trigger event configuration bit of Configurable Event input
bits : 16 - 16 (1 bit)
EXTI falling edge pending register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPIF0 : configurable event inputs x falling edge pending bit.
bits : 0 - 0 (1 bit)
FPIF1 : configurable event inputs x falling edge pending bit.
bits : 1 - 1 (1 bit)
FPIF2 : configurable event inputs x falling edge pending bit.
bits : 2 - 2 (1 bit)
FPIF3 : configurable event inputs x falling edge pending bit.
bits : 3 - 3 (1 bit)
FPIF4 : configurable event inputs x falling edge pending bit.
bits : 4 - 4 (1 bit)
FPIF5 : configurable event inputs x falling edge pending bit.
bits : 5 - 5 (1 bit)
FPIF6 : configurable event inputs x falling edge pending bit.
bits : 6 - 6 (1 bit)
FPIF7 : configurable event inputs x falling edge pending bit.
bits : 7 - 7 (1 bit)
FPIF8 : configurable event inputs x falling edge pending bit.
bits : 8 - 8 (1 bit)
FPIF9 : configurable event inputs x falling edge pending bit.
bits : 9 - 9 (1 bit)
FPIF10 : configurable event inputs x falling edge pending bit.
bits : 10 - 10 (1 bit)
FPIF11 : configurable event inputs x falling edge pending bit.
bits : 11 - 11 (1 bit)
FPIF12 : configurable event inputs x falling edge pending bit.
bits : 12 - 12 (1 bit)
FPIF13 : configurable event inputs x falling edge pending bit.
bits : 13 - 13 (1 bit)
FPIF14 : configurable event inputs x falling edge pending bit.
bits : 14 - 14 (1 bit)
FPIF15 : configurable event inputs x falling edge pending bit.
bits : 15 - 15 (1 bit)
FPIF16 : configurable event inputs x falling edge pending bit.
bits : 16 - 16 (1 bit)
EXTI TrustZone enable register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TZEN0 : TZEN
bits : 0 - 0 (1 bit)
TZEN1 : TZEN
bits : 1 - 1 (1 bit)
TZEN2 : TZEN
bits : 2 - 2 (1 bit)
TZEN3 : TZEN
bits : 3 - 3 (1 bit)
TZEN4 : TZEN
bits : 4 - 4 (1 bit)
TZEN5 : TZEN
bits : 5 - 5 (1 bit)
TZEN6 : TZEN
bits : 6 - 6 (1 bit)
TZEN7 : TZEN
bits : 7 - 7 (1 bit)
TZEN8 : TZEN
bits : 8 - 8 (1 bit)
TZEN9 : TZEN
bits : 9 - 9 (1 bit)
TZEN10 : TZEN
bits : 10 - 10 (1 bit)
TZEN11 : TZEN
bits : 11 - 11 (1 bit)
TZEN12 : TZEN
bits : 12 - 12 (1 bit)
TZEN13 : TZEN
bits : 13 - 13 (1 bit)
TZEN14 : TZEN
bits : 14 - 14 (1 bit)
TZEN15 : TZEN
bits : 15 - 15 (1 bit)
TZEN17 : TZEN
bits : 17 - 17 (1 bit)
TZEN18 : TZEN
bits : 18 - 18 (1 bit)
TZEN19 : TZEN
bits : 19 - 19 (1 bit)
TZEN24 : TZEN
bits : 24 - 24 (1 bit)
TZEN26 : TZEN
bits : 26 - 26 (1 bit)
EXTI TrustZone enable register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TZEN41 : TZEN
bits : 9 - 9 (1 bit)
TZEN54 : TZEN
bits : 22 - 22 (1 bit)
TZEN55 : TZEN
bits : 23 - 23 (1 bit)
TZEN56 : TZEN
bits : 24 - 24 (1 bit)
TZEN57 : TZEN
bits : 25 - 25 (1 bit)
TZEN58 : TZEN
bits : 26 - 26 (1 bit)
TZEN59 : TZEN
bits : 27 - 27 (1 bit)
TZEN60 : TZEN
bits : 28 - 28 (1 bit)
Hardware configuration registers
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TZ : TZ
bits : 0 - 31 (32 bit)
Hardware configuration registers
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TZ : TZ
bits : 0 - 31 (32 bit)
Hardware configuration registers
address_offset : 0x3C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TZ : TZ
bits : 0 - 31 (32 bit)
Hardware configuration registers
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPUEVENT : HW configuration CPU event generation
bits : 0 - 31 (32 bit)
Hardware configuration registers
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPUEVENT : HW configuration CPU event generation
bits : 0 - 31 (32 bit)
Hardware configuration registers
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPUEVENT : HW configuration CPU event generation
bits : 0 - 31 (32 bit)
Hardware configuration registers
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVENT_TRG : HW configuration event trigger type
bits : 0 - 31 (32 bit)
Hardware configuration registers
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVENT_TRG : HW configuration event trigger type
bits : 0 - 31 (32 bit)
Hardware configuration registers
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVENT_TRG : HW configuration event trigger type
bits : 0 - 31 (32 bit)
Hardware configuration registers
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NBEVENTS : configuration number of event
bits : 0 - 7 (8 bit)
NBCPUS : configuration number of CPUs
bits : 8 - 11 (4 bit)
CPUEVTEN : HW configuration of CPU event output enable
bits : 12 - 15 (4 bit)
NBIOPORT : HW configuration of number of IO ports
bits : 16 - 23 (8 bit)
AES version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINREV : Minor revision
bits : 0 - 3 (4 bit)
MAJREV : Major revision
bits : 4 - 7 (4 bit)
AES identification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : Identification code
bits : 0 - 31 (32 bit)
AES size ID register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : Size Identification code
bits : 0 - 31 (32 bit)
EXTI falling trigger selection register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR0 : Rising trigger event configuration bit of Configurable Event input
bits : 0 - 0 (1 bit)
TR1 : Rising trigger event configuration bit of Configurable Event input
bits : 1 - 1 (1 bit)
TR2 : Rising trigger event configuration bit of Configurable Event input
bits : 2 - 2 (1 bit)
TR3 : Rising trigger event configuration bit of Configurable Event input
bits : 3 - 3 (1 bit)
TR4 : Rising trigger event configuration bit of Configurable Event input
bits : 4 - 4 (1 bit)
TR5 : Rising trigger event configuration bit of Configurable Event input
bits : 5 - 5 (1 bit)
TR6 : Rising trigger event configuration bit of Configurable Event input
bits : 6 - 6 (1 bit)
TR7 : Rising trigger event configuration bit of Configurable Event input
bits : 7 - 7 (1 bit)
TR8 : Rising trigger event configuration bit of Configurable Event input
bits : 8 - 8 (1 bit)
TR9 : Rising trigger event configuration bit of Configurable Event input
bits : 9 - 9 (1 bit)
TR10 : Rising trigger event configuration bit of Configurable Event input
bits : 10 - 10 (1 bit)
TR11 : Rising trigger event configuration bit of Configurable Event input
bits : 11 - 11 (1 bit)
TR12 : Rising trigger event configuration bit of Configurable Event input
bits : 12 - 12 (1 bit)
TR13 : Rising trigger event configuration bit of Configurable Event input
bits : 13 - 13 (1 bit)
TR14 : Rising trigger event configuration bit of Configurable Event input
bits : 14 - 14 (1 bit)
TR15 : Rising trigger event configuration bit of Configurable Event input
bits : 15 - 15 (1 bit)
TR16 : Rising trigger event configuration bit of Configurable Event input
bits : 16 - 16 (1 bit)
EXTI rising trigger selection register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RT65 : RT
bits : 1 - 1 (1 bit)
RT66 : RT
bits : 2 - 2 (1 bit)
RT68 : RT
bits : 4 - 4 (1 bit)
RT73 : RT
bits : 9 - 9 (1 bit)
RT74 : RT
bits : 10 - 10 (1 bit)
EXTI falling trigger selection register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FT65 : FT
bits : 1 - 1 (1 bit)
FT66 : FT
bits : 2 - 2 (1 bit)
FT68 : FT
bits : 4 - 4 (1 bit)
FT73 : FT
bits : 9 - 9 (1 bit)
FT74 : FT
bits : 10 - 10 (1 bit)
EXTI software interrupt event register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW65 : SW
bits : 1 - 1 (1 bit)
SW66 : SW
bits : 2 - 2 (1 bit)
SW68 : SW
bits : 4 - 4 (1 bit)
SW73 : SW
bits : 9 - 9 (1 bit)
SW74 : SW
bits : 10 - 10 (1 bit)
EXTI rising edge pending register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RPIF65 : RPIF
bits : 1 - 1 (1 bit)
RPIF66 : RPIF
bits : 2 - 2 (1 bit)
RPIF68 : RPIF
bits : 4 - 4 (1 bit)
RPIF73 : RPIF
bits : 9 - 9 (1 bit)
RPIF74 : RPIF
bits : 10 - 10 (1 bit)
EXTI falling edge pending register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPIF65 : FPIF
bits : 1 - 1 (1 bit)
FPIF66 : FPIF
bits : 2 - 2 (1 bit)
FPIF68 : FPIF
bits : 4 - 4 (1 bit)
FPIF73 : FPIF
bits : 9 - 9 (1 bit)
FPIF74 : FPIF
bits : 10 - 10 (1 bit)
EXTI external interrupt selection register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTI0_7 : GPIO port selection
bits : 0 - 7 (8 bit)
EXTI8_15 : GPIO port selection
bits : 8 - 15 (8 bit)
EXTI16_23 : GPIO port selection
bits : 16 - 23 (8 bit)
EXTI24_31 : GPIO port selection
bits : 24 - 31 (8 bit)
EXTI external interrupt selection register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTI0_7 : GPIO port selection
bits : 0 - 7 (8 bit)
EXTI8_15 : GPIO port selection
bits : 8 - 15 (8 bit)
EXTI16_23 : GPIO port selection
bits : 16 - 23 (8 bit)
EXTI24_31 : GPIO port selection
bits : 24 - 31 (8 bit)
EXTI external interrupt selection register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTI0_7 : GPIO port selection
bits : 0 - 7 (8 bit)
EXTI8_15 : GPIO port selection
bits : 8 - 15 (8 bit)
EXTI16_23 : GPIO port selection
bits : 16 - 23 (8 bit)
EXTI24_31 : GPIO port selection
bits : 24 - 31 (8 bit)
EXTI external interrupt selection register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTI0_7 : GPIO port selection
bits : 0 - 7 (8 bit)
EXTI8_15 : GPIO port selection
bits : 8 - 15 (8 bit)
EXTI16_23 : GPIO port selection
bits : 16 - 23 (8 bit)
EXTI24_31 : GPIO port selection
bits : 24 - 31 (8 bit)
EXTI software interrupt event register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWIER0 : Rising trigger event configuration bit of Configurable Event input
bits : 0 - 0 (1 bit)
SWIER1 : Rising trigger event configuration bit of Configurable Event input
bits : 1 - 1 (1 bit)
SWIER2 : Rising trigger event configuration bit of Configurable Event input
bits : 2 - 2 (1 bit)
SWIER3 : Rising trigger event configuration bit of Configurable Event input
bits : 3 - 3 (1 bit)
SWIER4 : Rising trigger event configuration bit of Configurable Event input
bits : 4 - 4 (1 bit)
SWIER5 : Rising trigger event configuration bit of Configurable Event input
bits : 5 - 5 (1 bit)
SWIER6 : Rising trigger event configuration bit of Configurable Event input
bits : 6 - 6 (1 bit)
SWIER7 : Rising trigger event configuration bit of Configurable Event input
bits : 7 - 7 (1 bit)
SWIER8 : Rising trigger event configuration bit of Configurable Event input
bits : 8 - 8 (1 bit)
SWIER9 : Rising trigger event configuration bit of Configurable Event input
bits : 9 - 9 (1 bit)
SWIER10 : Rising trigger event configuration bit of Configurable Event input
bits : 10 - 10 (1 bit)
SWIER11 : Rising trigger event configuration bit of Configurable Event input
bits : 11 - 11 (1 bit)
SWIER12 : Rising trigger event configuration bit of Configurable Event input
bits : 12 - 12 (1 bit)
SWIER13 : Rising trigger event configuration bit of Configurable Event input
bits : 13 - 13 (1 bit)
SWIER14 : Rising trigger event configuration bit of Configurable Event input
bits : 14 - 14 (1 bit)
SWIER15 : Rising trigger event configuration bit of Configurable Event input
bits : 15 - 15 (1 bit)
SWIER16 : Rising trigger event configuration bit of Configurable Event input
bits : 16 - 16 (1 bit)
EXTI CPU wakeup with interrupt mask register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM0 : CPU wakeup with interrupt mask on event input
bits : 0 - 0 (1 bit)
IM1 : CPU wakeup with interrupt mask on event input
bits : 1 - 1 (1 bit)
IM2 : CPU wakeup with interrupt mask on event input
bits : 2 - 2 (1 bit)
IM3 : CPU wakeup with interrupt mask on event input
bits : 3 - 3 (1 bit)
IM4 : CPU wakeup with interrupt mask on event input
bits : 4 - 4 (1 bit)
IM5 : CPU wakeup with interrupt mask on event input
bits : 5 - 5 (1 bit)
IM6 : CPU wakeup with interrupt mask on event input
bits : 6 - 6 (1 bit)
IM7 : CPU wakeup with interrupt mask on event input
bits : 7 - 7 (1 bit)
IM8 : CPU wakeup with interrupt mask on event input
bits : 8 - 8 (1 bit)
IM9 : CPU wakeup with interrupt mask on event input
bits : 9 - 9 (1 bit)
IM10 : CPU wakeup with interrupt mask on event input
bits : 10 - 10 (1 bit)
IM11 : CPU wakeup with interrupt mask on event input
bits : 11 - 11 (1 bit)
IM12 : CPU wakeup with interrupt mask on event input
bits : 12 - 12 (1 bit)
IM13 : CPU wakeup with interrupt mask on event input
bits : 13 - 13 (1 bit)
IM14 : CPU wakeup with interrupt mask on event input
bits : 14 - 14 (1 bit)
IM15 : CPU wakeup with interrupt mask on event input
bits : 15 - 15 (1 bit)
IM16 : CPU wakeup with interrupt mask on event input
bits : 16 - 16 (1 bit)
IM17 : CPU wakeup with interrupt mask on event input
bits : 17 - 17 (1 bit)
IM18 : CPU wakeup with interrupt mask on event input
bits : 18 - 18 (1 bit)
IM19 : CPU wakeup with interrupt mask on event input
bits : 19 - 19 (1 bit)
IM20 : CPU wakeup with interrupt mask on event input
bits : 20 - 20 (1 bit)
IM21 : CPU wakeup with interrupt mask on event input
bits : 21 - 21 (1 bit)
IM22 : CPU wakeup with interrupt mask on event input
bits : 22 - 22 (1 bit)
IM23 : CPU wakeup with interrupt mask on event input
bits : 23 - 23 (1 bit)
IM24 : CPU wakeup with interrupt mask on event input
bits : 24 - 24 (1 bit)
IM25 : CPU wakeup with interrupt mask on event input
bits : 25 - 25 (1 bit)
IM26 : CPU wakeup with interrupt mask on event input
bits : 26 - 26 (1 bit)
IM27 : CPU wakeup with interrupt mask on event input
bits : 27 - 27 (1 bit)
IM28 : CPU wakeup with interrupt mask on event input
bits : 28 - 28 (1 bit)
IM29 : CPU wakeup with interrupt mask on event input
bits : 29 - 29 (1 bit)
IM30 : CPU wakeup with interrupt mask on event input
bits : 30 - 30 (1 bit)
IM31 : CPU wakeup with interrupt mask on event input
bits : 31 - 31 (1 bit)
EXTI CPUm wakeup with event mask register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM0 : CPU wakeup with interrupt mask on event input
bits : 0 - 0 (1 bit)
EM1 : CPU wakeup with interrupt mask on event input
bits : 1 - 1 (1 bit)
EM2 : CPU wakeup with interrupt mask on event input
bits : 2 - 2 (1 bit)
EM3 : CPU wakeup with interrupt mask on event input
bits : 3 - 3 (1 bit)
EM4 : CPU wakeup with interrupt mask on event input
bits : 4 - 4 (1 bit)
EM5 : CPU wakeup with interrupt mask on event input
bits : 5 - 5 (1 bit)
EM6 : CPU wakeup with interrupt mask on event input
bits : 6 - 6 (1 bit)
EM7 : CPU wakeup with interrupt mask on event input
bits : 7 - 7 (1 bit)
EM8 : CPU wakeup with interrupt mask on event input
bits : 8 - 8 (1 bit)
EM9 : CPU wakeup with interrupt mask on event input
bits : 9 - 9 (1 bit)
EM10 : CPU wakeup with interrupt mask on event input
bits : 10 - 10 (1 bit)
EM11 : CPU wakeup with interrupt mask on event input
bits : 11 - 11 (1 bit)
EM12 : CPU wakeup with interrupt mask on event input
bits : 12 - 12 (1 bit)
EM13 : CPU wakeup with interrupt mask on event input
bits : 13 - 13 (1 bit)
EM14 : CPU wakeup with interrupt mask on event input
bits : 14 - 14 (1 bit)
EM15 : CPU wakeup with interrupt mask on event input
bits : 15 - 15 (1 bit)
EM17 : CPU wakeup with interrupt mask on event input
bits : 17 - 17 (1 bit)
EM18 : CPU wakeup with interrupt mask on event input
bits : 18 - 18 (1 bit)
EM19 : CPU wakeup with interrupt mask on event input
bits : 19 - 19 (1 bit)
EXTI CPUm wakeup with interrupt mask register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM32 : CPU wakeup with interrupt mask on event input
bits : 0 - 0 (1 bit)
IM33 : CPU wakeup with interrupt mask on event input
bits : 1 - 1 (1 bit)
IM34 : CPU wakeup with interrupt mask on event input
bits : 2 - 2 (1 bit)
IM35 : CPU wakeup with interrupt mask on event input
bits : 3 - 3 (1 bit)
IM36 : CPU wakeup with interrupt mask on event input
bits : 4 - 4 (1 bit)
IM37 : CPU wakeup with interrupt mask on event input
bits : 5 - 5 (1 bit)
IM38 : CPU wakeup with interrupt mask on event input
bits : 6 - 6 (1 bit)
IM39 : CPU wakeup with interrupt mask on event input
bits : 7 - 7 (1 bit)
IM40 : CPU wakeup with interrupt mask on event input
bits : 8 - 8 (1 bit)
IM41 : CPU wakeup with interrupt mask on event input
bits : 9 - 9 (1 bit)
IM42 : CPU wakeup with interrupt mask on event input
bits : 10 - 10 (1 bit)
IM43 : CPU wakeup with interrupt mask on event input
bits : 11 - 11 (1 bit)
IM44 : CPU wakeup with interrupt mask on event input
bits : 12 - 12 (1 bit)
IM45 : CPU wakeup with interrupt mask on event input
bits : 13 - 13 (1 bit)
IM46 : CPU wakeup with interrupt mask on event input
bits : 14 - 14 (1 bit)
IM47 : CPU wakeup with interrupt mask on event input
bits : 15 - 15 (1 bit)
IM48 : CPU wakeup with interrupt mask on event input
bits : 16 - 16 (1 bit)
IM49 : CPU wakeup with interrupt mask on event input
bits : 17 - 17 (1 bit)
IM50 : CPU wakeup with interrupt mask on event input
bits : 18 - 18 (1 bit)
IM51 : CPU wakeup with interrupt mask on event input
bits : 19 - 19 (1 bit)
IM52 : CPU wakeup with interrupt mask on event input
bits : 20 - 20 (1 bit)
IM53 : CPU wakeup with interrupt mask on event input
bits : 21 - 21 (1 bit)
IM54 : CPU wakeup with interrupt mask on event input
bits : 22 - 22 (1 bit)
IM55 : CPU wakeup with interrupt mask on event input
bits : 23 - 23 (1 bit)
IM56 : CPU wakeup with interrupt mask on event input
bits : 24 - 24 (1 bit)
IM57 : CPU wakeup with interrupt mask on event input
bits : 25 - 25 (1 bit)
IM58 : CPU wakeup with interrupt mask on event input
bits : 26 - 26 (1 bit)
IM59 : CPU wakeup with interrupt mask on event input
bits : 27 - 27 (1 bit)
IM60 : CPU wakeup with interrupt mask on event input
bits : 28 - 28 (1 bit)
IM61 : CPU wakeup with interrupt mask on event input
bits : 29 - 29 (1 bit)
IM62 : CPU wakeup with interrupt mask on event input
bits : 30 - 30 (1 bit)
IM63 : CPU wakeup with interrupt mask on event input
bits : 31 - 31 (1 bit)
EXTI CPUm wakeup with interrupt mask register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM64 : CPU wakeup with interrupt mask on event input
bits : 0 - 0 (1 bit)
IM65 : CPU wakeup with interrupt mask on event input
bits : 1 - 1 (1 bit)
IM66 : CPU wakeup with interrupt mask on event input
bits : 2 - 2 (1 bit)
IM67 : CPU wakeup with interrupt mask on event input
bits : 3 - 3 (1 bit)
IM68 : CPU wakeup with interrupt mask on event input
bits : 4 - 4 (1 bit)
IM69 : CPU wakeup with interrupt mask on event input
bits : 5 - 5 (1 bit)
IM70 : CPU wakeup with interrupt mask on event input
bits : 6 - 6 (1 bit)
IM71 : CPU wakeup with interrupt mask on event input
bits : 7 - 7 (1 bit)
IM72 : CPU wakeup with interrupt mask on event input
bits : 8 - 8 (1 bit)
IM73 : CPU wakeup with interrupt mask on event input
bits : 9 - 9 (1 bit)
IM74 : CPU wakeup with interrupt mask on event input
bits : 10 - 10 (1 bit)
IM75 : CPU wakeup with interrupt mask on event input
bits : 11 - 11 (1 bit)
EXTI CPUm wakeup with event mask register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM66 : CPU wakeup with interrupt mask on event input
bits : 2 - 2 (1 bit)
EXTI rising edge pending register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RPIF0 : configurable event inputs x rising edge Pending bit.
bits : 0 - 0 (1 bit)
RPIF1 : configurable event inputs x rising edge Pending bit.
bits : 1 - 1 (1 bit)
RPIF2 : configurable event inputs x rising edge Pending bit.
bits : 2 - 2 (1 bit)
RPIF3 : configurable event inputs x rising edge Pending bit.
bits : 3 - 3 (1 bit)
RPIF4 : configurable event inputs x rising edge Pending bit.
bits : 4 - 4 (1 bit)
RPIF5 : configurable event inputs x rising edge Pending bit
bits : 5 - 5 (1 bit)
RPIF6 : configurable event inputs x rising edge Pending bit.
bits : 6 - 6 (1 bit)
RPIF7 : configurable event inputs x rising edge Pending bit.
bits : 7 - 7 (1 bit)
RPIF8 : configurable event inputs x rising edge Pending bit.
bits : 8 - 8 (1 bit)
RPIF9 : configurable event inputs x rising edge Pending bit.
bits : 9 - 9 (1 bit)
RPIF10 : configurable event inputs x rising edge Pending bit.
bits : 10 - 10 (1 bit)
RPIF11 : configurable event inputs x rising edge Pending bit.
bits : 11 - 11 (1 bit)
RPIF12 : configurable event inputs x rising edge Pending bit.
bits : 12 - 12 (1 bit)
RPIF13 : configurable event inputs x rising edge Pending bit.
bits : 13 - 13 (1 bit)
RPIF14 : configurable event inputs x rising edge Pending bit.
bits : 14 - 14 (1 bit)
RPIF15 : configurable event inputs x rising edge Pending bit.
bits : 15 - 15 (1 bit)
RPIF16 : configurable event inputs x rising edge Pending bit.
bits : 16 - 16 (1 bit)
EXTI CPU wakeup with event mask register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM0 : CPU wakeup with interrupt mask on event input
bits : 0 - 0 (1 bit)
IM1 : CPU wakeup with interrupt mask on event input
bits : 1 - 1 (1 bit)
IM2 : CPU wakeup with interrupt mask on event input
bits : 2 - 2 (1 bit)
IM3 : CPU wakeup with interrupt mask on event input
bits : 3 - 3 (1 bit)
IM4 : CPU wakeup with interrupt mask on event input
bits : 4 - 4 (1 bit)
IM5 : CPU wakeup with interrupt mask on event input
bits : 5 - 5 (1 bit)
IM6 : CPU wakeup with interrupt mask on event input
bits : 6 - 6 (1 bit)
IM7 : CPU wakeup with interrupt mask on event input
bits : 7 - 7 (1 bit)
IM8 : CPU wakeup with interrupt mask on event input
bits : 8 - 8 (1 bit)
IM9 : CPU wakeup with interrupt mask on event input
bits : 9 - 9 (1 bit)
IM10 : CPU wakeup with interrupt mask on event input
bits : 10 - 10 (1 bit)
IM11 : CPU wakeup with interrupt mask on event input
bits : 11 - 11 (1 bit)
IM12 : CPU wakeup with interrupt mask on event input
bits : 12 - 12 (1 bit)
IM13 : CPU wakeup with interrupt mask on event input
bits : 13 - 13 (1 bit)
IM14 : CPU wakeup with interrupt mask on event input
bits : 14 - 14 (1 bit)
IM15 : CPU wakeup with interrupt mask on event input
bits : 15 - 15 (1 bit)
IM16 : CPU wakeup with interrupt mask on event input
bits : 16 - 16 (1 bit)
IM17 : CPU wakeup with interrupt mask on event input
bits : 17 - 17 (1 bit)
IM18 : CPU wakeup with interrupt mask on event input
bits : 18 - 18 (1 bit)
IM19 : CPU wakeup with interrupt mask on event input
bits : 19 - 19 (1 bit)
IM20 : CPU wakeup with interrupt mask on event input
bits : 20 - 20 (1 bit)
IM21 : CPU wakeup with interrupt mask on event input
bits : 21 - 21 (1 bit)
IM22 : CPU wakeup with interrupt mask on event input
bits : 22 - 22 (1 bit)
IM23 : CPU wakeup with interrupt mask on event input
bits : 23 - 23 (1 bit)
IM24 : CPU wakeup with interrupt mask on event input
bits : 24 - 24 (1 bit)
IM25 : CPU wakeup with interrupt mask on event input
bits : 25 - 25 (1 bit)
IM26 : CPU wakeup with interrupt mask on event input
bits : 26 - 26 (1 bit)
IM27 : CPU wakeup with interrupt mask on event input
bits : 27 - 27 (1 bit)
IM28 : CPU wakeup with interrupt mask on event input
bits : 28 - 28 (1 bit)
IM29 : CPU wakeup with interrupt mask on event input
bits : 29 - 29 (1 bit)
IM30 : CPU wakeup with interrupt mask on event input
bits : 30 - 30 (1 bit)
IM31 : CPU wakeup with interrupt mask on event input
bits : 31 - 31 (1 bit)
EXTI CPUm wakeup with event mask register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM0 : CPU wakeup with interrupt mask on event input
bits : 0 - 0 (1 bit)
EM1 : CPU wakeup with interrupt mask on event input
bits : 1 - 1 (1 bit)
EM2 : CPU wakeup with interrupt mask on event input
bits : 2 - 2 (1 bit)
EM3 : CPU wakeup with interrupt mask on event input
bits : 3 - 3 (1 bit)
EM4 : CPU wakeup with interrupt mask on event input
bits : 4 - 4 (1 bit)
EM5 : CPU wakeup with interrupt mask on event input
bits : 5 - 5 (1 bit)
EM6 : CPU wakeup with interrupt mask on event input
bits : 6 - 6 (1 bit)
EM7 : CPU wakeup with interrupt mask on event input
bits : 7 - 7 (1 bit)
EM8 : CPU wakeup with interrupt mask on event input
bits : 8 - 8 (1 bit)
EM9 : CPU wakeup with interrupt mask on event input
bits : 9 - 9 (1 bit)
EM10 : CPU wakeup with interrupt mask on event input
bits : 10 - 10 (1 bit)
EM11 : CPU wakeup with interrupt mask on event input
bits : 11 - 11 (1 bit)
EM12 : CPU wakeup with interrupt mask on event input
bits : 12 - 12 (1 bit)
EM13 : CPU wakeup with interrupt mask on event input
bits : 13 - 13 (1 bit)
EM14 : CPU wakeup with interrupt mask on event input
bits : 14 - 14 (1 bit)
EM15 : CPU wakeup with interrupt mask on event input
bits : 15 - 15 (1 bit)
EM17 : CPU wakeup with interrupt mask on event input
bits : 17 - 17 (1 bit)
EM18 : CPU wakeup with interrupt mask on event input
bits : 18 - 18 (1 bit)
EM19 : CPU wakeup with interrupt mask on event input
bits : 19 - 19 (1 bit)
EXTI CPUm wakeup with interrupt mask register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM32 : CPU wakeup with interrupt mask on event input
bits : 0 - 0 (1 bit)
IM33 : CPU wakeup with interrupt mask on event input
bits : 1 - 1 (1 bit)
IM34 : CPU wakeup with interrupt mask on event input
bits : 2 - 2 (1 bit)
IM35 : CPU wakeup with interrupt mask on event input
bits : 3 - 3 (1 bit)
IM36 : CPU wakeup with interrupt mask on event input
bits : 4 - 4 (1 bit)
IM37 : CPU wakeup with interrupt mask on event input
bits : 5 - 5 (1 bit)
IM38 : CPU wakeup with interrupt mask on event input
bits : 6 - 6 (1 bit)
IM39 : CPU wakeup with interrupt mask on event input
bits : 7 - 7 (1 bit)
IM40 : CPU wakeup with interrupt mask on event input
bits : 8 - 8 (1 bit)
IM41 : CPU wakeup with interrupt mask on event input
bits : 9 - 9 (1 bit)
IM42 : CPU wakeup with interrupt mask on event input
bits : 10 - 10 (1 bit)
IM43 : CPU wakeup with interrupt mask on event input
bits : 11 - 11 (1 bit)
IM44 : CPU wakeup with interrupt mask on event input
bits : 12 - 12 (1 bit)
IM45 : CPU wakeup with interrupt mask on event input
bits : 13 - 13 (1 bit)
IM46 : CPU wakeup with interrupt mask on event input
bits : 14 - 14 (1 bit)
IM47 : CPU wakeup with interrupt mask on event input
bits : 15 - 15 (1 bit)
IM48 : CPU wakeup with interrupt mask on event input
bits : 16 - 16 (1 bit)
IM49 : CPU wakeup with interrupt mask on event input
bits : 17 - 17 (1 bit)
IM50 : CPU wakeup with interrupt mask on event input
bits : 18 - 18 (1 bit)
IM51 : CPU wakeup with interrupt mask on event input
bits : 19 - 19 (1 bit)
IM52 : CPU wakeup with interrupt mask on event input
bits : 20 - 20 (1 bit)
IM53 : CPU wakeup with interrupt mask on event input
bits : 21 - 21 (1 bit)
IM54 : CPU wakeup with interrupt mask on event input
bits : 22 - 22 (1 bit)
IM55 : CPU wakeup with interrupt mask on event input
bits : 23 - 23 (1 bit)
IM56 : CPU wakeup with interrupt mask on event input
bits : 24 - 24 (1 bit)
IM57 : CPU wakeup with interrupt mask on event input
bits : 25 - 25 (1 bit)
IM58 : CPU wakeup with interrupt mask on event input
bits : 26 - 26 (1 bit)
IM59 : CPU wakeup with interrupt mask on event input
bits : 27 - 27 (1 bit)
IM60 : CPU wakeup with interrupt mask on event input
bits : 28 - 28 (1 bit)
IM61 : CPU wakeup with interrupt mask on event input
bits : 29 - 29 (1 bit)
IM62 : CPU wakeup with interrupt mask on event input
bits : 30 - 30 (1 bit)
IM63 : CPU wakeup with interrupt mask on event input
bits : 31 - 31 (1 bit)
EXTI CPUm wakeup with interrupt mask register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM64 : CPU wakeup with interrupt mask on event input
bits : 0 - 0 (1 bit)
IM65 : CPU wakeup with interrupt mask on event input
bits : 1 - 1 (1 bit)
IM66 : CPU wakeup with interrupt mask on event input
bits : 2 - 2 (1 bit)
IM67 : CPU wakeup with interrupt mask on event input
bits : 3 - 3 (1 bit)
IM68 : CPU wakeup with interrupt mask on event input
bits : 4 - 4 (1 bit)
IM69 : CPU wakeup with interrupt mask on event input
bits : 5 - 5 (1 bit)
IM70 : CPU wakeup with interrupt mask on event input
bits : 6 - 6 (1 bit)
IM71 : CPU wakeup with interrupt mask on event input
bits : 7 - 7 (1 bit)
IM72 : CPU wakeup with interrupt mask on event input
bits : 8 - 8 (1 bit)
IM73 : CPU wakeup with interrupt mask on event input
bits : 9 - 9 (1 bit)
IM74 : CPU wakeup with interrupt mask on event input
bits : 10 - 10 (1 bit)
IM75 : CPU wakeup with interrupt mask on event input
bits : 11 - 11 (1 bit)
EXTI CPUm wakeup with event mask register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM66 : CPU wakeup with interrupt mask on event input
bits : 2 - 2 (1 bit)
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