\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
TIM1/TIM8 control register 1
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : CEN
bits : 0 - 0 (1 bit)
access : read-write
UDIS : UDIS
bits : 1 - 1 (1 bit)
access : read-write
URS : URS
bits : 2 - 2 (1 bit)
access : read-write
OPM : OPM
bits : 3 - 3 (1 bit)
access : read-write
DIR : DIR
bits : 4 - 4 (1 bit)
access : read-write
CMS : CMS
bits : 5 - 6 (2 bit)
access : read-write
ARPE : ARPE
bits : 7 - 7 (1 bit)
access : read-write
CKD : CKD
bits : 8 - 9 (2 bit)
access : read-write
UIFREMAP : UIFREMAP
bits : 11 - 11 (1 bit)
access : read-write
TIM1/TIM8 status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIF : UIF
bits : 0 - 0 (1 bit)
access : read-write
CC1IF : CC1IF
bits : 1 - 1 (1 bit)
access : read-write
CC2IF : CC2IF
bits : 2 - 2 (1 bit)
access : read-write
CC3IF : CC3IF
bits : 3 - 3 (1 bit)
access : read-write
CC4IF : CC4IF
bits : 4 - 4 (1 bit)
access : read-write
COMIF : COMIF
bits : 5 - 5 (1 bit)
access : read-write
TIF : TIF
bits : 6 - 6 (1 bit)
access : read-write
BIF : BIF
bits : 7 - 7 (1 bit)
access : read-write
B2IF : B2IF
bits : 8 - 8 (1 bit)
access : read-write
CC1OF : CC1OF
bits : 9 - 9 (1 bit)
access : read-write
CC2OF : CC2OF
bits : 10 - 10 (1 bit)
access : read-write
CC3OF : CC3OF
bits : 11 - 11 (1 bit)
access : read-write
CC4OF : CC4OF
bits : 12 - 12 (1 bit)
access : read-write
SBIF : SBIF
bits : 13 - 13 (1 bit)
access : read-write
CC5IF : CC5IF
bits : 16 - 16 (1 bit)
access : read-write
CC6IF : CC6IF
bits : 17 - 17 (1 bit)
access : read-write
TIM1/TIM8 event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UG : UG
bits : 0 - 0 (1 bit)
access : write-only
CC1G : CC1G
bits : 1 - 1 (1 bit)
access : write-only
CC2G : CC2G
bits : 2 - 2 (1 bit)
access : write-only
CC3G : CC3G
bits : 3 - 3 (1 bit)
access : write-only
CC4G : CC4G
bits : 4 - 4 (1 bit)
access : write-only
COMG : COMG
bits : 5 - 5 (1 bit)
access : write-only
TG : TG
bits : 6 - 6 (1 bit)
access : write-only
BG : BG
bits : 7 - 7 (1 bit)
access : write-only
B2G : B2G
bits : 8 - 8 (1 bit)
access : write-only
capture/compare mode register 1 (output mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC1S : Capture/Compare 1 selection
bits : 0 - 1 (2 bit)
OC1FE : Output Compare 1 fast enable
bits : 2 - 2 (1 bit)
OC1PE : Output Compare 1 preload enable
bits : 3 - 3 (1 bit)
OC1M : Output Compare 1 mode
bits : 4 - 6 (3 bit)
OC1CE : Output Compare 1 clear enable
bits : 7 - 7 (1 bit)
CC2S : Capture/Compare 2 selection
bits : 8 - 9 (2 bit)
OC2FE : Output Compare 2 fast enable
bits : 10 - 10 (1 bit)
OC2PE : Output Compare 2 preload enable
bits : 11 - 11 (1 bit)
OC2M : Output Compare 2 mode
bits : 12 - 14 (3 bit)
OC2CE : Output Compare 2 clear enable
bits : 15 - 15 (1 bit)
OC1M_3 : Output Compare 1 mode - bit 3
bits : 16 - 16 (1 bit)
OC2M_3 : Output Compare 2 mode - bit 3
bits : 24 - 24 (1 bit)
capture/compare mode register 1 (output mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TIMx_CCMR1_Output
reset_Mask : 0x0
CC1S : Capture/Compare 1 selection
bits : 0 - 1 (2 bit)
OC1FE : Output Compare 1 fast enable
bits : 2 - 2 (1 bit)
OC1PE : Output Compare 1 preload enable
bits : 3 - 3 (1 bit)
OC1M : Output Compare 1 mode
bits : 4 - 6 (3 bit)
OC1CE : Output Compare 1 clear enable
bits : 7 - 7 (1 bit)
CC2S : Capture/Compare 2 selection
bits : 8 - 9 (2 bit)
OC2FE : Output Compare 2 fast enable
bits : 10 - 10 (1 bit)
OC2PE : Output Compare 2 preload enable
bits : 11 - 11 (1 bit)
OC2M : Output Compare 2 mode
bits : 12 - 14 (3 bit)
OC2CE : Output Compare 2 clear enable
bits : 15 - 15 (1 bit)
capture/compare mode register 2 (output mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC3S : Capture/Compare 3 selection
bits : 0 - 1 (2 bit)
OC3FE : Output compare 3 fast enable
bits : 2 - 2 (1 bit)
OC3PE : Output compare 3 preload enable
bits : 3 - 3 (1 bit)
OC3M : Output compare 3 mode
bits : 4 - 6 (3 bit)
OC3CE : Output compare 3 clear enable
bits : 7 - 7 (1 bit)
CC4S : Capture/Compare 4 selection
bits : 8 - 9 (2 bit)
OC4FE : Output compare 4 fast enable
bits : 10 - 10 (1 bit)
OC4PE : Output compare 4 preload enable
bits : 11 - 11 (1 bit)
OC4M : Output compare 4 mode
bits : 12 - 14 (3 bit)
OC4CE : Output compare 4 clear enable
bits : 15 - 15 (1 bit)
OC3M_3 : Output Compare 3 mode - bit 3
bits : 16 - 16 (1 bit)
OC4M_3 : Output Compare 4 mode - bit 3
bits : 24 - 24 (1 bit)
capture/compare mode register 2 (output mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TIMx_CCMR2_Output
reset_Mask : 0x0
CC3S : Capture/Compare 3 selection
bits : 0 - 1 (2 bit)
OC3FE : Output compare 3 fast enable
bits : 2 - 2 (1 bit)
OC3PE : Output compare 3 preload enable
bits : 3 - 3 (1 bit)
OC3M : Output compare 3 mode
bits : 4 - 6 (3 bit)
OC3CE : Output compare 3 clear enable
bits : 7 - 7 (1 bit)
CC4S : Capture/Compare 4 selection
bits : 8 - 9 (2 bit)
OC4FE : Output compare 4 fast enable
bits : 10 - 10 (1 bit)
OC4PE : Output compare 4 preload enable
bits : 11 - 11 (1 bit)
OC4M : Output compare 4 mode
bits : 12 - 14 (3 bit)
OC4CE : Output compare 4 clear enable
bits : 15 - 15 (1 bit)
capture/compare enable register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC1E : Capture/Compare 1 output enable
bits : 0 - 0 (1 bit)
CC1P : Capture/Compare 1 output Polarity
bits : 1 - 1 (1 bit)
CC1NE : Capture/Compare 1 complementary output enable
bits : 2 - 2 (1 bit)
CC1NP : Capture/Compare 1 output Polarity
bits : 3 - 3 (1 bit)
CC2E : Capture/Compare 2 output enable
bits : 4 - 4 (1 bit)
CC2P : Capture/Compare 2 output Polarity
bits : 5 - 5 (1 bit)
CC2NE : Capture/Compare 2 complementary output enable
bits : 6 - 6 (1 bit)
CC2NP : Capture/Compare 2 output Polarity
bits : 7 - 7 (1 bit)
CC3E : Capture/Compare 3 output enable
bits : 8 - 8 (1 bit)
CC3P : Capture/Compare 3 output Polarity
bits : 9 - 9 (1 bit)
CC3NE : Capture/Compare 3 complementary output enable
bits : 10 - 10 (1 bit)
CC3NP : Capture/Compare 3 output Polarity
bits : 11 - 11 (1 bit)
CC4E : Capture/Compare 4 output enable
bits : 12 - 12 (1 bit)
CC4P : Capture/Compare 3 output Polarity
bits : 13 - 13 (1 bit)
CC4NP : Capture/Compare 4 complementary output polarity
bits : 15 - 15 (1 bit)
CC5E : Capture/Compare 5 output enable
bits : 16 - 16 (1 bit)
CC5P : Capture/Compare 5 output polarity
bits : 17 - 17 (1 bit)
CC6E : Capture/Compare 6 output enable
bits : 20 - 20 (1 bit)
CC6P : Capture/Compare 6 output polarity
bits : 21 - 21 (1 bit)
TIM1/TIM8 counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : CNT
bits : 0 - 15 (16 bit)
access : read-write
UIFCPY : UIFCPY
bits : 31 - 31 (1 bit)
access : read-only
TIM1/TIM8 prescaler
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : PSC
bits : 0 - 15 (16 bit)
access : read-write
TIM1/TIM8 auto-reload register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARR : ARR
bits : 0 - 15 (16 bit)
access : read-write
TIM1/TIM8 repetition counter register
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REP : REP
bits : 0 - 15 (16 bit)
access : read-write
TIM1/TIM8 capture/compare register 1
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR1 : CCR1
bits : 0 - 15 (16 bit)
access : read-write
TIM1/TIM8 capture/compare register 2
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR2 : CCR2
bits : 0 - 15 (16 bit)
access : read-write
TIM1/TIM8 capture/compare register 3
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR3 : CCR3
bits : 0 - 15 (16 bit)
access : read-write
TIM1/TIM8 control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCPC : CCPC
bits : 0 - 0 (1 bit)
access : read-write
CCUS : CCUS
bits : 2 - 2 (1 bit)
access : read-write
CCDS : CCDS
bits : 3 - 3 (1 bit)
access : read-write
MMS : MMS
bits : 4 - 6 (3 bit)
access : read-write
TI1S : TI1S
bits : 7 - 7 (1 bit)
access : read-write
OIS1 : OIS1
bits : 8 - 8 (1 bit)
access : read-write
OIS1N : OIS1N
bits : 9 - 9 (1 bit)
access : read-write
OIS2 : OIS2
bits : 10 - 10 (1 bit)
access : read-write
OIS2N : OIS2N
bits : 11 - 11 (1 bit)
access : read-write
OIS3 : OIS3
bits : 12 - 12 (1 bit)
access : read-write
OIS3N : OIS3N
bits : 13 - 13 (1 bit)
access : read-write
OIS4 : OIS4
bits : 14 - 14 (1 bit)
access : read-write
OIS5 : OIS5
bits : 16 - 16 (1 bit)
access : read-write
OIS6 : OIS6
bits : 18 - 18 (1 bit)
access : read-write
MMS2 : MMS2
bits : 20 - 23 (4 bit)
access : read-write
TIM1/TIM8 capture/compare register 4
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR4 : CCR4
bits : 0 - 15 (16 bit)
access : read-write
As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTG : DTG
bits : 0 - 7 (8 bit)
access : read-write
LOCK : LOCK
bits : 8 - 9 (2 bit)
access : read-write
OSSI : OSSI
bits : 10 - 10 (1 bit)
access : read-write
OSSR : OSSR
bits : 11 - 11 (1 bit)
access : read-write
BKE : BKE
bits : 12 - 12 (1 bit)
access : read-write
BKP : BKP
bits : 13 - 13 (1 bit)
access : read-write
AOE : AOE
bits : 14 - 14 (1 bit)
access : read-write
MOE : MOE
bits : 15 - 15 (1 bit)
access : read-write
BKF : BKF
bits : 16 - 19 (4 bit)
access : read-write
BK2F : BK2F
bits : 20 - 23 (4 bit)
access : read-write
BK2E : BK2E
bits : 24 - 24 (1 bit)
access : read-write
BK2P : BK2P
bits : 25 - 25 (1 bit)
access : read-write
BKDSRM : BKDSRM
bits : 26 - 26 (1 bit)
access : read-write
BK2DSRM : BK2DSRM
bits : 27 - 27 (1 bit)
access : read-write
BKBID : BKBID
bits : 28 - 28 (1 bit)
access : read-write
BK2BID : BK2BID
bits : 29 - 29 (1 bit)
access : read-write
TIM1/TIM8 DMA control register
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBA : DBA
bits : 0 - 4 (5 bit)
access : read-write
DBL : DBL
bits : 8 - 12 (5 bit)
access : read-write
DMA address for full transfer
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAB : DMA register for burst accesses
bits : 0 - 15 (16 bit)
capture/compare mode register 3 (output mode)
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OC5FE : Output compare 5 fast enable
bits : 2 - 2 (1 bit)
OC5PE : Output compare 5 preload enable
bits : 3 - 3 (1 bit)
OC5M : Output compare 5 mode
bits : 4 - 6 (3 bit)
OC5CE : Output compare 3 clear enable
bits : 7 - 7 (1 bit)
OC6FE : Output compare 6 fast enable
bits : 10 - 10 (1 bit)
OC6PE : Output compare 6 preload enable
bits : 11 - 11 (1 bit)
OC6M : Output compare 6 mode
bits : 12 - 14 (3 bit)
OC6CE : Output compare 6 clear enable
bits : 15 - 15 (1 bit)
OC5M_3 : OC5M_3
bits : 16 - 16 (1 bit)
OC6M_3 : OC6M_3
bits : 24 - 24 (1 bit)
TIM1/TIM8 capture/compare register 5
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR5 : CCR5
bits : 0 - 15 (16 bit)
access : read-write
GC5C1 : GC5C1
bits : 29 - 29 (1 bit)
access : read-write
GC5C2 : GC5C2
bits : 30 - 30 (1 bit)
access : read-write
GC5C3 : GC5C3
bits : 31 - 31 (1 bit)
access : read-write
TIM1/TIM8 capture/compare register 6
address_offset : 0x5C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR6 : CCR6
bits : 0 - 15 (16 bit)
access : read-write
DMA address for full transfer
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKINE : BRK BKIN input enable
bits : 0 - 0 (1 bit)
BKDF1BK0E : BKDF1BK0E
bits : 8 - 8 (1 bit)
BKINP : BRK BKIN input polarity
bits : 9 - 9 (1 bit)
ETRSEL : ETR source selection
bits : 14 - 17 (4 bit)
DMA address for full transfer
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BK2INE : BRK2 BKIN input enable
bits : 0 - 0 (1 bit)
BK2DFBK0E : BRK2 DFSDM_BREAK0 enable
bits : 8 - 8 (1 bit)
BK2INP : BRK2 BKIN input polarity
bits : 9 - 9 (1 bit)
TIM1 timer input selection register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TI1SEL : TI1SEL
bits : 0 - 3 (4 bit)
TI2SEL : TI2SEL
bits : 8 - 11 (4 bit)
TI3SEL : TI3SEL
bits : 16 - 19 (4 bit)
TI4SEL : TI4SEL
bits : 24 - 27 (4 bit)
TIM1/TIM8 slave mode control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMS : SMS
bits : 0 - 2 (3 bit)
access : read-write
TS : TS
bits : 4 - 6 (3 bit)
access : read-write
MSM : MSM
bits : 7 - 7 (1 bit)
access : read-write
ETF : ETF
bits : 8 - 11 (4 bit)
access : read-write
ETPS : ETPS
bits : 12 - 13 (2 bit)
access : read-write
ECE : ECE
bits : 14 - 14 (1 bit)
access : read-write
ETP : ETP
bits : 15 - 15 (1 bit)
access : read-write
SMS_3 : SMS_3
bits : 16 - 16 (1 bit)
access : read-write
TS_4_3 : TS_4_3
bits : 20 - 21 (2 bit)
access : read-write
TIM1/TIM8 DMA/interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIE : UIE
bits : 0 - 0 (1 bit)
access : read-write
CC1IE : CC1IE
bits : 1 - 1 (1 bit)
access : read-write
CC2IE : CC2IE
bits : 2 - 2 (1 bit)
access : read-write
CC3IE : CC3IE
bits : 3 - 3 (1 bit)
access : read-write
CC4IE : CC4IE
bits : 4 - 4 (1 bit)
access : read-write
COMIE : COMIE
bits : 5 - 5 (1 bit)
access : read-write
TIE : TIE
bits : 6 - 6 (1 bit)
access : read-write
BIE : BIE
bits : 7 - 7 (1 bit)
access : read-write
UDE : UDE
bits : 8 - 8 (1 bit)
access : read-write
CC1DE : CC1DE
bits : 9 - 9 (1 bit)
access : read-write
CC2DE : CC2DE
bits : 10 - 10 (1 bit)
access : read-write
CC3DE : CC3DE
bits : 11 - 11 (1 bit)
access : read-write
CC4DE : CC4DE
bits : 12 - 12 (1 bit)
access : read-write
COMDE : COMDE
bits : 13 - 13 (1 bit)
access : read-write
TDE : TDE
bits : 14 - 14 (1 bit)
access : read-write
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