\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
TIMx control register 1
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : CEN
bits : 0 - 0 (1 bit)
access : read-write
UDIS : UDIS
bits : 1 - 1 (1 bit)
access : read-write
URS : URS
bits : 2 - 2 (1 bit)
access : read-write
OPM : OPM
bits : 3 - 3 (1 bit)
access : read-write
DIR : DIR
bits : 4 - 4 (1 bit)
access : read-write
CMS : CMS
bits : 5 - 6 (2 bit)
access : read-write
ARPE : ARPE
bits : 7 - 7 (1 bit)
access : read-write
CKD : CKD
bits : 8 - 9 (2 bit)
access : read-write
UIFREMAP : UIFREMAP
bits : 11 - 11 (1 bit)
access : read-write
TIMx status register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIF : UIF
bits : 0 - 0 (1 bit)
access : read-write
CC1IF : CC1IF
bits : 1 - 1 (1 bit)
access : read-write
CC2IF : CC2IF
bits : 2 - 2 (1 bit)
access : read-write
CC3IF : CC3IF
bits : 3 - 3 (1 bit)
access : read-write
CC4IF : CC4IF
bits : 4 - 4 (1 bit)
access : read-write
TIF : TIF
bits : 6 - 6 (1 bit)
access : read-write
CC1OF : CC1OF
bits : 9 - 9 (1 bit)
access : read-write
CC2OF : CC2OF
bits : 10 - 10 (1 bit)
access : read-write
CC3OF : CC3OF
bits : 11 - 11 (1 bit)
access : read-write
CC4OF : CC4OF
bits : 12 - 12 (1 bit)
access : read-write
event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UG : Update generation
bits : 0 - 0 (1 bit)
CC1G : Capture/compare 1 generation
bits : 1 - 1 (1 bit)
CC2G : Capture/compare 2 generation
bits : 2 - 2 (1 bit)
CC3G : Capture/compare 3 generation
bits : 3 - 3 (1 bit)
CC4G : Capture/compare 4 generation
bits : 4 - 4 (1 bit)
TG : Trigger generation
bits : 6 - 6 (1 bit)
capture/compare mode register 1 (output mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC1S : Capture/Compare 1 selection
bits : 0 - 1 (2 bit)
OC1FE : Output compare 1 fast enable
bits : 2 - 2 (1 bit)
OC1PE : Output compare 1 preload enable
bits : 3 - 3 (1 bit)
OC1M : Output compare 1 mode
bits : 4 - 6 (3 bit)
OC1CE : Output compare 1 clear enable
bits : 7 - 7 (1 bit)
CC2S : Capture/Compare 2 selection
bits : 8 - 9 (2 bit)
OC2FE : Output compare 2 fast enable
bits : 10 - 10 (1 bit)
OC2PE : Output compare 2 preload enable
bits : 11 - 11 (1 bit)
OC2M : Output compare 2 mode
bits : 12 - 14 (3 bit)
OC2CE : Output compare 2 clear enable
bits : 15 - 15 (1 bit)
OC1M_3 : Output Compare 1 mode - bit 3
bits : 16 - 16 (1 bit)
OC2M_3 : Output Compare 2 mode - bit 3
bits : 24 - 24 (1 bit)
capture/compare mode register 1 (input mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TIMx_CCMR1_Output
reset_Mask : 0x0
CC1S : Capture/Compare 1 selection
bits : 0 - 1 (2 bit)
IC1PSC : Input capture 1 prescaler
bits : 2 - 3 (2 bit)
IC1F : Input capture 1 filter
bits : 4 - 7 (4 bit)
CC2S : Capture/compare 2 selection
bits : 8 - 9 (2 bit)
IC2PSC : Input capture 2 prescaler
bits : 10 - 11 (2 bit)
IC2F : Input capture 2 filter
bits : 12 - 15 (4 bit)
capture/compare mode register 2 (output mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC3S : Capture/Compare 3 selection
bits : 0 - 1 (2 bit)
OC3FE : Output compare 3 fast enable
bits : 2 - 2 (1 bit)
OC3PE : Output compare 3 preload enable
bits : 3 - 3 (1 bit)
OC3M : Output compare 3 mode
bits : 4 - 6 (3 bit)
OC3CE : Output compare 3 clear enable
bits : 7 - 7 (1 bit)
CC4S : Capture/Compare 4 selection
bits : 8 - 9 (2 bit)
OC4FE : Output compare 4 fast enable
bits : 10 - 10 (1 bit)
OC4PE : Output compare 4 preload enable
bits : 11 - 11 (1 bit)
OC4M : Output compare 4 mode
bits : 12 - 14 (3 bit)
OC4CE : Output compare 4 clear enable
bits : 15 - 15 (1 bit)
OC3M_3 : Output Compare 3 mode - bit 3
bits : 16 - 16 (1 bit)
OC4M_3 : Output Compare 4 mode - bit 3
bits : 24 - 24 (1 bit)
capture/compare mode register 2 (input mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TIMx_CCMR2_Output
reset_Mask : 0x0
CC3S : Capture/Compare 3 selection
bits : 0 - 1 (2 bit)
IC3PSC : Input capture 3 prescaler
bits : 2 - 3 (2 bit)
IC3F : Input capture 3 filter
bits : 4 - 7 (4 bit)
CC4S : Capture/Compare 4 selection
bits : 8 - 9 (2 bit)
IC4PSC : Input capture 4 prescaler
bits : 10 - 11 (2 bit)
IC4F : Input capture 4 filter
bits : 12 - 15 (4 bit)
TIMx capture/compare enable register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC1E : CC1E
bits : 0 - 0 (1 bit)
access : read-write
CC1P : CC1P
bits : 1 - 1 (1 bit)
access : read-write
CC1NP : CC1NP
bits : 3 - 3 (1 bit)
access : read-write
CC2E : CC2E
bits : 4 - 4 (1 bit)
access : read-write
CC2P : CC2P
bits : 5 - 5 (1 bit)
access : read-write
CC2NP : CC2NP
bits : 7 - 7 (1 bit)
access : read-write
CC3E : CC3E
bits : 8 - 8 (1 bit)
access : read-write
CC3P : CC3P
bits : 9 - 9 (1 bit)
access : read-write
CC3NP : CC3NP
bits : 11 - 11 (1 bit)
access : read-write
CC4E : CC4E
bits : 12 - 12 (1 bit)
access : read-write
CC4P : CC4P
bits : 13 - 13 (1 bit)
access : read-write
CC4NP : CC4NP
bits : 15 - 15 (1 bit)
access : read-write
counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_L : Low counter value
bits : 0 - 15 (16 bit)
CNT_H : High counter value (TIM2 only)
bits : 16 - 31 (16 bit)
TIMx prescaler
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : PSC
bits : 0 - 15 (16 bit)
access : read-write
auto-reload register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARR_L : Low Auto-reload value
bits : 0 - 15 (16 bit)
ARR_H : High Auto-reload value (TIM2 only)
bits : 16 - 31 (16 bit)
capture/compare register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR1_L : Low Capture/Compare 1 value
bits : 0 - 15 (16 bit)
CCR1_H : High Capture/Compare 1 value (TIM2 only)
bits : 16 - 31 (16 bit)
capture/compare register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR2_L : Low Capture/Compare 2 value
bits : 0 - 15 (16 bit)
CCR2_H : High Capture/Compare 2 value (TIM2 only)
bits : 16 - 31 (16 bit)
capture/compare register 3
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR3_L : Low Capture/Compare value
bits : 0 - 15 (16 bit)
CCR3_H : High Capture/Compare value (TIM2 only)
bits : 16 - 31 (16 bit)
TIMx control register 2
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCDS : CCDS
bits : 3 - 3 (1 bit)
access : read-write
MMS : MMS
bits : 4 - 6 (3 bit)
access : read-write
TI1S : TI1S
bits : 7 - 7 (1 bit)
access : read-write
capture/compare register 4
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR4_L : Low Capture/Compare value
bits : 0 - 15 (16 bit)
CCR4_H : High Capture/Compare value (TIM2 only)
bits : 16 - 31 (16 bit)
TIMx DMA control register
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBA : DBA
bits : 0 - 4 (5 bit)
access : read-write
DBL : DBL
bits : 8 - 12 (5 bit)
access : read-write
TIMx DMA address for full transfer
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAB : DMAB
bits : 0 - 15 (16 bit)
access : read-write
TIM alternate function option register 1
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETRSEL : External trigger source selection
bits : 14 - 17 (4 bit)
TIMx timer input selection register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TI1SEL : TI1SEL
bits : 0 - 3 (4 bit)
access : read-write
TI2SEL : TI2SEL
bits : 8 - 11 (4 bit)
access : read-write
TI3SEL : TI3SEL
bits : 16 - 19 (4 bit)
access : read-write
TI4SEL : TI4SEL
bits : 24 - 27 (4 bit)
access : read-write
slave mode control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMS : Slave mode selection
bits : 0 - 2 (3 bit)
OCCS : OCREF clear selection
bits : 3 - 3 (1 bit)
TS : Trigger selection
bits : 4 - 6 (3 bit)
MSM : Master/Slave mode
bits : 7 - 7 (1 bit)
ETF : External trigger filter
bits : 8 - 11 (4 bit)
ETPS : External trigger prescaler
bits : 12 - 13 (2 bit)
ECE : External clock enable
bits : 14 - 14 (1 bit)
ETP : External trigger polarity
bits : 15 - 15 (1 bit)
SMS_3 : Slave mode selection - bit 3
bits : 16 - 16 (1 bit)
TS_4_3 : Trigger selection
bits : 20 - 21 (2 bit)
TIMx DMA/Interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIE : UIE
bits : 0 - 0 (1 bit)
access : read-write
CC1IE : CC1IE
bits : 1 - 1 (1 bit)
access : read-write
CC2IE : CC2IE
bits : 2 - 2 (1 bit)
access : read-write
CC3IE : CC3IE
bits : 3 - 3 (1 bit)
access : read-write
CC4IE : CC4IE
bits : 4 - 4 (1 bit)
access : read-write
TIE : TIE
bits : 6 - 6 (1 bit)
access : read-write
UDE : UDE
bits : 8 - 8 (1 bit)
access : read-write
CC1DE : CC1DE
bits : 9 - 9 (1 bit)
access : read-write
CC2DE : CC2DE
bits : 10 - 10 (1 bit)
access : read-write
CC3DE : CC3DE
bits : 11 - 11 (1 bit)
access : read-write
CC4DE : CC4DE
bits : 12 - 12 (1 bit)
access : read-write
TDE : TDE
bits : 14 - 14 (1 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.