\n

UART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

UART0DR

DR

UART0FR

FR

UART0IBRD

IBRD

UART0FBRD

FBRD

UART0LCRH

LCRH

UART0CTL

CTL

UART0IFLS

IFLS

UART0IM

IM

UART0RIS

RIS

UART0RSR

UART0ECR

RSR

ECR

UART0MIS

MIS

UART0ICR

ICR


UART0DR

UART Data
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART0DR UART0DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_DR_DATA UART_DR_FE UART_DR_PE UART_DR_BE UART_DR_OE

UART_DR_DATA : Data Transmitted or Received
bits : 0 - 7 (8 bit)

UART_DR_FE : UART Framing Error
bits : 8 - 16 (9 bit)

UART_DR_PE : UART Parity Error
bits : 9 - 18 (10 bit)

UART_DR_BE : UART Break Error
bits : 10 - 20 (11 bit)

UART_DR_OE : UART Overrun Error
bits : 11 - 22 (12 bit)


DR

UART Data
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_DR_DATA UART_DR_FE UART_DR_PE UART_DR_BE UART_DR_OE

UART_DR_DATA : Data Transmitted or Received
bits : 0 - 7 (8 bit)

UART_DR_FE : UART Framing Error
bits : 8 - 16 (9 bit)

UART_DR_PE : UART Parity Error
bits : 9 - 18 (10 bit)

UART_DR_BE : UART Break Error
bits : 10 - 20 (11 bit)

UART_DR_OE : UART Overrun Error
bits : 11 - 22 (12 bit)


UART0FR

UART Flag
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART0FR UART0FR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_FR_BUSY UART_FR_RXFE UART_FR_TXFF UART_FR_RXFF UART_FR_TXFE

UART_FR_BUSY : UART Busy
bits : 3 - 6 (4 bit)

UART_FR_RXFE : UART Receive FIFO Empty
bits : 4 - 8 (5 bit)

UART_FR_TXFF : UART Transmit FIFO Full
bits : 5 - 10 (6 bit)

UART_FR_RXFF : UART Receive FIFO Full
bits : 6 - 12 (7 bit)

UART_FR_TXFE : UART Transmit FIFO Empty
bits : 7 - 14 (8 bit)


FR

UART Flag
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR FR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_FR_BUSY UART_FR_RXFE UART_FR_TXFF UART_FR_RXFF UART_FR_TXFE

UART_FR_BUSY : UART Busy
bits : 3 - 6 (4 bit)

UART_FR_RXFE : UART Receive FIFO Empty
bits : 4 - 8 (5 bit)

UART_FR_TXFF : UART Transmit FIFO Full
bits : 5 - 10 (6 bit)

UART_FR_RXFF : UART Receive FIFO Full
bits : 6 - 12 (7 bit)

UART_FR_TXFE : UART Transmit FIFO Empty
bits : 7 - 14 (8 bit)


UART0IBRD

UART Integer Baud-Rate Divisor
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART0IBRD UART0IBRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_IBRD_DIVINT

UART_IBRD_DIVINT : Integer Baud-Rate Divisor
bits : 0 - 15 (16 bit)


IBRD

UART Integer Baud-Rate Divisor
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IBRD IBRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_IBRD_DIVINT

UART_IBRD_DIVINT : Integer Baud-Rate Divisor
bits : 0 - 15 (16 bit)


UART0FBRD

UART Fractional Baud-Rate Divisor
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART0FBRD UART0FBRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_FBRD_DIVFRAC

UART_FBRD_DIVFRAC : Fractional Baud-Rate Divisor
bits : 0 - 5 (6 bit)


FBRD

UART Fractional Baud-Rate Divisor
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FBRD FBRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_FBRD_DIVFRAC

UART_FBRD_DIVFRAC : Fractional Baud-Rate Divisor
bits : 0 - 5 (6 bit)


UART0LCRH

UART Line Control
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART0LCRH UART0LCRH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_LCRH_BRK UART_LCRH_PEN UART_LCRH_EPS UART_LCRH_STP2 UART_LCRH_FEN UART_LCRH_WLEN UART_LCRH_SPS

UART_LCRH_BRK : UART Send Break
bits : 0 - 0 (1 bit)

UART_LCRH_PEN : UART Parity Enable
bits : 1 - 2 (2 bit)

UART_LCRH_EPS : UART Even Parity Select
bits : 2 - 4 (3 bit)

UART_LCRH_STP2 : UART Two Stop Bits Select
bits : 3 - 6 (4 bit)

UART_LCRH_FEN : UART Enable FIFOs
bits : 4 - 8 (5 bit)

UART_LCRH_WLEN : UART Word Length
bits : 5 - 11 (7 bit)

Enumeration:

0x0 : UART_LCRH_WLEN_5

5 bits (default)

0x1 : UART_LCRH_WLEN_6

6 bits

0x2 : UART_LCRH_WLEN_7

7 bits

0x3 : UART_LCRH_WLEN_8

8 bits

End of enumeration elements list.

UART_LCRH_SPS : UART Stick Parity Select
bits : 7 - 14 (8 bit)


LCRH

UART Line Control
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCRH LCRH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_LCRH_BRK UART_LCRH_PEN UART_LCRH_EPS UART_LCRH_STP2 UART_LCRH_FEN UART_LCRH_WLEN UART_LCRH_SPS

UART_LCRH_BRK : UART Send Break
bits : 0 - 0 (1 bit)

UART_LCRH_PEN : UART Parity Enable
bits : 1 - 2 (2 bit)

UART_LCRH_EPS : UART Even Parity Select
bits : 2 - 4 (3 bit)

UART_LCRH_STP2 : UART Two Stop Bits Select
bits : 3 - 6 (4 bit)

UART_LCRH_FEN : UART Enable FIFOs
bits : 4 - 8 (5 bit)

UART_LCRH_WLEN : UART Word Length
bits : 5 - 11 (7 bit)

Enumeration:

0x0 : UART_LCRH_WLEN_5

5 bits (default)

0x1 : UART_LCRH_WLEN_6

6 bits

0x2 : UART_LCRH_WLEN_7

7 bits

0x3 : UART_LCRH_WLEN_8

8 bits

End of enumeration elements list.

UART_LCRH_SPS : UART Stick Parity Select
bits : 7 - 14 (8 bit)


UART0CTL

UART Control
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART0CTL UART0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_CTL_UARTEN UART_CTL_LBE UART_CTL_TXE UART_CTL_RXE

UART_CTL_UARTEN : UART Enable
bits : 0 - 0 (1 bit)

UART_CTL_LBE : UART Loop Back Enable
bits : 7 - 14 (8 bit)

UART_CTL_TXE : UART Transmit Enable
bits : 8 - 16 (9 bit)

UART_CTL_RXE : UART Receive Enable
bits : 9 - 18 (10 bit)


CTL

UART Control
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_CTL_UARTEN UART_CTL_LBE UART_CTL_TXE UART_CTL_RXE

UART_CTL_UARTEN : UART Enable
bits : 0 - 0 (1 bit)

UART_CTL_LBE : UART Loop Back Enable
bits : 7 - 14 (8 bit)

UART_CTL_TXE : UART Transmit Enable
bits : 8 - 16 (9 bit)

UART_CTL_RXE : UART Receive Enable
bits : 9 - 18 (10 bit)


UART0IFLS

UART Interrupt FIFO Level Select
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART0IFLS UART0IFLS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_IFLS_TX UART_IFLS_RX

UART_IFLS_TX : UART Transmit Interrupt FIFO Level Select
bits : 0 - 2 (3 bit)

Enumeration:

0x0 : UART_IFLS_TX1_8

TX FIFO <= 1/8 full

0x1 : UART_IFLS_TX2_8

TX FIFO <= 1/4 full

0x2 : UART_IFLS_TX4_8

TX FIFO <= 1/2 full (default)

0x3 : UART_IFLS_TX6_8

TX FIFO <= 3/4 full

0x4 : UART_IFLS_TX7_8

TX FIFO <= 7/8 full

End of enumeration elements list.

UART_IFLS_RX : UART Receive Interrupt FIFO Level Select
bits : 3 - 8 (6 bit)

Enumeration:

0x0 : UART_IFLS_RX1_8

RX FIFO >= 1/8 full

0x1 : UART_IFLS_RX2_8

RX FIFO >= 1/4 full

0x2 : UART_IFLS_RX4_8

RX FIFO >= 1/2 full (default)

0x3 : UART_IFLS_RX6_8

RX FIFO >= 3/4 full

0x4 : UART_IFLS_RX7_8

RX FIFO >= 7/8 full

End of enumeration elements list.


IFLS

UART Interrupt FIFO Level Select
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFLS IFLS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_IFLS_TX UART_IFLS_RX

UART_IFLS_TX : UART Transmit Interrupt FIFO Level Select
bits : 0 - 2 (3 bit)

Enumeration:

0x0 : UART_IFLS_TX1_8

TX FIFO and lt = 1/8 full

0x1 : UART_IFLS_TX2_8

TX FIFO and lt = 1/4 full

0x2 : UART_IFLS_TX4_8

TX FIFO and lt = 1/2 full (default)

0x3 : UART_IFLS_TX6_8

TX FIFO and lt = 3/4 full

0x4 : UART_IFLS_TX7_8

TX FIFO and lt = 7/8 full

End of enumeration elements list.

UART_IFLS_RX : UART Receive Interrupt FIFO Level Select
bits : 3 - 8 (6 bit)

Enumeration:

0x0 : UART_IFLS_RX1_8

RX FIFO >= 1/8 full

0x1 : UART_IFLS_RX2_8

RX FIFO >= 1/4 full

0x2 : UART_IFLS_RX4_8

RX FIFO >= 1/2 full (default)

0x3 : UART_IFLS_RX6_8

RX FIFO >= 3/4 full

0x4 : UART_IFLS_RX7_8

RX FIFO >= 7/8 full

End of enumeration elements list.


UART0IM

UART Interrupt Mask
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART0IM UART0IM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_IM_RXIM UART_IM_TXIM UART_IM_RTIM UART_IM_FEIM UART_IM_PEIM UART_IM_BEIM UART_IM_OEIM

UART_IM_RXIM : UART Receive Interrupt Mask
bits : 4 - 8 (5 bit)

UART_IM_TXIM : UART Transmit Interrupt Mask
bits : 5 - 10 (6 bit)

UART_IM_RTIM : UART Receive Time-Out Interrupt Mask
bits : 6 - 12 (7 bit)

UART_IM_FEIM : UART Framing Error Interrupt Mask
bits : 7 - 14 (8 bit)

UART_IM_PEIM : UART Parity Error Interrupt Mask
bits : 8 - 16 (9 bit)

UART_IM_BEIM : UART Break Error Interrupt Mask
bits : 9 - 18 (10 bit)

UART_IM_OEIM : UART Overrun Error Interrupt Mask
bits : 10 - 20 (11 bit)


IM

UART Interrupt Mask
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IM IM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_IM_RXIM UART_IM_TXIM UART_IM_RTIM UART_IM_FEIM UART_IM_PEIM UART_IM_BEIM UART_IM_OEIM

UART_IM_RXIM : UART Receive Interrupt Mask
bits : 4 - 8 (5 bit)

UART_IM_TXIM : UART Transmit Interrupt Mask
bits : 5 - 10 (6 bit)

UART_IM_RTIM : UART Receive Time-Out Interrupt Mask
bits : 6 - 12 (7 bit)

UART_IM_FEIM : UART Framing Error Interrupt Mask
bits : 7 - 14 (8 bit)

UART_IM_PEIM : UART Parity Error Interrupt Mask
bits : 8 - 16 (9 bit)

UART_IM_BEIM : UART Break Error Interrupt Mask
bits : 9 - 18 (10 bit)

UART_IM_OEIM : UART Overrun Error Interrupt Mask
bits : 10 - 20 (11 bit)


UART0RIS

UART Raw Interrupt Status
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART0RIS UART0RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_RIS_RXRIS UART_RIS_TXRIS UART_RIS_RTRIS UART_RIS_FERIS UART_RIS_PERIS UART_RIS_BERIS UART_RIS_OERIS

UART_RIS_RXRIS : UART Receive Raw Interrupt Status
bits : 4 - 8 (5 bit)

UART_RIS_TXRIS : UART Transmit Raw Interrupt Status
bits : 5 - 10 (6 bit)

UART_RIS_RTRIS : UART Receive Time-Out Raw Interrupt Status
bits : 6 - 12 (7 bit)

UART_RIS_FERIS : UART Framing Error Raw Interrupt Status
bits : 7 - 14 (8 bit)

UART_RIS_PERIS : UART Parity Error Raw Interrupt Status
bits : 8 - 16 (9 bit)

UART_RIS_BERIS : UART Break Error Raw Interrupt Status
bits : 9 - 18 (10 bit)

UART_RIS_OERIS : UART Overrun Error Raw Interrupt Status
bits : 10 - 20 (11 bit)


RIS

UART Raw Interrupt Status
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_RIS_RXRIS UART_RIS_TXRIS UART_RIS_RTRIS UART_RIS_FERIS UART_RIS_PERIS UART_RIS_BERIS UART_RIS_OERIS

UART_RIS_RXRIS : UART Receive Raw Interrupt Status
bits : 4 - 8 (5 bit)

UART_RIS_TXRIS : UART Transmit Raw Interrupt Status
bits : 5 - 10 (6 bit)

UART_RIS_RTRIS : UART Receive Time-Out Raw Interrupt Status
bits : 6 - 12 (7 bit)

UART_RIS_FERIS : UART Framing Error Raw Interrupt Status
bits : 7 - 14 (8 bit)

UART_RIS_PERIS : UART Parity Error Raw Interrupt Status
bits : 8 - 16 (9 bit)

UART_RIS_BERIS : UART Break Error Raw Interrupt Status
bits : 9 - 18 (10 bit)

UART_RIS_OERIS : UART Overrun Error Raw Interrupt Status
bits : 10 - 20 (11 bit)


UART0RSR

UART Receive Status/Error Clear
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART0RSR UART0RSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_RSR_FE UART_RSR_PE UART_RSR_BE UART_RSR_OE

UART_RSR_FE : UART Framing Error
bits : 0 - 0 (1 bit)

UART_RSR_PE : UART Parity Error
bits : 1 - 2 (2 bit)

UART_RSR_BE : UART Break Error
bits : 2 - 4 (3 bit)

UART_RSR_OE : UART Overrun Error
bits : 3 - 6 (4 bit)


UART0ECR

UART Receive Status/Error Clear
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : UART_ALT
reset_Mask : 0x0

UART0ECR UART0ECR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_ECR_DATA

UART_ECR_DATA : Error Clear
bits : 0 - 7 (8 bit)


RSR

UART Receive Status/Error Clear
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSR RSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_RSR_FE UART_RSR_PE UART_RSR_BE UART_RSR_OE

UART_RSR_FE : UART Framing Error
bits : 0 - 0 (1 bit)

UART_RSR_PE : UART Parity Error
bits : 1 - 2 (2 bit)

UART_RSR_BE : UART Break Error
bits : 2 - 4 (3 bit)

UART_RSR_OE : UART Overrun Error
bits : 3 - 6 (4 bit)


ECR

UART Receive Status/Error Clear
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECR ECR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_ECR_DATA

UART_ECR_DATA : Error Clear
bits : 0 - 7 (8 bit)


UART0MIS

UART Masked Interrupt Status
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART0MIS UART0MIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_MIS_RXMIS UART_MIS_TXMIS UART_MIS_RTMIS UART_MIS_FEMIS UART_MIS_PEMIS UART_MIS_BEMIS UART_MIS_OEMIS

UART_MIS_RXMIS : UART Receive Masked Interrupt Status
bits : 4 - 8 (5 bit)

UART_MIS_TXMIS : UART Transmit Masked Interrupt Status
bits : 5 - 10 (6 bit)

UART_MIS_RTMIS : UART Receive Time-Out Masked Interrupt Status
bits : 6 - 12 (7 bit)

UART_MIS_FEMIS : UART Framing Error Masked Interrupt Status
bits : 7 - 14 (8 bit)

UART_MIS_PEMIS : UART Parity Error Masked Interrupt Status
bits : 8 - 16 (9 bit)

UART_MIS_BEMIS : UART Break Error Masked Interrupt Status
bits : 9 - 18 (10 bit)

UART_MIS_OEMIS : UART Overrun Error Masked Interrupt Status
bits : 10 - 20 (11 bit)


MIS

UART Masked Interrupt Status
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIS MIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_MIS_RXMIS UART_MIS_TXMIS UART_MIS_RTMIS UART_MIS_FEMIS UART_MIS_PEMIS UART_MIS_BEMIS UART_MIS_OEMIS

UART_MIS_RXMIS : UART Receive Masked Interrupt Status
bits : 4 - 8 (5 bit)

UART_MIS_TXMIS : UART Transmit Masked Interrupt Status
bits : 5 - 10 (6 bit)

UART_MIS_RTMIS : UART Receive Time-Out Masked Interrupt Status
bits : 6 - 12 (7 bit)

UART_MIS_FEMIS : UART Framing Error Masked Interrupt Status
bits : 7 - 14 (8 bit)

UART_MIS_PEMIS : UART Parity Error Masked Interrupt Status
bits : 8 - 16 (9 bit)

UART_MIS_BEMIS : UART Break Error Masked Interrupt Status
bits : 9 - 18 (10 bit)

UART_MIS_OEMIS : UART Overrun Error Masked Interrupt Status
bits : 10 - 20 (11 bit)


UART0ICR

UART Interrupt Clear
address_offset : 0x44 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UART0ICR UART0ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_ICR_RXIC UART_ICR_TXIC UART_ICR_RTIC UART_ICR_FEIC UART_ICR_PEIC UART_ICR_BEIC UART_ICR_OEIC

UART_ICR_RXIC : Receive Interrupt Clear
bits : 4 - 8 (5 bit)
access : write-only

UART_ICR_TXIC : Transmit Interrupt Clear
bits : 5 - 10 (6 bit)
access : write-only

UART_ICR_RTIC : Receive Time-Out Interrupt Clear
bits : 6 - 12 (7 bit)
access : write-only

UART_ICR_FEIC : Framing Error Interrupt Clear
bits : 7 - 14 (8 bit)
access : write-only

UART_ICR_PEIC : Parity Error Interrupt Clear
bits : 8 - 16 (9 bit)
access : write-only

UART_ICR_BEIC : Break Error Interrupt Clear
bits : 9 - 18 (10 bit)
access : write-only

UART_ICR_OEIC : Overrun Error Interrupt Clear
bits : 10 - 20 (11 bit)
access : write-only


ICR

UART Interrupt Clear
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICR ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_ICR_RXIC UART_ICR_TXIC UART_ICR_RTIC UART_ICR_FEIC UART_ICR_PEIC UART_ICR_BEIC UART_ICR_OEIC

UART_ICR_RXIC : Receive Interrupt Clear
bits : 4 - 8 (5 bit)
access : write-only

UART_ICR_TXIC : Transmit Interrupt Clear
bits : 5 - 10 (6 bit)
access : write-only

UART_ICR_RTIC : Receive Time-Out Interrupt Clear
bits : 6 - 12 (7 bit)
access : write-only

UART_ICR_FEIC : Framing Error Interrupt Clear
bits : 7 - 14 (8 bit)
access : write-only

UART_ICR_PEIC : Parity Error Interrupt Clear
bits : 8 - 16 (9 bit)
access : write-only

UART_ICR_BEIC : Break Error Interrupt Clear
bits : 9 - 18 (10 bit)
access : write-only

UART_ICR_OEIC : Overrun Error Interrupt Clear
bits : 10 - 20 (11 bit)
access : write-only



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