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PWM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PWM0CTL

CTL

PWM0FAULT

FAULT

PWM0INTEN

INTEN

PWM0RIS

RIS

PWM0ISC

ISC

PWM0STATUS

STATUS

PWM0SYNC

SYNC

0_CTL

_0_CTL

0_INTEN

_0_INTEN

0_RIS

_0_RIS

0_ISC

_0_ISC

0_LOAD

_0_LOAD

0_COUNT

_0_COUNT

0_CMPA

_0_CMPA

0_CMPB

_0_CMPB

0_GENA

_0_GENA

0_GENB

_0_GENB

0_DBCTL

_0_DBCTL

0_DBRISE

_0_DBRISE

0_DBFALL

_0_DBFALL

PWM0ENABLE

ENABLE

1_CTL

_1_CTL

1_INTEN

_1_INTEN

1_RIS

_1_RIS

1_ISC

_1_ISC

1_LOAD

_1_LOAD

1_COUNT

_1_COUNT

1_CMPA

_1_CMPA

1_CMPB

_1_CMPB

1_GENA

_1_GENA

1_GENB

_1_GENB

1_DBCTL

_1_DBCTL

1_DBRISE

_1_DBRISE

1_DBFALL

_1_DBFALL

PWM0INVERT

INVERT

2_CTL

_2_CTL

2_INTEN

_2_INTEN

2_RIS

_2_RIS

2_ISC

_2_ISC

2_LOAD

_2_LOAD

2_COUNT

_2_COUNT

2_CMPA

_2_CMPA

2_CMPB

_2_CMPB

2_GENA

_2_GENA

2_GENB

_2_GENB

2_DBCTL

_2_DBCTL

2_DBRISE

_2_DBRISE

2_DBFALL

_2_DBFALL


PWM0CTL

PWM Master Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0CTL PWM0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_CTL_GLOBALSYNC0 PWM_CTL_GLOBALSYNC1 PWM_CTL_GLOBALSYNC2

PWM_CTL_GLOBALSYNC0 : Update PWM Generator 0
bits : 0 - 0 (1 bit)

PWM_CTL_GLOBALSYNC1 : Update PWM Generator 1
bits : 1 - 2 (2 bit)

PWM_CTL_GLOBALSYNC2 : Update PWM Generator 2
bits : 2 - 4 (3 bit)


CTL

PWM Master Control
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_CTL_GLOBALSYNC0 PWM_CTL_GLOBALSYNC1 PWM_CTL_GLOBALSYNC2

PWM_CTL_GLOBALSYNC0 : Update PWM Generator 0
bits : 0 - 0 (1 bit)

PWM_CTL_GLOBALSYNC1 : Update PWM Generator 1
bits : 1 - 2 (2 bit)

PWM_CTL_GLOBALSYNC2 : Update PWM Generator 2
bits : 2 - 4 (3 bit)


PWM0FAULT

PWM Output Fault
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0FAULT PWM0FAULT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_FAULT_FAULT0 PWM_FAULT_FAULT1 PWM_FAULT_FAULT2 PWM_FAULT_FAULT3 PWM_FAULT_FAULT4 PWM_FAULT_FAULT5

PWM_FAULT_FAULT0 : PWM0 Fault
bits : 0 - 0 (1 bit)

PWM_FAULT_FAULT1 : PWM1 Fault
bits : 1 - 2 (2 bit)

PWM_FAULT_FAULT2 : PWM2 Fault
bits : 2 - 4 (3 bit)

PWM_FAULT_FAULT3 : PWM3 Fault
bits : 3 - 6 (4 bit)

PWM_FAULT_FAULT4 : PWM4 Fault
bits : 4 - 8 (5 bit)

PWM_FAULT_FAULT5 : PWM5 Fault
bits : 5 - 10 (6 bit)


FAULT

PWM Output Fault
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FAULT FAULT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_FAULT_FAULT0 PWM_FAULT_FAULT1 PWM_FAULT_FAULT2 PWM_FAULT_FAULT3 PWM_FAULT_FAULT4 PWM_FAULT_FAULT5

PWM_FAULT_FAULT0 : PWM0 Fault
bits : 0 - 0 (1 bit)

PWM_FAULT_FAULT1 : PWM1 Fault
bits : 1 - 2 (2 bit)

PWM_FAULT_FAULT2 : PWM2 Fault
bits : 2 - 4 (3 bit)

PWM_FAULT_FAULT3 : PWM3 Fault
bits : 3 - 6 (4 bit)

PWM_FAULT_FAULT4 : PWM4 Fault
bits : 4 - 8 (5 bit)

PWM_FAULT_FAULT5 : PWM5 Fault
bits : 5 - 10 (6 bit)


PWM0INTEN

PWM Interrupt Enable
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0INTEN PWM0INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_INTEN_INTPWM0 PWM_INTEN_INTPWM1 PWM_INTEN_INTPWM2 PWM_INTEN_INTFAULT

PWM_INTEN_INTPWM0 : PWM0 Interrupt Enable
bits : 0 - 0 (1 bit)

PWM_INTEN_INTPWM1 : PWM1 Interrupt Enable
bits : 1 - 2 (2 bit)

PWM_INTEN_INTPWM2 : PWM2 Interrupt Enable
bits : 2 - 4 (3 bit)

PWM_INTEN_INTFAULT : Fault Interrupt Enable
bits : 16 - 32 (17 bit)


INTEN

PWM Interrupt Enable
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_INTEN_INTPWM0 PWM_INTEN_INTPWM1 PWM_INTEN_INTPWM2 PWM_INTEN_INTFAULT

PWM_INTEN_INTPWM0 : PWM0 Interrupt Enable
bits : 0 - 0 (1 bit)

PWM_INTEN_INTPWM1 : PWM1 Interrupt Enable
bits : 1 - 2 (2 bit)

PWM_INTEN_INTPWM2 : PWM2 Interrupt Enable
bits : 2 - 4 (3 bit)

PWM_INTEN_INTFAULT : Fault Interrupt Enable
bits : 16 - 32 (17 bit)


PWM0RIS

PWM Raw Interrupt Status
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0RIS PWM0RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_RIS_INTPWM0 PWM_RIS_INTPWM1 PWM_RIS_INTPWM2 PWM_RIS_INTFAULT

PWM_RIS_INTPWM0 : PWM0 Interrupt Asserted
bits : 0 - 0 (1 bit)

PWM_RIS_INTPWM1 : PWM1 Interrupt Asserted
bits : 1 - 2 (2 bit)

PWM_RIS_INTPWM2 : PWM2 Interrupt Asserted
bits : 2 - 4 (3 bit)

PWM_RIS_INTFAULT : Fault Interrupt Asserted
bits : 16 - 32 (17 bit)


RIS

PWM Raw Interrupt Status
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_RIS_INTPWM0 PWM_RIS_INTPWM1 PWM_RIS_INTPWM2 PWM_RIS_INTFAULT

PWM_RIS_INTPWM0 : PWM0 Interrupt Asserted
bits : 0 - 0 (1 bit)

PWM_RIS_INTPWM1 : PWM1 Interrupt Asserted
bits : 1 - 2 (2 bit)

PWM_RIS_INTPWM2 : PWM2 Interrupt Asserted
bits : 2 - 4 (3 bit)

PWM_RIS_INTFAULT : Fault Interrupt Asserted
bits : 16 - 32 (17 bit)


PWM0ISC

PWM Interrupt Status and Clear
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0ISC PWM0ISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_ISC_INTPWM0 PWM_ISC_INTPWM1 PWM_ISC_INTPWM2 PWM_ISC_INTFAULT

PWM_ISC_INTPWM0 : PWM0 Interrupt Status
bits : 0 - 0 (1 bit)

PWM_ISC_INTPWM1 : PWM1 Interrupt Status
bits : 1 - 2 (2 bit)

PWM_ISC_INTPWM2 : PWM2 Interrupt Status
bits : 2 - 4 (3 bit)

PWM_ISC_INTFAULT : Fault Interrupt Asserted
bits : 16 - 32 (17 bit)


ISC

PWM Interrupt Status and Clear
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISC ISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_ISC_INTPWM0 PWM_ISC_INTPWM1 PWM_ISC_INTPWM2 PWM_ISC_INTFAULT

PWM_ISC_INTPWM0 : PWM0 Interrupt Status
bits : 0 - 0 (1 bit)

PWM_ISC_INTPWM1 : PWM1 Interrupt Status
bits : 1 - 2 (2 bit)

PWM_ISC_INTPWM2 : PWM2 Interrupt Status
bits : 2 - 4 (3 bit)

PWM_ISC_INTFAULT : Fault Interrupt Asserted
bits : 16 - 32 (17 bit)


PWM0STATUS

PWM Status
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0STATUS PWM0STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

STATUS

PWM Status
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM0SYNC

PWM Time Base Sync
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0SYNC PWM0SYNC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_SYNC_SYNC0 PWM_SYNC_SYNC1 PWM_SYNC_SYNC2

PWM_SYNC_SYNC0 : Reset Generator 0 Counter
bits : 0 - 0 (1 bit)

PWM_SYNC_SYNC1 : Reset Generator 1 Counter
bits : 1 - 2 (2 bit)

PWM_SYNC_SYNC2 : Reset Generator 2 Counter
bits : 2 - 4 (3 bit)


SYNC

PWM Time Base Sync
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNC SYNC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_SYNC_SYNC0 PWM_SYNC_SYNC1 PWM_SYNC_SYNC2

PWM_SYNC_SYNC0 : Reset Generator 0 Counter
bits : 0 - 0 (1 bit)

PWM_SYNC_SYNC1 : Reset Generator 1 Counter
bits : 1 - 2 (2 bit)

PWM_SYNC_SYNC2 : Reset Generator 2 Counter
bits : 2 - 4 (3 bit)


0_CTL

PWM0 Control
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

0_CTL 0_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_CTL_ENABLE PWM_X_CTL_MODE PWM_X_CTL_DEBUG PWM_X_CTL_LOADUPD PWM_X_CTL_CMPAUPD PWM_X_CTL_CMPBUPD

PWM_X_CTL_ENABLE : PWM Block Enable
bits : 0 - 0 (1 bit)

PWM_X_CTL_MODE : Counter Mode
bits : 1 - 2 (2 bit)

PWM_X_CTL_DEBUG : Debug Mode
bits : 2 - 4 (3 bit)

PWM_X_CTL_LOADUPD : Load Register Update Mode
bits : 3 - 6 (4 bit)

PWM_X_CTL_CMPAUPD : Comparator A Update Mode
bits : 4 - 8 (5 bit)

PWM_X_CTL_CMPBUPD : Comparator B Update Mode
bits : 5 - 10 (6 bit)


_0_CTL

PWM0 Control
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_0_CTL _0_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_CTL_ENABLE PWM_X_CTL_MODE PWM_X_CTL_DEBUG PWM_X_CTL_LOADUPD PWM_X_CTL_CMPAUPD PWM_X_CTL_CMPBUPD

PWM_X_CTL_ENABLE : PWM Block Enable
bits : 0 - 0 (1 bit)

PWM_X_CTL_MODE : Counter Mode
bits : 1 - 2 (2 bit)

PWM_X_CTL_DEBUG : Debug Mode
bits : 2 - 4 (3 bit)

PWM_X_CTL_LOADUPD : Load Register Update Mode
bits : 3 - 6 (4 bit)

PWM_X_CTL_CMPAUPD : Comparator A Update Mode
bits : 4 - 8 (5 bit)

PWM_X_CTL_CMPBUPD : Comparator B Update Mode
bits : 5 - 10 (6 bit)


0_INTEN

PWM0 Interrupt and Trigger Enable
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

0_INTEN 0_INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_INTEN_INTCNTZERO PWM_X_INTEN_INTCNTLOAD PWM_X_INTEN_INTCMPAU PWM_X_INTEN_INTCMPAD PWM_X_INTEN_INTCMPBU PWM_X_INTEN_INTCMPBD PWM_X_INTEN_TRCNTZERO PWM_X_INTEN_TRCNTLOAD PWM_X_INTEN_TRCMPAU PWM_X_INTEN_TRCMPAD PWM_X_INTEN_TRCMPBU PWM_X_INTEN_TRCMPBD

PWM_X_INTEN_INTCNTZERO : Interrupt for Counter=0
bits : 0 - 0 (1 bit)

PWM_X_INTEN_INTCNTLOAD : Interrupt for Counter=PWMnLOAD
bits : 1 - 2 (2 bit)

PWM_X_INTEN_INTCMPAU : Interrupt for Counter=PWMnCMPA Up
bits : 2 - 4 (3 bit)

PWM_X_INTEN_INTCMPAD : Interrupt for Counter=PWMnCMPA Down
bits : 3 - 6 (4 bit)

PWM_X_INTEN_INTCMPBU : Interrupt for Counter=PWMnCMPB Up
bits : 4 - 8 (5 bit)

PWM_X_INTEN_INTCMPBD : Interrupt for Counter=PWMnCMPB Down
bits : 5 - 10 (6 bit)

PWM_X_INTEN_TRCNTZERO : Trigger for Counter=0
bits : 8 - 16 (9 bit)

PWM_X_INTEN_TRCNTLOAD : Trigger for Counter=PWMnLOAD
bits : 9 - 18 (10 bit)

PWM_X_INTEN_TRCMPAU : Trigger for Counter=PWMnCMPA Up
bits : 10 - 20 (11 bit)

PWM_X_INTEN_TRCMPAD : Trigger for Counter=PWMnCMPA Down
bits : 11 - 22 (12 bit)

PWM_X_INTEN_TRCMPBU : Trigger for Counter=PWMnCMPB Up
bits : 12 - 24 (13 bit)

PWM_X_INTEN_TRCMPBD : Trigger for Counter=PWMnCMPB Down
bits : 13 - 26 (14 bit)


_0_INTEN

PWM0 Interrupt and Trigger Enable
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_0_INTEN _0_INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_INTEN_INTCNTZERO PWM_X_INTEN_INTCNTLOAD PWM_X_INTEN_INTCMPAU PWM_X_INTEN_INTCMPAD PWM_X_INTEN_INTCMPBU PWM_X_INTEN_INTCMPBD PWM_X_INTEN_TRCNTZERO PWM_X_INTEN_TRCNTLOAD PWM_X_INTEN_TRCMPAU PWM_X_INTEN_TRCMPAD PWM_X_INTEN_TRCMPBU PWM_X_INTEN_TRCMPBD

PWM_X_INTEN_INTCNTZERO : Interrupt for Counter=0
bits : 0 - 0 (1 bit)

PWM_X_INTEN_INTCNTLOAD : Interrupt for Counter=PWMnLOAD
bits : 1 - 2 (2 bit)

PWM_X_INTEN_INTCMPAU : Interrupt for Counter=PWMnCMPA Up
bits : 2 - 4 (3 bit)

PWM_X_INTEN_INTCMPAD : Interrupt for Counter=PWMnCMPA Down
bits : 3 - 6 (4 bit)

PWM_X_INTEN_INTCMPBU : Interrupt for Counter=PWMnCMPB Up
bits : 4 - 8 (5 bit)

PWM_X_INTEN_INTCMPBD : Interrupt for Counter=PWMnCMPB Down
bits : 5 - 10 (6 bit)

PWM_X_INTEN_TRCNTZERO : Trigger for Counter=0
bits : 8 - 16 (9 bit)

PWM_X_INTEN_TRCNTLOAD : Trigger for Counter=PWMnLOAD
bits : 9 - 18 (10 bit)

PWM_X_INTEN_TRCMPAU : Trigger for Counter=PWMnCMPA Up
bits : 10 - 20 (11 bit)

PWM_X_INTEN_TRCMPAD : Trigger for Counter=PWMnCMPA Down
bits : 11 - 22 (12 bit)

PWM_X_INTEN_TRCMPBU : Trigger for Counter=PWMnCMPB Up
bits : 12 - 24 (13 bit)

PWM_X_INTEN_TRCMPBD : Trigger for Counter=PWMnCMPB Down
bits : 13 - 26 (14 bit)


0_RIS

PWM0 Raw Interrupt Status
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

0_RIS 0_RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_RIS_INTCNTZERO PWM_X_RIS_INTCNTLOAD PWM_X_RIS_INTCMPAU PWM_X_RIS_INTCMPAD PWM_X_RIS_INTCMPBU PWM_X_RIS_INTCMPBD

PWM_X_RIS_INTCNTZERO : Counter=0 Interrupt Status
bits : 0 - 0 (1 bit)

PWM_X_RIS_INTCNTLOAD : Counter=Load Interrupt Status
bits : 1 - 2 (2 bit)

PWM_X_RIS_INTCMPAU : Comparator A Up Interrupt Status
bits : 2 - 4 (3 bit)

PWM_X_RIS_INTCMPAD : Comparator A Down Interrupt Status
bits : 3 - 6 (4 bit)

PWM_X_RIS_INTCMPBU : Comparator B Up Interrupt Status
bits : 4 - 8 (5 bit)

PWM_X_RIS_INTCMPBD : Comparator B Down Interrupt Status
bits : 5 - 10 (6 bit)


_0_RIS

PWM0 Raw Interrupt Status
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_0_RIS _0_RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_RIS_INTCNTZERO PWM_X_RIS_INTCNTLOAD PWM_X_RIS_INTCMPAU PWM_X_RIS_INTCMPAD PWM_X_RIS_INTCMPBU PWM_X_RIS_INTCMPBD

PWM_X_RIS_INTCNTZERO : Counter=0 Interrupt Status
bits : 0 - 0 (1 bit)

PWM_X_RIS_INTCNTLOAD : Counter=Load Interrupt Status
bits : 1 - 2 (2 bit)

PWM_X_RIS_INTCMPAU : Comparator A Up Interrupt Status
bits : 2 - 4 (3 bit)

PWM_X_RIS_INTCMPAD : Comparator A Down Interrupt Status
bits : 3 - 6 (4 bit)

PWM_X_RIS_INTCMPBU : Comparator B Up Interrupt Status
bits : 4 - 8 (5 bit)

PWM_X_RIS_INTCMPBD : Comparator B Down Interrupt Status
bits : 5 - 10 (6 bit)


0_ISC

PWM0 Interrupt Status and Clear
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

0_ISC 0_ISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_ISC_INTCNTZERO PWM_X_ISC_INTCNTLOAD PWM_X_ISC_INTCMPAU PWM_X_ISC_INTCMPAD PWM_X_ISC_INTCMPBU PWM_X_ISC_INTCMPBD

PWM_X_ISC_INTCNTZERO : Counter=0 Interrupt
bits : 0 - 0 (1 bit)

PWM_X_ISC_INTCNTLOAD : Counter=Load Interrupt
bits : 1 - 2 (2 bit)

PWM_X_ISC_INTCMPAU : Comparator A Up Interrupt
bits : 2 - 4 (3 bit)

PWM_X_ISC_INTCMPAD : Comparator A Down Interrupt
bits : 3 - 6 (4 bit)

PWM_X_ISC_INTCMPBU : Comparator B Up Interrupt
bits : 4 - 8 (5 bit)

PWM_X_ISC_INTCMPBD : Comparator B Down Interrupt
bits : 5 - 10 (6 bit)


_0_ISC

PWM0 Interrupt Status and Clear
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_0_ISC _0_ISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_ISC_INTCNTZERO PWM_X_ISC_INTCNTLOAD PWM_X_ISC_INTCMPAU PWM_X_ISC_INTCMPAD PWM_X_ISC_INTCMPBU PWM_X_ISC_INTCMPBD

PWM_X_ISC_INTCNTZERO : Counter=0 Interrupt
bits : 0 - 0 (1 bit)

PWM_X_ISC_INTCNTLOAD : Counter=Load Interrupt
bits : 1 - 2 (2 bit)

PWM_X_ISC_INTCMPAU : Comparator A Up Interrupt
bits : 2 - 4 (3 bit)

PWM_X_ISC_INTCMPAD : Comparator A Down Interrupt
bits : 3 - 6 (4 bit)

PWM_X_ISC_INTCMPBU : Comparator B Up Interrupt
bits : 4 - 8 (5 bit)

PWM_X_ISC_INTCMPBD : Comparator B Down Interrupt
bits : 5 - 10 (6 bit)


0_LOAD

PWM0 Load
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

0_LOAD 0_LOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_LOAD

PWM_X_LOAD : Counter Load Value
bits : 0 - 15 (16 bit)


_0_LOAD

PWM0 Load
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_0_LOAD _0_LOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_LOAD

PWM_X_LOAD : Counter Load Value
bits : 0 - 15 (16 bit)


0_COUNT

PWM0 Counter
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

0_COUNT 0_COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_COUNT

PWM_X_COUNT : Counter Value
bits : 0 - 15 (16 bit)


_0_COUNT

PWM0 Counter
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_0_COUNT _0_COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_COUNT

PWM_X_COUNT : Counter Value
bits : 0 - 15 (16 bit)


0_CMPA

PWM0 Compare A
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

0_CMPA 0_CMPA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_CMPA

PWM_X_CMPA : Comparator A Value
bits : 0 - 15 (16 bit)


_0_CMPA

PWM0 Compare A
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_0_CMPA _0_CMPA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_CMPA

PWM_X_CMPA : Comparator A Value
bits : 0 - 15 (16 bit)


0_CMPB

PWM0 Compare B
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

0_CMPB 0_CMPB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_CMPB

PWM_X_CMPB : Comparator B Value
bits : 0 - 15 (16 bit)


_0_CMPB

PWM0 Compare B
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_0_CMPB _0_CMPB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_CMPB

PWM_X_CMPB : Comparator B Value
bits : 0 - 15 (16 bit)


0_GENA

PWM0 Generator A Control
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

0_GENA 0_GENA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_GENA_ACTZERO PWM_X_GENA_ACTLOAD PWM_X_GENA_ACTCMPAU PWM_X_GENA_ACTCMPAD PWM_X_GENA_ACTCMPBU PWM_X_GENA_ACTCMPBD

PWM_X_GENA_ACTZERO : Action for Counter=0
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : PWM_X_GENA_ACTZERO_NONE

Do nothing

0x1 : PWM_X_GENA_ACTZERO_INV

Invert pwmA

0x2 : PWM_X_GENA_ACTZERO_ZERO

Drive pwmA Low

0x3 : PWM_X_GENA_ACTZERO_ONE

Drive pwmA High

End of enumeration elements list.

PWM_X_GENA_ACTLOAD : Action for Counter=LOAD
bits : 2 - 5 (4 bit)

Enumeration:

0x0 : PWM_X_GENA_ACTLOAD_NONE

Do nothing

0x1 : PWM_X_GENA_ACTLOAD_INV

Invert pwmA

0x2 : PWM_X_GENA_ACTLOAD_ZERO

Drive pwmA Low

0x3 : PWM_X_GENA_ACTLOAD_ONE

Drive pwmA High

End of enumeration elements list.

PWM_X_GENA_ACTCMPAU : Action for Comparator A Up
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : PWM_X_GENA_ACTCMPAU_NONE

Do nothing

0x1 : PWM_X_GENA_ACTCMPAU_INV

Invert pwmA

0x2 : PWM_X_GENA_ACTCMPAU_ZERO

Drive pwmA Low

0x3 : PWM_X_GENA_ACTCMPAU_ONE

Drive pwmA High

End of enumeration elements list.

PWM_X_GENA_ACTCMPAD : Action for Comparator A Down
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : PWM_X_GENA_ACTCMPAD_NONE

Do nothing

0x1 : PWM_X_GENA_ACTCMPAD_INV

Invert pwmA

0x2 : PWM_X_GENA_ACTCMPAD_ZERO

Drive pwmA Low

0x3 : PWM_X_GENA_ACTCMPAD_ONE

Drive pwmA High

End of enumeration elements list.

PWM_X_GENA_ACTCMPBU : Action for Comparator B Up
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : PWM_X_GENA_ACTCMPBU_NONE

Do nothing

0x1 : PWM_X_GENA_ACTCMPBU_INV

Invert pwmA

0x2 : PWM_X_GENA_ACTCMPBU_ZERO

Drive pwmA Low

0x3 : PWM_X_GENA_ACTCMPBU_ONE

Drive pwmA High

End of enumeration elements list.

PWM_X_GENA_ACTCMPBD : Action for Comparator B Down
bits : 10 - 21 (12 bit)

Enumeration:

0x0 : PWM_X_GENA_ACTCMPBD_NONE

Do nothing

0x1 : PWM_X_GENA_ACTCMPBD_INV

Invert pwmA

0x2 : PWM_X_GENA_ACTCMPBD_ZERO

Drive pwmA Low

0x3 : PWM_X_GENA_ACTCMPBD_ONE

Drive pwmA High

End of enumeration elements list.


_0_GENA

PWM0 Generator A Control
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_0_GENA _0_GENA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_GENA_ACTZERO PWM_X_GENA_ACTLOAD PWM_X_GENA_ACTCMPAU PWM_X_GENA_ACTCMPAD PWM_X_GENA_ACTCMPBU PWM_X_GENA_ACTCMPBD

PWM_X_GENA_ACTZERO : Action for Counter=0
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : PWM_X_GENA_ACTZERO_NONE

Do nothing

0x1 : PWM_X_GENA_ACTZERO_INV

Invert pwmA

0x2 : PWM_X_GENA_ACTZERO_ZERO

Drive pwmA Low

0x3 : PWM_X_GENA_ACTZERO_ONE

Drive pwmA High

End of enumeration elements list.

PWM_X_GENA_ACTLOAD : Action for Counter=LOAD
bits : 2 - 5 (4 bit)

Enumeration:

0x0 : PWM_X_GENA_ACTLOAD_NONE

Do nothing

0x1 : PWM_X_GENA_ACTLOAD_INV

Invert pwmA

0x2 : PWM_X_GENA_ACTLOAD_ZERO

Drive pwmA Low

0x3 : PWM_X_GENA_ACTLOAD_ONE

Drive pwmA High

End of enumeration elements list.

PWM_X_GENA_ACTCMPAU : Action for Comparator A Up
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : PWM_X_GENA_ACTCMPAU_NONE

Do nothing

0x1 : PWM_X_GENA_ACTCMPAU_INV

Invert pwmA

0x2 : PWM_X_GENA_ACTCMPAU_ZERO

Drive pwmA Low

0x3 : PWM_X_GENA_ACTCMPAU_ONE

Drive pwmA High

End of enumeration elements list.

PWM_X_GENA_ACTCMPAD : Action for Comparator A Down
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : PWM_X_GENA_ACTCMPAD_NONE

Do nothing

0x1 : PWM_X_GENA_ACTCMPAD_INV

Invert pwmA

0x2 : PWM_X_GENA_ACTCMPAD_ZERO

Drive pwmA Low

0x3 : PWM_X_GENA_ACTCMPAD_ONE

Drive pwmA High

End of enumeration elements list.

PWM_X_GENA_ACTCMPBU : Action for Comparator B Up
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : PWM_X_GENA_ACTCMPBU_NONE

Do nothing

0x1 : PWM_X_GENA_ACTCMPBU_INV

Invert pwmA

0x2 : PWM_X_GENA_ACTCMPBU_ZERO

Drive pwmA Low

0x3 : PWM_X_GENA_ACTCMPBU_ONE

Drive pwmA High

End of enumeration elements list.

PWM_X_GENA_ACTCMPBD : Action for Comparator B Down
bits : 10 - 21 (12 bit)

Enumeration:

0x0 : PWM_X_GENA_ACTCMPBD_NONE

Do nothing

0x1 : PWM_X_GENA_ACTCMPBD_INV

Invert pwmA

0x2 : PWM_X_GENA_ACTCMPBD_ZERO

Drive pwmA Low

0x3 : PWM_X_GENA_ACTCMPBD_ONE

Drive pwmA High

End of enumeration elements list.


0_GENB

PWM0 Generator B Control
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

0_GENB 0_GENB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_GENB_ACTZERO PWM_X_GENB_ACTLOAD PWM_X_GENB_ACTCMPAU PWM_X_GENB_ACTCMPAD PWM_X_GENB_ACTCMPBU PWM_X_GENB_ACTCMPBD

PWM_X_GENB_ACTZERO : Action for Counter=0
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : PWM_X_GENB_ACTZERO_NONE

Do nothing

0x1 : PWM_X_GENB_ACTZERO_INV

Invert pwmB

0x2 : PWM_X_GENB_ACTZERO_ZERO

Drive pwmB Low

0x3 : PWM_X_GENB_ACTZERO_ONE

Drive pwmB High

End of enumeration elements list.

PWM_X_GENB_ACTLOAD : Action for Counter=LOAD
bits : 2 - 5 (4 bit)

Enumeration:

0x0 : PWM_X_GENB_ACTLOAD_NONE

Do nothing

0x1 : PWM_X_GENB_ACTLOAD_INV

Invert pwmB

0x2 : PWM_X_GENB_ACTLOAD_ZERO

Drive pwmB Low

0x3 : PWM_X_GENB_ACTLOAD_ONE

Drive pwmB High

End of enumeration elements list.

PWM_X_GENB_ACTCMPAU : Action for Comparator A Up
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : PWM_X_GENB_ACTCMPAU_NONE

Do nothing

0x1 : PWM_X_GENB_ACTCMPAU_INV

Invert pwmB

0x2 : PWM_X_GENB_ACTCMPAU_ZERO

Drive pwmB Low

0x3 : PWM_X_GENB_ACTCMPAU_ONE

Drive pwmB High

End of enumeration elements list.

PWM_X_GENB_ACTCMPAD : Action for Comparator A Down
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : PWM_X_GENB_ACTCMPAD_NONE

Do nothing

0x1 : PWM_X_GENB_ACTCMPAD_INV

Invert pwmB

0x2 : PWM_X_GENB_ACTCMPAD_ZERO

Drive pwmB Low

0x3 : PWM_X_GENB_ACTCMPAD_ONE

Drive pwmB High

End of enumeration elements list.

PWM_X_GENB_ACTCMPBU : Action for Comparator B Up
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : PWM_X_GENB_ACTCMPBU_NONE

Do nothing

0x1 : PWM_X_GENB_ACTCMPBU_INV

Invert pwmB

0x2 : PWM_X_GENB_ACTCMPBU_ZERO

Drive pwmB Low

0x3 : PWM_X_GENB_ACTCMPBU_ONE

Drive pwmB High

End of enumeration elements list.

PWM_X_GENB_ACTCMPBD : Action for Comparator B Down
bits : 10 - 21 (12 bit)

Enumeration:

0x0 : PWM_X_GENB_ACTCMPBD_NONE

Do nothing

0x1 : PWM_X_GENB_ACTCMPBD_INV

Invert pwmB

0x2 : PWM_X_GENB_ACTCMPBD_ZERO

Drive pwmB Low

0x3 : PWM_X_GENB_ACTCMPBD_ONE

Drive pwmB High

End of enumeration elements list.


_0_GENB

PWM0 Generator B Control
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_0_GENB _0_GENB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_GENB_ACTZERO PWM_X_GENB_ACTLOAD PWM_X_GENB_ACTCMPAU PWM_X_GENB_ACTCMPAD PWM_X_GENB_ACTCMPBU PWM_X_GENB_ACTCMPBD

PWM_X_GENB_ACTZERO : Action for Counter=0
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : PWM_X_GENB_ACTZERO_NONE

Do nothing

0x1 : PWM_X_GENB_ACTZERO_INV

Invert pwmB

0x2 : PWM_X_GENB_ACTZERO_ZERO

Drive pwmB Low

0x3 : PWM_X_GENB_ACTZERO_ONE

Drive pwmB High

End of enumeration elements list.

PWM_X_GENB_ACTLOAD : Action for Counter=LOAD
bits : 2 - 5 (4 bit)

Enumeration:

0x0 : PWM_X_GENB_ACTLOAD_NONE

Do nothing

0x1 : PWM_X_GENB_ACTLOAD_INV

Invert pwmB

0x2 : PWM_X_GENB_ACTLOAD_ZERO

Drive pwmB Low

0x3 : PWM_X_GENB_ACTLOAD_ONE

Drive pwmB High

End of enumeration elements list.

PWM_X_GENB_ACTCMPAU : Action for Comparator A Up
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : PWM_X_GENB_ACTCMPAU_NONE

Do nothing

0x1 : PWM_X_GENB_ACTCMPAU_INV

Invert pwmB

0x2 : PWM_X_GENB_ACTCMPAU_ZERO

Drive pwmB Low

0x3 : PWM_X_GENB_ACTCMPAU_ONE

Drive pwmB High

End of enumeration elements list.

PWM_X_GENB_ACTCMPAD : Action for Comparator A Down
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : PWM_X_GENB_ACTCMPAD_NONE

Do nothing

0x1 : PWM_X_GENB_ACTCMPAD_INV

Invert pwmB

0x2 : PWM_X_GENB_ACTCMPAD_ZERO

Drive pwmB Low

0x3 : PWM_X_GENB_ACTCMPAD_ONE

Drive pwmB High

End of enumeration elements list.

PWM_X_GENB_ACTCMPBU : Action for Comparator B Up
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : PWM_X_GENB_ACTCMPBU_NONE

Do nothing

0x1 : PWM_X_GENB_ACTCMPBU_INV

Invert pwmB

0x2 : PWM_X_GENB_ACTCMPBU_ZERO

Drive pwmB Low

0x3 : PWM_X_GENB_ACTCMPBU_ONE

Drive pwmB High

End of enumeration elements list.

PWM_X_GENB_ACTCMPBD : Action for Comparator B Down
bits : 10 - 21 (12 bit)

Enumeration:

0x0 : PWM_X_GENB_ACTCMPBD_NONE

Do nothing

0x1 : PWM_X_GENB_ACTCMPBD_INV

Invert pwmB

0x2 : PWM_X_GENB_ACTCMPBD_ZERO

Drive pwmB Low

0x3 : PWM_X_GENB_ACTCMPBD_ONE

Drive pwmB High

End of enumeration elements list.


0_DBCTL

PWM0 Dead-Band Control
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

0_DBCTL 0_DBCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_DBCTL_ENABLE

PWM_X_DBCTL_ENABLE : Dead-Band Generator Enable
bits : 0 - 0 (1 bit)


_0_DBCTL

PWM0 Dead-Band Control
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_0_DBCTL _0_DBCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_DBCTL_ENABLE

PWM_X_DBCTL_ENABLE : Dead-Band Generator Enable
bits : 0 - 0 (1 bit)


0_DBRISE

PWM0 Dead-Band Rising-Edge Delay
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

0_DBRISE 0_DBRISE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_DBRISE_DELAY

PWM_X_DBRISE_DELAY : Dead-Band Rise Delay
bits : 0 - 11 (12 bit)


_0_DBRISE

PWM0 Dead-Band Rising-Edge Delay
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_0_DBRISE _0_DBRISE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_DBRISE_DELAY

PWM_X_DBRISE_DELAY : Dead-Band Rise Delay
bits : 0 - 11 (12 bit)


0_DBFALL

PWM0 Dead-Band Falling-Edge-Delay
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

0_DBFALL 0_DBFALL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_DBFALL_DELAY

PWM_X_DBFALL_DELAY : Dead-Band Fall Delay
bits : 0 - 11 (12 bit)


_0_DBFALL

PWM0 Dead-Band Falling-Edge-Delay
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_0_DBFALL _0_DBFALL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_X_DBFALL_DELAY

PWM_X_DBFALL_DELAY : Dead-Band Fall Delay
bits : 0 - 11 (12 bit)


PWM0ENABLE

PWM Output Enable
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0ENABLE PWM0ENABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_ENABLE_PWM0EN PWM_ENABLE_PWM1EN PWM_ENABLE_PWM2EN PWM_ENABLE_PWM3EN PWM_ENABLE_PWM4EN PWM_ENABLE_PWM5EN

PWM_ENABLE_PWM0EN : PWM0 Output Enable
bits : 0 - 0 (1 bit)

PWM_ENABLE_PWM1EN : PWM1 Output Enable
bits : 1 - 2 (2 bit)

PWM_ENABLE_PWM2EN : PWM2 Output Enable
bits : 2 - 4 (3 bit)

PWM_ENABLE_PWM3EN : PWM3 Output Enable
bits : 3 - 6 (4 bit)

PWM_ENABLE_PWM4EN : PWM4 Output Enable
bits : 4 - 8 (5 bit)

PWM_ENABLE_PWM5EN : PWM5 Output Enable
bits : 5 - 10 (6 bit)


ENABLE

PWM Output Enable
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENABLE ENABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_ENABLE_PWM0EN PWM_ENABLE_PWM1EN PWM_ENABLE_PWM2EN PWM_ENABLE_PWM3EN PWM_ENABLE_PWM4EN PWM_ENABLE_PWM5EN

PWM_ENABLE_PWM0EN : PWM0 Output Enable
bits : 0 - 0 (1 bit)

PWM_ENABLE_PWM1EN : PWM1 Output Enable
bits : 1 - 2 (2 bit)

PWM_ENABLE_PWM2EN : PWM2 Output Enable
bits : 2 - 4 (3 bit)

PWM_ENABLE_PWM3EN : PWM3 Output Enable
bits : 3 - 6 (4 bit)

PWM_ENABLE_PWM4EN : PWM4 Output Enable
bits : 4 - 8 (5 bit)

PWM_ENABLE_PWM5EN : PWM5 Output Enable
bits : 5 - 10 (6 bit)


1_CTL

PWM1 Control
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

1_CTL 1_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_1_CTL

PWM1 Control
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_1_CTL _1_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1_INTEN

PWM1 Interrupt and Trigger Enable
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

1_INTEN 1_INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_1_INTEN

PWM1 Interrupt and Trigger Enable
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_1_INTEN _1_INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1_RIS

PWM1 Raw Interrupt Status
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

1_RIS 1_RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_1_RIS

PWM1 Raw Interrupt Status
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_1_RIS _1_RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1_ISC

PWM1 Interrupt Status and Clear
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

1_ISC 1_ISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_1_ISC

PWM1 Interrupt Status and Clear
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_1_ISC _1_ISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1_LOAD

PWM1 Load
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

1_LOAD 1_LOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_1_LOAD

PWM1 Load
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_1_LOAD _1_LOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1_COUNT

PWM1 Counter
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

1_COUNT 1_COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_1_COUNT

PWM1 Counter
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_1_COUNT _1_COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1_CMPA

PWM1 Compare A
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

1_CMPA 1_CMPA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_1_CMPA

PWM1 Compare A
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_1_CMPA _1_CMPA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1_CMPB

PWM1 Compare B
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

1_CMPB 1_CMPB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_1_CMPB

PWM1 Compare B
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_1_CMPB _1_CMPB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1_GENA

PWM1 Generator A Control
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

1_GENA 1_GENA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_1_GENA

PWM1 Generator A Control
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_1_GENA _1_GENA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1_GENB

PWM1 Generator B Control
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

1_GENB 1_GENB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_1_GENB

PWM1 Generator B Control
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_1_GENB _1_GENB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1_DBCTL

PWM1 Dead-Band Control
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

1_DBCTL 1_DBCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_1_DBCTL

PWM1 Dead-Band Control
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_1_DBCTL _1_DBCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1_DBRISE

PWM1 Dead-Band Rising-Edge Delay
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

1_DBRISE 1_DBRISE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_1_DBRISE

PWM1 Dead-Band Rising-Edge Delay
address_offset : 0xAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_1_DBRISE _1_DBRISE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1_DBFALL

PWM1 Dead-Band Falling-Edge-Delay
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

1_DBFALL 1_DBFALL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_1_DBFALL

PWM1 Dead-Band Falling-Edge-Delay
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_1_DBFALL _1_DBFALL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM0INVERT

PWM Output Inversion
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM0INVERT PWM0INVERT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_INVERT_PWM0INV PWM_INVERT_PWM1INV PWM_INVERT_PWM2INV PWM_INVERT_PWM3INV PWM_INVERT_PWM4INV PWM_INVERT_PWM5INV

PWM_INVERT_PWM0INV : Invert PWM0 Signal
bits : 0 - 0 (1 bit)

PWM_INVERT_PWM1INV : Invert PWM1 Signal
bits : 1 - 2 (2 bit)

PWM_INVERT_PWM2INV : Invert PWM2 Signal
bits : 2 - 4 (3 bit)

PWM_INVERT_PWM3INV : Invert PWM3 Signal
bits : 3 - 6 (4 bit)

PWM_INVERT_PWM4INV : Invert PWM4 Signal
bits : 4 - 8 (5 bit)

PWM_INVERT_PWM5INV : Invert PWM5 Signal
bits : 5 - 10 (6 bit)


INVERT

PWM Output Inversion
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INVERT INVERT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_INVERT_PWM0INV PWM_INVERT_PWM1INV PWM_INVERT_PWM2INV PWM_INVERT_PWM3INV PWM_INVERT_PWM4INV PWM_INVERT_PWM5INV

PWM_INVERT_PWM0INV : Invert PWM0 Signal
bits : 0 - 0 (1 bit)

PWM_INVERT_PWM1INV : Invert PWM1 Signal
bits : 1 - 2 (2 bit)

PWM_INVERT_PWM2INV : Invert PWM2 Signal
bits : 2 - 4 (3 bit)

PWM_INVERT_PWM3INV : Invert PWM3 Signal
bits : 3 - 6 (4 bit)

PWM_INVERT_PWM4INV : Invert PWM4 Signal
bits : 4 - 8 (5 bit)

PWM_INVERT_PWM5INV : Invert PWM5 Signal
bits : 5 - 10 (6 bit)


2_CTL

PWM2 Control
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

2_CTL 2_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_2_CTL

PWM2 Control
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_2_CTL _2_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

2_INTEN

PWM2 Interrupt and Trigger Enable
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

2_INTEN 2_INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_2_INTEN

PWM2 Interrupt and Trigger Enable
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_2_INTEN _2_INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

2_RIS

PWM2 Raw Interrupt Status
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

2_RIS 2_RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_2_RIS

PWM2 Raw Interrupt Status
address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_2_RIS _2_RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

2_ISC

PWM2 Interrupt Status and Clear
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

2_ISC 2_ISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_2_ISC

PWM2 Interrupt Status and Clear
address_offset : 0xCC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_2_ISC _2_ISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

2_LOAD

PWM2 Load
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

2_LOAD 2_LOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_2_LOAD

PWM2 Load
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_2_LOAD _2_LOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

2_COUNT

PWM2 Counter
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

2_COUNT 2_COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_2_COUNT

PWM2 Counter
address_offset : 0xD4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_2_COUNT _2_COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

2_CMPA

PWM2 Compare A
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

2_CMPA 2_CMPA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_2_CMPA

PWM2 Compare A
address_offset : 0xD8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_2_CMPA _2_CMPA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

2_CMPB

PWM2 Compare B
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

2_CMPB 2_CMPB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_2_CMPB

PWM2 Compare B
address_offset : 0xDC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_2_CMPB _2_CMPB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

2_GENA

PWM2 Generator A Control
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

2_GENA 2_GENA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_2_GENA

PWM2 Generator A Control
address_offset : 0xE0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_2_GENA _2_GENA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

2_GENB

PWM2 Generator B Control
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

2_GENB 2_GENB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_2_GENB

PWM2 Generator B Control
address_offset : 0xE4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_2_GENB _2_GENB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

2_DBCTL

PWM2 Dead-Band Control
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

2_DBCTL 2_DBCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_2_DBCTL

PWM2 Dead-Band Control
address_offset : 0xE8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_2_DBCTL _2_DBCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

2_DBRISE

PWM2 Dead-Band Rising-Edge Delay
address_offset : 0xEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

2_DBRISE 2_DBRISE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_2_DBRISE

PWM2 Dead-Band Rising-Edge Delay
address_offset : 0xEC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_2_DBRISE _2_DBRISE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

2_DBFALL

PWM2 Dead-Band Falling-Edge-Delay
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

2_DBFALL 2_DBFALL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_2_DBFALL

PWM2 Dead-Band Falling-Edge-Delay
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

_2_DBFALL _2_DBFALL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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