Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
ADC Active Sample Sequencer
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_ACTSS_ASEN0 : ADC SS0 Enable
bits : 0 - 0 (1 bit)
ADC_ACTSS_ASEN1 : ADC SS1 Enable
bits : 1 - 2 (2 bit)
ADC_ACTSS_ASEN2 : ADC SS2 Enable
bits : 2 - 4 (3 bit)
ADC_ACTSS_ASEN3 : ADC SS3 Enable
bits : 3 - 6 (4 bit)
ADC Active Sample Sequencer
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_ACTSS_ASEN0 : ADC SS0 Enable
bits : 0 - 0 (1 bit)
ADC_ACTSS_ASEN1 : ADC SS1 Enable
bits : 1 - 2 (2 bit)
ADC_ACTSS_ASEN2 : ADC SS2 Enable
bits : 2 - 4 (3 bit)
ADC_ACTSS_ASEN3 : ADC SS3 Enable
bits : 3 - 6 (4 bit)
ADC Overflow Status
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_OSTAT_OV0 : SS0 FIFO Overflow
bits : 0 - 0 (1 bit)
ADC_OSTAT_OV1 : SS1 FIFO Overflow
bits : 1 - 2 (2 bit)
ADC_OSTAT_OV2 : SS2 FIFO Overflow
bits : 2 - 4 (3 bit)
ADC_OSTAT_OV3 : SS3 FIFO Overflow
bits : 3 - 6 (4 bit)
ADC Overflow Status
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_OSTAT_OV0 : SS0 FIFO Overflow
bits : 0 - 0 (1 bit)
ADC_OSTAT_OV1 : SS1 FIFO Overflow
bits : 1 - 2 (2 bit)
ADC_OSTAT_OV2 : SS2 FIFO Overflow
bits : 2 - 4 (3 bit)
ADC_OSTAT_OV3 : SS3 FIFO Overflow
bits : 3 - 6 (4 bit)
ADC Event Multiplexer Select
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_EMUX_EM0 : SS0 Trigger Select
bits : 0 - 3 (4 bit)
Enumeration:
0x0 : ADC_EMUX_EM0_PROCESSOR
Processor (default)
0x4 : ADC_EMUX_EM0_EXTERNAL
External (GPIO PB4)
0x5 : ADC_EMUX_EM0_TIMER
Timer
0x6 : ADC_EMUX_EM0_PWM0
PWM0
0x7 : ADC_EMUX_EM0_PWM1
PWM1
0x8 : ADC_EMUX_EM0_PWM2
PWM2
0xf : ADC_EMUX_EM0_ALWAYS
Always (continuously sample)
End of enumeration elements list.
ADC_EMUX_EM1 : SS1 Trigger Select
bits : 4 - 11 (8 bit)
Enumeration:
0x0 : ADC_EMUX_EM1_PROCESSOR
Processor (default)
0x4 : ADC_EMUX_EM1_EXTERNAL
External (GPIO PB4)
0x5 : ADC_EMUX_EM1_TIMER
Timer
0x6 : ADC_EMUX_EM1_PWM0
PWM0
0x7 : ADC_EMUX_EM1_PWM1
PWM1
0x8 : ADC_EMUX_EM1_PWM2
PWM2
0xf : ADC_EMUX_EM1_ALWAYS
Always (continuously sample)
End of enumeration elements list.
ADC_EMUX_EM2 : SS2 Trigger Select
bits : 8 - 19 (12 bit)
Enumeration:
0x0 : ADC_EMUX_EM2_PROCESSOR
Processor (default)
0x4 : ADC_EMUX_EM2_EXTERNAL
External (GPIO PB4)
0x5 : ADC_EMUX_EM2_TIMER
Timer
0x6 : ADC_EMUX_EM2_PWM0
PWM0
0x7 : ADC_EMUX_EM2_PWM1
PWM1
0x8 : ADC_EMUX_EM2_PWM2
PWM2
0xf : ADC_EMUX_EM2_ALWAYS
Always (continuously sample)
End of enumeration elements list.
ADC_EMUX_EM3 : SS3 Trigger Select
bits : 12 - 27 (16 bit)
Enumeration:
0x0 : ADC_EMUX_EM3_PROCESSOR
Processor (default)
0x4 : ADC_EMUX_EM3_EXTERNAL
External (GPIO PB4)
0x5 : ADC_EMUX_EM3_TIMER
Timer
0x6 : ADC_EMUX_EM3_PWM0
PWM0
0x7 : ADC_EMUX_EM3_PWM1
PWM1
0x8 : ADC_EMUX_EM3_PWM2
PWM2
0xf : ADC_EMUX_EM3_ALWAYS
Always (continuously sample)
End of enumeration elements list.
ADC Event Multiplexer Select
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_EMUX_EM0 : SS0 Trigger Select
bits : 0 - 3 (4 bit)
Enumeration:
0x0 : ADC_EMUX_EM0_PROCESSOR
Processor (default)
0x4 : ADC_EMUX_EM0_EXTERNAL
External (GPIO PB4)
0x5 : ADC_EMUX_EM0_TIMER
Timer
0x6 : ADC_EMUX_EM0_PWM0
PWM0
0x7 : ADC_EMUX_EM0_PWM1
PWM1
0x8 : ADC_EMUX_EM0_PWM2
PWM2
0xf : ADC_EMUX_EM0_ALWAYS
Always (continuously sample)
End of enumeration elements list.
ADC_EMUX_EM1 : SS1 Trigger Select
bits : 4 - 11 (8 bit)
Enumeration:
0x0 : ADC_EMUX_EM1_PROCESSOR
Processor (default)
0x4 : ADC_EMUX_EM1_EXTERNAL
External (GPIO PB4)
0x5 : ADC_EMUX_EM1_TIMER
Timer
0x6 : ADC_EMUX_EM1_PWM0
PWM0
0x7 : ADC_EMUX_EM1_PWM1
PWM1
0x8 : ADC_EMUX_EM1_PWM2
PWM2
0xf : ADC_EMUX_EM1_ALWAYS
Always (continuously sample)
End of enumeration elements list.
ADC_EMUX_EM2 : SS2 Trigger Select
bits : 8 - 19 (12 bit)
Enumeration:
0x0 : ADC_EMUX_EM2_PROCESSOR
Processor (default)
0x4 : ADC_EMUX_EM2_EXTERNAL
External (GPIO PB4)
0x5 : ADC_EMUX_EM2_TIMER
Timer
0x6 : ADC_EMUX_EM2_PWM0
PWM0
0x7 : ADC_EMUX_EM2_PWM1
PWM1
0x8 : ADC_EMUX_EM2_PWM2
PWM2
0xf : ADC_EMUX_EM2_ALWAYS
Always (continuously sample)
End of enumeration elements list.
ADC_EMUX_EM3 : SS3 Trigger Select
bits : 12 - 27 (16 bit)
Enumeration:
0x0 : ADC_EMUX_EM3_PROCESSOR
Processor (default)
0x4 : ADC_EMUX_EM3_EXTERNAL
External (GPIO PB4)
0x5 : ADC_EMUX_EM3_TIMER
Timer
0x6 : ADC_EMUX_EM3_PWM0
PWM0
0x7 : ADC_EMUX_EM3_PWM1
PWM1
0x8 : ADC_EMUX_EM3_PWM2
PWM2
0xf : ADC_EMUX_EM3_ALWAYS
Always (continuously sample)
End of enumeration elements list.
ADC Underflow Status
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_USTAT_UV0 : SS0 FIFO Underflow
bits : 0 - 0 (1 bit)
ADC_USTAT_UV1 : SS1 FIFO Underflow
bits : 1 - 2 (2 bit)
ADC_USTAT_UV2 : SS2 FIFO Underflow
bits : 2 - 4 (3 bit)
ADC_USTAT_UV3 : SS3 FIFO Underflow
bits : 3 - 6 (4 bit)
ADC Underflow Status
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_USTAT_UV0 : SS0 FIFO Underflow
bits : 0 - 0 (1 bit)
ADC_USTAT_UV1 : SS1 FIFO Underflow
bits : 1 - 2 (2 bit)
ADC_USTAT_UV2 : SS2 FIFO Underflow
bits : 2 - 4 (3 bit)
ADC_USTAT_UV3 : SS3 FIFO Underflow
bits : 3 - 6 (4 bit)
ADC Sample Sequencer Priority
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSPRI_SS0 : SS0 Priority
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : ADC_SSPRI_SS0_1ST
First priority
0x1 : ADC_SSPRI_SS0_2ND
Second priority
0x2 : ADC_SSPRI_SS0_3RD
Third priority
0x3 : ADC_SSPRI_SS0_4TH
Fourth priority
End of enumeration elements list.
ADC_SSPRI_SS1 : SS1 Priority
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : ADC_SSPRI_SS1_1ST
First priority
0x1 : ADC_SSPRI_SS1_2ND
Second priority
0x2 : ADC_SSPRI_SS1_3RD
Third priority
0x3 : ADC_SSPRI_SS1_4TH
Fourth priority
End of enumeration elements list.
ADC_SSPRI_SS2 : SS2 Priority
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : ADC_SSPRI_SS2_1ST
First priority
0x1 : ADC_SSPRI_SS2_2ND
Second priority
0x2 : ADC_SSPRI_SS2_3RD
Third priority
0x3 : ADC_SSPRI_SS2_4TH
Fourth priority
End of enumeration elements list.
ADC_SSPRI_SS3 : SS3 Priority
bits : 12 - 25 (14 bit)
Enumeration:
0x0 : ADC_SSPRI_SS3_1ST
First priority
0x1 : ADC_SSPRI_SS3_2ND
Second priority
0x2 : ADC_SSPRI_SS3_3RD
Third priority
0x3 : ADC_SSPRI_SS3_4TH
Fourth priority
End of enumeration elements list.
ADC Sample Sequencer Priority
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSPRI_SS0 : SS0 Priority
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : ADC_SSPRI_SS0_1ST
First priority
0x1 : ADC_SSPRI_SS0_2ND
Second priority
0x2 : ADC_SSPRI_SS0_3RD
Third priority
0x3 : ADC_SSPRI_SS0_4TH
Fourth priority
End of enumeration elements list.
ADC_SSPRI_SS1 : SS1 Priority
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : ADC_SSPRI_SS1_1ST
First priority
0x1 : ADC_SSPRI_SS1_2ND
Second priority
0x2 : ADC_SSPRI_SS1_3RD
Third priority
0x3 : ADC_SSPRI_SS1_4TH
Fourth priority
End of enumeration elements list.
ADC_SSPRI_SS2 : SS2 Priority
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : ADC_SSPRI_SS2_1ST
First priority
0x1 : ADC_SSPRI_SS2_2ND
Second priority
0x2 : ADC_SSPRI_SS2_3RD
Third priority
0x3 : ADC_SSPRI_SS2_4TH
Fourth priority
End of enumeration elements list.
ADC_SSPRI_SS3 : SS3 Priority
bits : 12 - 25 (14 bit)
Enumeration:
0x0 : ADC_SSPRI_SS3_1ST
First priority
0x1 : ADC_SSPRI_SS3_2ND
Second priority
0x2 : ADC_SSPRI_SS3_3RD
Third priority
0x3 : ADC_SSPRI_SS3_4TH
Fourth priority
End of enumeration elements list.
ADC Processor Sample Sequence Initiate
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_PSSI_SS0 : SS0 Initiate
bits : 0 - 0 (1 bit)
ADC_PSSI_SS1 : SS1 Initiate
bits : 1 - 2 (2 bit)
ADC_PSSI_SS2 : SS2 Initiate
bits : 2 - 4 (3 bit)
ADC_PSSI_SS3 : SS3 Initiate
bits : 3 - 6 (4 bit)
ADC Processor Sample Sequence Initiate
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_PSSI_SS0 : SS0 Initiate
bits : 0 - 0 (1 bit)
ADC_PSSI_SS1 : SS1 Initiate
bits : 1 - 2 (2 bit)
ADC_PSSI_SS2 : SS2 Initiate
bits : 2 - 4 (3 bit)
ADC_PSSI_SS3 : SS3 Initiate
bits : 3 - 6 (4 bit)
ADC Sample Averaging Control
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SAC_AVG : Hardware Averaging Control
bits : 0 - 2 (3 bit)
Enumeration:
0x0 : ADC_SAC_AVG_OFF
No hardware oversampling
0x1 : ADC_SAC_AVG_2X
2x hardware oversampling
0x2 : ADC_SAC_AVG_4X
4x hardware oversampling
0x3 : ADC_SAC_AVG_8X
8x hardware oversampling
0x4 : ADC_SAC_AVG_16X
16x hardware oversampling
0x5 : ADC_SAC_AVG_32X
32x hardware oversampling
0x6 : ADC_SAC_AVG_64X
64x hardware oversampling
End of enumeration elements list.
ADC Sample Averaging Control
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SAC_AVG : Hardware Averaging Control
bits : 0 - 2 (3 bit)
Enumeration:
0x0 : ADC_SAC_AVG_OFF
No hardware oversampling
0x1 : ADC_SAC_AVG_2X
2x hardware oversampling
0x2 : ADC_SAC_AVG_4X
4x hardware oversampling
0x3 : ADC_SAC_AVG_8X
8x hardware oversampling
0x4 : ADC_SAC_AVG_16X
16x hardware oversampling
0x5 : ADC_SAC_AVG_32X
32x hardware oversampling
0x6 : ADC_SAC_AVG_64X
64x hardware oversampling
End of enumeration elements list.
ADC Raw Interrupt Status
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_RIS_INR0 : SS0 Raw Interrupt Status
bits : 0 - 0 (1 bit)
ADC_RIS_INR1 : SS1 Raw Interrupt Status
bits : 1 - 2 (2 bit)
ADC_RIS_INR2 : SS2 Raw Interrupt Status
bits : 2 - 4 (3 bit)
ADC_RIS_INR3 : SS3 Raw Interrupt Status
bits : 3 - 6 (4 bit)
ADC Raw Interrupt Status
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_RIS_INR0 : SS0 Raw Interrupt Status
bits : 0 - 0 (1 bit)
ADC_RIS_INR1 : SS1 Raw Interrupt Status
bits : 1 - 2 (2 bit)
ADC_RIS_INR2 : SS2 Raw Interrupt Status
bits : 2 - 4 (3 bit)
ADC_RIS_INR3 : SS3 Raw Interrupt Status
bits : 3 - 6 (4 bit)
ADC Sample Sequence Input Multiplexer Select 0
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSMUX0_MUX0 : 1st Sample Input Select
bits : 0 - 1 (2 bit)
ADC_SSMUX0_MUX1 : 2nd Sample Input Select
bits : 4 - 9 (6 bit)
ADC_SSMUX0_MUX2 : 3rd Sample Input Select
bits : 8 - 17 (10 bit)
ADC_SSMUX0_MUX3 : 4th Sample Input Select
bits : 12 - 25 (14 bit)
ADC_SSMUX0_MUX4 : 5th Sample Input Select
bits : 16 - 33 (18 bit)
ADC_SSMUX0_MUX5 : 6th Sample Input Select
bits : 20 - 41 (22 bit)
ADC_SSMUX0_MUX6 : 7th Sample Input Select
bits : 24 - 49 (26 bit)
ADC_SSMUX0_MUX7 : 8th Sample Input Select
bits : 28 - 57 (30 bit)
ADC Sample Sequence Input Multiplexer Select 0
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSMUX0_MUX0 : 1st Sample Input Select
bits : 0 - 1 (2 bit)
ADC_SSMUX0_MUX1 : 2nd Sample Input Select
bits : 4 - 9 (6 bit)
ADC_SSMUX0_MUX2 : 3rd Sample Input Select
bits : 8 - 17 (10 bit)
ADC_SSMUX0_MUX3 : 4th Sample Input Select
bits : 12 - 25 (14 bit)
ADC_SSMUX0_MUX4 : 5th Sample Input Select
bits : 16 - 33 (18 bit)
ADC_SSMUX0_MUX5 : 6th Sample Input Select
bits : 20 - 41 (22 bit)
ADC_SSMUX0_MUX6 : 7th Sample Input Select
bits : 24 - 49 (26 bit)
ADC_SSMUX0_MUX7 : 8th Sample Input Select
bits : 28 - 57 (30 bit)
ADC Sample Sequence Control 0
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSCTL0_D0 : 1st Sample Diff Input Select
bits : 0 - 0 (1 bit)
ADC_SSCTL0_END0 : 1st Sample is End of Sequence
bits : 1 - 2 (2 bit)
ADC_SSCTL0_IE0 : 1st Sample Interrupt Enable
bits : 2 - 4 (3 bit)
ADC_SSCTL0_TS0 : 1st Sample Temp Sensor Select
bits : 3 - 6 (4 bit)
ADC_SSCTL0_D1 : 2nd Sample Diff Input Select
bits : 4 - 8 (5 bit)
ADC_SSCTL0_END1 : 2nd Sample is End of Sequence
bits : 5 - 10 (6 bit)
ADC_SSCTL0_IE1 : 2nd Sample Interrupt Enable
bits : 6 - 12 (7 bit)
ADC_SSCTL0_TS1 : 2nd Sample Temp Sensor Select
bits : 7 - 14 (8 bit)
ADC_SSCTL0_D2 : 3rd Sample Diff Input Select
bits : 8 - 16 (9 bit)
ADC_SSCTL0_END2 : 3rd Sample is End of Sequence
bits : 9 - 18 (10 bit)
ADC_SSCTL0_IE2 : 3rd Sample Interrupt Enable
bits : 10 - 20 (11 bit)
ADC_SSCTL0_TS2 : 3rd Sample Temp Sensor Select
bits : 11 - 22 (12 bit)
ADC_SSCTL0_D3 : 4th Sample Diff Input Select
bits : 12 - 24 (13 bit)
ADC_SSCTL0_END3 : 4th Sample is End of Sequence
bits : 13 - 26 (14 bit)
ADC_SSCTL0_IE3 : 4th Sample Interrupt Enable
bits : 14 - 28 (15 bit)
ADC_SSCTL0_TS3 : 4th Sample Temp Sensor Select
bits : 15 - 30 (16 bit)
ADC_SSCTL0_D4 : 5th Sample Diff Input Select
bits : 16 - 32 (17 bit)
ADC_SSCTL0_END4 : 5th Sample is End of Sequence
bits : 17 - 34 (18 bit)
ADC_SSCTL0_IE4 : 5th Sample Interrupt Enable
bits : 18 - 36 (19 bit)
ADC_SSCTL0_TS4 : 5th Sample Temp Sensor Select
bits : 19 - 38 (20 bit)
ADC_SSCTL0_D5 : 6th Sample Diff Input Select
bits : 20 - 40 (21 bit)
ADC_SSCTL0_END5 : 6th Sample is End of Sequence
bits : 21 - 42 (22 bit)
ADC_SSCTL0_IE5 : 6th Sample Interrupt Enable
bits : 22 - 44 (23 bit)
ADC_SSCTL0_TS5 : 6th Sample Temp Sensor Select
bits : 23 - 46 (24 bit)
ADC_SSCTL0_D6 : 7th Sample Diff Input Select
bits : 24 - 48 (25 bit)
ADC_SSCTL0_END6 : 7th Sample is End of Sequence
bits : 25 - 50 (26 bit)
ADC_SSCTL0_IE6 : 7th Sample Interrupt Enable
bits : 26 - 52 (27 bit)
ADC_SSCTL0_TS6 : 7th Sample Temp Sensor Select
bits : 27 - 54 (28 bit)
ADC_SSCTL0_D7 : 8th Sample Diff Input Select
bits : 28 - 56 (29 bit)
ADC_SSCTL0_END7 : 8th Sample is End of Sequence
bits : 29 - 58 (30 bit)
ADC_SSCTL0_IE7 : 8th Sample Interrupt Enable
bits : 30 - 60 (31 bit)
ADC_SSCTL0_TS7 : 8th Sample Temp Sensor Select
bits : 31 - 62 (32 bit)
ADC Sample Sequence Control 0
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSCTL0_D0 : 1st Sample Diff Input Select
bits : 0 - 0 (1 bit)
ADC_SSCTL0_END0 : 1st Sample is End of Sequence
bits : 1 - 2 (2 bit)
ADC_SSCTL0_IE0 : 1st Sample Interrupt Enable
bits : 2 - 4 (3 bit)
ADC_SSCTL0_TS0 : 1st Sample Temp Sensor Select
bits : 3 - 6 (4 bit)
ADC_SSCTL0_D1 : 2nd Sample Diff Input Select
bits : 4 - 8 (5 bit)
ADC_SSCTL0_END1 : 2nd Sample is End of Sequence
bits : 5 - 10 (6 bit)
ADC_SSCTL0_IE1 : 2nd Sample Interrupt Enable
bits : 6 - 12 (7 bit)
ADC_SSCTL0_TS1 : 2nd Sample Temp Sensor Select
bits : 7 - 14 (8 bit)
ADC_SSCTL0_D2 : 3rd Sample Diff Input Select
bits : 8 - 16 (9 bit)
ADC_SSCTL0_END2 : 3rd Sample is End of Sequence
bits : 9 - 18 (10 bit)
ADC_SSCTL0_IE2 : 3rd Sample Interrupt Enable
bits : 10 - 20 (11 bit)
ADC_SSCTL0_TS2 : 3rd Sample Temp Sensor Select
bits : 11 - 22 (12 bit)
ADC_SSCTL0_D3 : 4th Sample Diff Input Select
bits : 12 - 24 (13 bit)
ADC_SSCTL0_END3 : 4th Sample is End of Sequence
bits : 13 - 26 (14 bit)
ADC_SSCTL0_IE3 : 4th Sample Interrupt Enable
bits : 14 - 28 (15 bit)
ADC_SSCTL0_TS3 : 4th Sample Temp Sensor Select
bits : 15 - 30 (16 bit)
ADC_SSCTL0_D4 : 5th Sample Diff Input Select
bits : 16 - 32 (17 bit)
ADC_SSCTL0_END4 : 5th Sample is End of Sequence
bits : 17 - 34 (18 bit)
ADC_SSCTL0_IE4 : 5th Sample Interrupt Enable
bits : 18 - 36 (19 bit)
ADC_SSCTL0_TS4 : 5th Sample Temp Sensor Select
bits : 19 - 38 (20 bit)
ADC_SSCTL0_D5 : 6th Sample Diff Input Select
bits : 20 - 40 (21 bit)
ADC_SSCTL0_END5 : 6th Sample is End of Sequence
bits : 21 - 42 (22 bit)
ADC_SSCTL0_IE5 : 6th Sample Interrupt Enable
bits : 22 - 44 (23 bit)
ADC_SSCTL0_TS5 : 6th Sample Temp Sensor Select
bits : 23 - 46 (24 bit)
ADC_SSCTL0_D6 : 7th Sample Diff Input Select
bits : 24 - 48 (25 bit)
ADC_SSCTL0_END6 : 7th Sample is End of Sequence
bits : 25 - 50 (26 bit)
ADC_SSCTL0_IE6 : 7th Sample Interrupt Enable
bits : 26 - 52 (27 bit)
ADC_SSCTL0_TS6 : 7th Sample Temp Sensor Select
bits : 27 - 54 (28 bit)
ADC_SSCTL0_D7 : 8th Sample Diff Input Select
bits : 28 - 56 (29 bit)
ADC_SSCTL0_END7 : 8th Sample is End of Sequence
bits : 29 - 58 (30 bit)
ADC_SSCTL0_IE7 : 8th Sample Interrupt Enable
bits : 30 - 60 (31 bit)
ADC_SSCTL0_TS7 : 8th Sample Temp Sensor Select
bits : 31 - 62 (32 bit)
ADC Sample Sequence Result FIFO 0
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSFIFO0_DATA : Conversion Result Data
bits : 0 - 9 (10 bit)
ADC Sample Sequence Result FIFO 0
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSFIFO0_DATA : Conversion Result Data
bits : 0 - 9 (10 bit)
ADC Sample Sequence FIFO 0 Status
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSFSTAT0_TPTR : FIFO Tail Pointer
bits : 0 - 3 (4 bit)
ADC_SSFSTAT0_HPTR : FIFO Head Pointer
bits : 4 - 11 (8 bit)
ADC_SSFSTAT0_EMPTY : FIFO Empty
bits : 8 - 16 (9 bit)
ADC_SSFSTAT0_FULL : FIFO Full
bits : 12 - 24 (13 bit)
ADC Sample Sequence FIFO 0 Status
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSFSTAT0_TPTR : FIFO Tail Pointer
bits : 0 - 3 (4 bit)
ADC_SSFSTAT0_HPTR : FIFO Head Pointer
bits : 4 - 11 (8 bit)
ADC_SSFSTAT0_EMPTY : FIFO Empty
bits : 8 - 16 (9 bit)
ADC_SSFSTAT0_FULL : FIFO Full
bits : 12 - 24 (13 bit)
ADC Sample Sequence Input Multiplexer Select 1
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSMUX1_MUX0 : 1st Sample Input Select
bits : 0 - 1 (2 bit)
ADC_SSMUX1_MUX1 : 2nd Sample Input Select
bits : 4 - 9 (6 bit)
ADC_SSMUX1_MUX2 : 3rd Sample Input Select
bits : 8 - 17 (10 bit)
ADC_SSMUX1_MUX3 : 4th Sample Input Select
bits : 12 - 25 (14 bit)
ADC Sample Sequence Input Multiplexer Select 1
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSMUX1_MUX0 : 1st Sample Input Select
bits : 0 - 1 (2 bit)
ADC_SSMUX1_MUX1 : 2nd Sample Input Select
bits : 4 - 9 (6 bit)
ADC_SSMUX1_MUX2 : 3rd Sample Input Select
bits : 8 - 17 (10 bit)
ADC_SSMUX1_MUX3 : 4th Sample Input Select
bits : 12 - 25 (14 bit)
ADC Sample Sequence Control 1
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSCTL1_D0 : 1st Sample Diff Input Select
bits : 0 - 0 (1 bit)
ADC_SSCTL1_END0 : 1st Sample is End of Sequence
bits : 1 - 2 (2 bit)
ADC_SSCTL1_IE0 : 1st Sample Interrupt Enable
bits : 2 - 4 (3 bit)
ADC_SSCTL1_TS0 : 1st Sample Temp Sensor Select
bits : 3 - 6 (4 bit)
ADC_SSCTL1_D1 : 2nd Sample Diff Input Select
bits : 4 - 8 (5 bit)
ADC_SSCTL1_END1 : 2nd Sample is End of Sequence
bits : 5 - 10 (6 bit)
ADC_SSCTL1_IE1 : 2nd Sample Interrupt Enable
bits : 6 - 12 (7 bit)
ADC_SSCTL1_TS1 : 2nd Sample Temp Sensor Select
bits : 7 - 14 (8 bit)
ADC_SSCTL1_D2 : 3rd Sample Diff Input Select
bits : 8 - 16 (9 bit)
ADC_SSCTL1_END2 : 3rd Sample is End of Sequence
bits : 9 - 18 (10 bit)
ADC_SSCTL1_IE2 : 3rd Sample Interrupt Enable
bits : 10 - 20 (11 bit)
ADC_SSCTL1_TS2 : 3rd Sample Temp Sensor Select
bits : 11 - 22 (12 bit)
ADC_SSCTL1_D3 : 4th Sample Diff Input Select
bits : 12 - 24 (13 bit)
ADC_SSCTL1_END3 : 4th Sample is End of Sequence
bits : 13 - 26 (14 bit)
ADC_SSCTL1_IE3 : 4th Sample Interrupt Enable
bits : 14 - 28 (15 bit)
ADC_SSCTL1_TS3 : 4th Sample Temp Sensor Select
bits : 15 - 30 (16 bit)
ADC Sample Sequence Control 1
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSCTL1_D0 : 1st Sample Diff Input Select
bits : 0 - 0 (1 bit)
ADC_SSCTL1_END0 : 1st Sample is End of Sequence
bits : 1 - 2 (2 bit)
ADC_SSCTL1_IE0 : 1st Sample Interrupt Enable
bits : 2 - 4 (3 bit)
ADC_SSCTL1_TS0 : 1st Sample Temp Sensor Select
bits : 3 - 6 (4 bit)
ADC_SSCTL1_D1 : 2nd Sample Diff Input Select
bits : 4 - 8 (5 bit)
ADC_SSCTL1_END1 : 2nd Sample is End of Sequence
bits : 5 - 10 (6 bit)
ADC_SSCTL1_IE1 : 2nd Sample Interrupt Enable
bits : 6 - 12 (7 bit)
ADC_SSCTL1_TS1 : 2nd Sample Temp Sensor Select
bits : 7 - 14 (8 bit)
ADC_SSCTL1_D2 : 3rd Sample Diff Input Select
bits : 8 - 16 (9 bit)
ADC_SSCTL1_END2 : 3rd Sample is End of Sequence
bits : 9 - 18 (10 bit)
ADC_SSCTL1_IE2 : 3rd Sample Interrupt Enable
bits : 10 - 20 (11 bit)
ADC_SSCTL1_TS2 : 3rd Sample Temp Sensor Select
bits : 11 - 22 (12 bit)
ADC_SSCTL1_D3 : 4th Sample Diff Input Select
bits : 12 - 24 (13 bit)
ADC_SSCTL1_END3 : 4th Sample is End of Sequence
bits : 13 - 26 (14 bit)
ADC_SSCTL1_IE3 : 4th Sample Interrupt Enable
bits : 14 - 28 (15 bit)
ADC_SSCTL1_TS3 : 4th Sample Temp Sensor Select
bits : 15 - 30 (16 bit)
ADC Sample Sequence Result FIFO 1
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSFIFO1_DATA : Conversion Result Data
bits : 0 - 9 (10 bit)
ADC Sample Sequence Result FIFO 1
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSFIFO1_DATA : Conversion Result Data
bits : 0 - 9 (10 bit)
ADC Sample Sequence FIFO 1 Status
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSFSTAT1_TPTR : FIFO Tail Pointer
bits : 0 - 3 (4 bit)
ADC_SSFSTAT1_HPTR : FIFO Head Pointer
bits : 4 - 11 (8 bit)
ADC_SSFSTAT1_EMPTY : FIFO Empty
bits : 8 - 16 (9 bit)
ADC_SSFSTAT1_FULL : FIFO Full
bits : 12 - 24 (13 bit)
ADC Sample Sequence FIFO 1 Status
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSFSTAT1_TPTR : FIFO Tail Pointer
bits : 0 - 3 (4 bit)
ADC_SSFSTAT1_HPTR : FIFO Head Pointer
bits : 4 - 11 (8 bit)
ADC_SSFSTAT1_EMPTY : FIFO Empty
bits : 8 - 16 (9 bit)
ADC_SSFSTAT1_FULL : FIFO Full
bits : 12 - 24 (13 bit)
ADC Interrupt Mask
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_IM_MASK0 : SS0 Interrupt Mask
bits : 0 - 0 (1 bit)
ADC_IM_MASK1 : SS1 Interrupt Mask
bits : 1 - 2 (2 bit)
ADC_IM_MASK2 : SS2 Interrupt Mask
bits : 2 - 4 (3 bit)
ADC_IM_MASK3 : SS3 Interrupt Mask
bits : 3 - 6 (4 bit)
ADC Interrupt Mask
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_IM_MASK0 : SS0 Interrupt Mask
bits : 0 - 0 (1 bit)
ADC_IM_MASK1 : SS1 Interrupt Mask
bits : 1 - 2 (2 bit)
ADC_IM_MASK2 : SS2 Interrupt Mask
bits : 2 - 4 (3 bit)
ADC_IM_MASK3 : SS3 Interrupt Mask
bits : 3 - 6 (4 bit)
ADC Sample Sequence Input Multiplexer Select 2
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSMUX2_MUX0 : 1st Sample Input Select
bits : 0 - 1 (2 bit)
ADC_SSMUX2_MUX1 : 2nd Sample Input Select
bits : 4 - 9 (6 bit)
ADC_SSMUX2_MUX2 : 3rd Sample Input Select
bits : 8 - 17 (10 bit)
ADC_SSMUX2_MUX3 : 4th Sample Input Select
bits : 12 - 25 (14 bit)
ADC Sample Sequence Input Multiplexer Select 2
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSMUX2_MUX0 : 1st Sample Input Select
bits : 0 - 1 (2 bit)
ADC_SSMUX2_MUX1 : 2nd Sample Input Select
bits : 4 - 9 (6 bit)
ADC_SSMUX2_MUX2 : 3rd Sample Input Select
bits : 8 - 17 (10 bit)
ADC_SSMUX2_MUX3 : 4th Sample Input Select
bits : 12 - 25 (14 bit)
ADC Sample Sequence Control 2
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSCTL2_D0 : 1st Sample Diff Input Select
bits : 0 - 0 (1 bit)
ADC_SSCTL2_END0 : 1st Sample is End of Sequence
bits : 1 - 2 (2 bit)
ADC_SSCTL2_IE0 : 1st Sample Interrupt Enable
bits : 2 - 4 (3 bit)
ADC_SSCTL2_TS0 : 1st Sample Temp Sensor Select
bits : 3 - 6 (4 bit)
ADC_SSCTL2_D1 : 2nd Sample Diff Input Select
bits : 4 - 8 (5 bit)
ADC_SSCTL2_END1 : 2nd Sample is End of Sequence
bits : 5 - 10 (6 bit)
ADC_SSCTL2_IE1 : 2nd Sample Interrupt Enable
bits : 6 - 12 (7 bit)
ADC_SSCTL2_TS1 : 2nd Sample Temp Sensor Select
bits : 7 - 14 (8 bit)
ADC_SSCTL2_D2 : 3rd Sample Diff Input Select
bits : 8 - 16 (9 bit)
ADC_SSCTL2_END2 : 3rd Sample is End of Sequence
bits : 9 - 18 (10 bit)
ADC_SSCTL2_IE2 : 3rd Sample Interrupt Enable
bits : 10 - 20 (11 bit)
ADC_SSCTL2_TS2 : 3rd Sample Temp Sensor Select
bits : 11 - 22 (12 bit)
ADC_SSCTL2_D3 : 4th Sample Diff Input Select
bits : 12 - 24 (13 bit)
ADC_SSCTL2_END3 : 4th Sample is End of Sequence
bits : 13 - 26 (14 bit)
ADC_SSCTL2_IE3 : 4th Sample Interrupt Enable
bits : 14 - 28 (15 bit)
ADC_SSCTL2_TS3 : 4th Sample Temp Sensor Select
bits : 15 - 30 (16 bit)
ADC Sample Sequence Control 2
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSCTL2_D0 : 1st Sample Diff Input Select
bits : 0 - 0 (1 bit)
ADC_SSCTL2_END0 : 1st Sample is End of Sequence
bits : 1 - 2 (2 bit)
ADC_SSCTL2_IE0 : 1st Sample Interrupt Enable
bits : 2 - 4 (3 bit)
ADC_SSCTL2_TS0 : 1st Sample Temp Sensor Select
bits : 3 - 6 (4 bit)
ADC_SSCTL2_D1 : 2nd Sample Diff Input Select
bits : 4 - 8 (5 bit)
ADC_SSCTL2_END1 : 2nd Sample is End of Sequence
bits : 5 - 10 (6 bit)
ADC_SSCTL2_IE1 : 2nd Sample Interrupt Enable
bits : 6 - 12 (7 bit)
ADC_SSCTL2_TS1 : 2nd Sample Temp Sensor Select
bits : 7 - 14 (8 bit)
ADC_SSCTL2_D2 : 3rd Sample Diff Input Select
bits : 8 - 16 (9 bit)
ADC_SSCTL2_END2 : 3rd Sample is End of Sequence
bits : 9 - 18 (10 bit)
ADC_SSCTL2_IE2 : 3rd Sample Interrupt Enable
bits : 10 - 20 (11 bit)
ADC_SSCTL2_TS2 : 3rd Sample Temp Sensor Select
bits : 11 - 22 (12 bit)
ADC_SSCTL2_D3 : 4th Sample Diff Input Select
bits : 12 - 24 (13 bit)
ADC_SSCTL2_END3 : 4th Sample is End of Sequence
bits : 13 - 26 (14 bit)
ADC_SSCTL2_IE3 : 4th Sample Interrupt Enable
bits : 14 - 28 (15 bit)
ADC_SSCTL2_TS3 : 4th Sample Temp Sensor Select
bits : 15 - 30 (16 bit)
ADC Sample Sequence Result FIFO 2
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSFIFO2_DATA : Conversion Result Data
bits : 0 - 9 (10 bit)
ADC Sample Sequence Result FIFO 2
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSFIFO2_DATA : Conversion Result Data
bits : 0 - 9 (10 bit)
ADC Sample Sequence FIFO 2 Status
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSFSTAT2_TPTR : FIFO Tail Pointer
bits : 0 - 3 (4 bit)
ADC_SSFSTAT2_HPTR : FIFO Head Pointer
bits : 4 - 11 (8 bit)
ADC_SSFSTAT2_EMPTY : FIFO Empty
bits : 8 - 16 (9 bit)
ADC_SSFSTAT2_FULL : FIFO Full
bits : 12 - 24 (13 bit)
ADC Sample Sequence FIFO 2 Status
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSFSTAT2_TPTR : FIFO Tail Pointer
bits : 0 - 3 (4 bit)
ADC_SSFSTAT2_HPTR : FIFO Head Pointer
bits : 4 - 11 (8 bit)
ADC_SSFSTAT2_EMPTY : FIFO Empty
bits : 8 - 16 (9 bit)
ADC_SSFSTAT2_FULL : FIFO Full
bits : 12 - 24 (13 bit)
ADC Sample Sequence Input Multiplexer Select 3
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSMUX3_MUX0 : 1st Sample Input Select
bits : 0 - 1 (2 bit)
ADC Sample Sequence Input Multiplexer Select 3
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSMUX3_MUX0 : 1st Sample Input Select
bits : 0 - 1 (2 bit)
ADC Sample Sequence Control 3
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSCTL3_D0 : 1st Sample Diff Input Select
bits : 0 - 0 (1 bit)
ADC_SSCTL3_END0 : 1st Sample is End of Sequence
bits : 1 - 2 (2 bit)
ADC_SSCTL3_IE0 : 1st Sample Interrupt Enable
bits : 2 - 4 (3 bit)
ADC_SSCTL3_TS0 : 1st Sample Temp Sensor Select
bits : 3 - 6 (4 bit)
ADC Sample Sequence Control 3
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSCTL3_D0 : 1st Sample Diff Input Select
bits : 0 - 0 (1 bit)
ADC_SSCTL3_END0 : 1st Sample is End of Sequence
bits : 1 - 2 (2 bit)
ADC_SSCTL3_IE0 : 1st Sample Interrupt Enable
bits : 2 - 4 (3 bit)
ADC_SSCTL3_TS0 : 1st Sample Temp Sensor Select
bits : 3 - 6 (4 bit)
ADC Sample Sequence Result FIFO 3
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSFIFO3_DATA : Conversion Result Data
bits : 0 - 9 (10 bit)
ADC Sample Sequence Result FIFO 3
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSFIFO3_DATA : Conversion Result Data
bits : 0 - 9 (10 bit)
ADC Sample Sequence FIFO 3 Status
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSFSTAT3_TPTR : FIFO Tail Pointer
bits : 0 - 3 (4 bit)
ADC_SSFSTAT3_HPTR : FIFO Head Pointer
bits : 4 - 11 (8 bit)
ADC_SSFSTAT3_EMPTY : FIFO Empty
bits : 8 - 16 (9 bit)
ADC_SSFSTAT3_FULL : FIFO Full
bits : 12 - 24 (13 bit)
ADC Sample Sequence FIFO 3 Status
address_offset : 0xAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_SSFSTAT3_TPTR : FIFO Tail Pointer
bits : 0 - 3 (4 bit)
ADC_SSFSTAT3_HPTR : FIFO Head Pointer
bits : 4 - 11 (8 bit)
ADC_SSFSTAT3_EMPTY : FIFO Empty
bits : 8 - 16 (9 bit)
ADC_SSFSTAT3_FULL : FIFO Full
bits : 12 - 24 (13 bit)
ADC Interrupt Status and Clear
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_ISC_IN0 : SS0 Interrupt Status and Clear
bits : 0 - 0 (1 bit)
ADC_ISC_IN1 : SS1 Interrupt Status and Clear
bits : 1 - 2 (2 bit)
ADC_ISC_IN2 : SS2 Interrupt Status and Clear
bits : 2 - 4 (3 bit)
ADC_ISC_IN3 : SS3 Interrupt Status and Clear
bits : 3 - 6 (4 bit)
ADC Interrupt Status and Clear
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_ISC_IN0 : SS0 Interrupt Status and Clear
bits : 0 - 0 (1 bit)
ADC_ISC_IN1 : SS1 Interrupt Status and Clear
bits : 1 - 2 (2 bit)
ADC_ISC_IN2 : SS2 Interrupt Status and Clear
bits : 2 - 4 (3 bit)
ADC_ISC_IN3 : SS3 Interrupt Status and Clear
bits : 3 - 6 (4 bit)
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