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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ADC0ACTSS

ACTSS

ADC0OSTAT

OSTAT

ADC0EMUX

EMUX

ADC0USTAT

USTAT

ADC0SSPRI

SSPRI

ADC0SPC

SPC

ADC0PSSI

PSSI

ADC0SAC

SAC

ADC0DCISC

DCISC

ADC0CTL

CTL

ADC0RIS

RIS

ADC0SSMUX0

SSMUX0

ADC0SSCTL0

SSCTL0

ADC0SSFIFO0

SSFIFO0

ADC0SSFSTAT0

SSFSTAT0

ADC0SSOP0

SSOP0

ADC0SSDC0

SSDC0

ADC0SSMUX1

SSMUX1

ADC0SSCTL1

SSCTL1

ADC0SSFIFO1

SSFIFO1

ADC0SSFSTAT1

SSFSTAT1

ADC0SSOP1

SSOP1

ADC0SSDC1

SSDC1

ADC0IM

IM

ADC0SSMUX2

SSMUX2

ADC0SSCTL2

SSCTL2

ADC0SSFIFO2

SSFIFO2

ADC0SSFSTAT2

SSFSTAT2

ADC0SSOP2

SSOP2

ADC0SSDC2

SSDC2

ADC0SSMUX3

SSMUX3

ADC0SSCTL3

SSCTL3

ADC0SSFIFO3

SSFIFO3

ADC0SSFSTAT3

SSFSTAT3

ADC0SSOP3

SSOP3

ADC0SSDC3

SSDC3

ADC0ISC

ISC

ADC0DCRIC

DCRIC

ADC0DCCTL0

DCCTL0

ADC0DCCTL1

DCCTL1

ADC0DCCTL2

DCCTL2

ADC0DCCTL3

DCCTL3

ADC0DCCTL4

DCCTL4

ADC0DCCTL5

DCCTL5

ADC0DCCTL6

DCCTL6

ADC0DCCTL7

DCCTL7

ADC0DCCMP0

DCCMP0

ADC0DCCMP1

DCCMP1

ADC0DCCMP2

DCCMP2

ADC0DCCMP3

DCCMP3

ADC0DCCMP4

DCCMP4

ADC0DCCMP5

DCCMP5

ADC0DCCMP6

DCCMP6

ADC0DCCMP7

DCCMP7


ADC0ACTSS

ADC Active Sample Sequencer
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0ACTSS ADC0ACTSS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_ACTSS_ASEN0 ADC_ACTSS_ASEN1 ADC_ACTSS_ASEN2 ADC_ACTSS_ASEN3

ADC_ACTSS_ASEN0 : ADC SS0 Enable
bits : 0 - 0 (1 bit)

ADC_ACTSS_ASEN1 : ADC SS1 Enable
bits : 1 - 2 (2 bit)

ADC_ACTSS_ASEN2 : ADC SS2 Enable
bits : 2 - 4 (3 bit)

ADC_ACTSS_ASEN3 : ADC SS3 Enable
bits : 3 - 6 (4 bit)


ACTSS

ADC Active Sample Sequencer
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACTSS ACTSS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_ACTSS_ASEN0 ADC_ACTSS_ASEN1 ADC_ACTSS_ASEN2 ADC_ACTSS_ASEN3

ADC_ACTSS_ASEN0 : ADC SS0 Enable
bits : 0 - 0 (1 bit)

ADC_ACTSS_ASEN1 : ADC SS1 Enable
bits : 1 - 2 (2 bit)

ADC_ACTSS_ASEN2 : ADC SS2 Enable
bits : 2 - 4 (3 bit)

ADC_ACTSS_ASEN3 : ADC SS3 Enable
bits : 3 - 6 (4 bit)


ADC0OSTAT

ADC Overflow Status
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0OSTAT ADC0OSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_OSTAT_OV0 ADC_OSTAT_OV1 ADC_OSTAT_OV2 ADC_OSTAT_OV3

ADC_OSTAT_OV0 : SS0 FIFO Overflow
bits : 0 - 0 (1 bit)

ADC_OSTAT_OV1 : SS1 FIFO Overflow
bits : 1 - 2 (2 bit)

ADC_OSTAT_OV2 : SS2 FIFO Overflow
bits : 2 - 4 (3 bit)

ADC_OSTAT_OV3 : SS3 FIFO Overflow
bits : 3 - 6 (4 bit)


OSTAT

ADC Overflow Status
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSTAT OSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_OSTAT_OV0 ADC_OSTAT_OV1 ADC_OSTAT_OV2 ADC_OSTAT_OV3

ADC_OSTAT_OV0 : SS0 FIFO Overflow
bits : 0 - 0 (1 bit)

ADC_OSTAT_OV1 : SS1 FIFO Overflow
bits : 1 - 2 (2 bit)

ADC_OSTAT_OV2 : SS2 FIFO Overflow
bits : 2 - 4 (3 bit)

ADC_OSTAT_OV3 : SS3 FIFO Overflow
bits : 3 - 6 (4 bit)


ADC0EMUX

ADC Event Multiplexer Select
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0EMUX ADC0EMUX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_EMUX_EM0 ADC_EMUX_EM1 ADC_EMUX_EM2 ADC_EMUX_EM3

ADC_EMUX_EM0 : SS0 Trigger Select
bits : 0 - 3 (4 bit)

Enumeration:

0x0 : ADC_EMUX_EM0_PROCESSOR

Processor (default)

0x1 : ADC_EMUX_EM0_COMP0

Analog Comparator 0

0x2 : ADC_EMUX_EM0_COMP1

Analog Comparator 1

0x4 : ADC_EMUX_EM0_EXTERNAL

External (GPIO PB4)

0x5 : ADC_EMUX_EM0_TIMER

Timer

0xf : ADC_EMUX_EM0_ALWAYS

Always (continuously sample)

End of enumeration elements list.

ADC_EMUX_EM1 : SS1 Trigger Select
bits : 4 - 11 (8 bit)

Enumeration:

0x0 : ADC_EMUX_EM1_PROCESSOR

Processor (default)

0x1 : ADC_EMUX_EM1_COMP0

Analog Comparator 0

0x2 : ADC_EMUX_EM1_COMP1

Analog Comparator 1

0x4 : ADC_EMUX_EM1_EXTERNAL

External (GPIO PB4)

0x5 : ADC_EMUX_EM1_TIMER

Timer

0xf : ADC_EMUX_EM1_ALWAYS

Always (continuously sample)

End of enumeration elements list.

ADC_EMUX_EM2 : SS2 Trigger Select
bits : 8 - 19 (12 bit)

Enumeration:

0x0 : ADC_EMUX_EM2_PROCESSOR

Processor (default)

0x1 : ADC_EMUX_EM2_COMP0

Analog Comparator 0

0x2 : ADC_EMUX_EM2_COMP1

Analog Comparator 1

0x4 : ADC_EMUX_EM2_EXTERNAL

External (GPIO PB4)

0x5 : ADC_EMUX_EM2_TIMER

Timer

0xf : ADC_EMUX_EM2_ALWAYS

Always (continuously sample)

End of enumeration elements list.

ADC_EMUX_EM3 : SS3 Trigger Select
bits : 12 - 27 (16 bit)

Enumeration:

0x0 : ADC_EMUX_EM3_PROCESSOR

Processor (default)

0x1 : ADC_EMUX_EM3_COMP0

Analog Comparator 0

0x2 : ADC_EMUX_EM3_COMP1

Analog Comparator 1

0x4 : ADC_EMUX_EM3_EXTERNAL

External (GPIO PB4)

0x5 : ADC_EMUX_EM3_TIMER

Timer

0xf : ADC_EMUX_EM3_ALWAYS

Always (continuously sample)

End of enumeration elements list.


EMUX

ADC Event Multiplexer Select
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EMUX EMUX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_EMUX_EM0 ADC_EMUX_EM1 ADC_EMUX_EM2 ADC_EMUX_EM3

ADC_EMUX_EM0 : SS0 Trigger Select
bits : 0 - 3 (4 bit)

Enumeration:

0x0 : ADC_EMUX_EM0_PROCESSOR

Processor (default)

0x1 : ADC_EMUX_EM0_COMP0

Analog Comparator 0

0x2 : ADC_EMUX_EM0_COMP1

Analog Comparator 1

0x4 : ADC_EMUX_EM0_EXTERNAL

External (GPIO PB4)

0x5 : ADC_EMUX_EM0_TIMER

Timer

0xf : ADC_EMUX_EM0_ALWAYS

Always (continuously sample)

End of enumeration elements list.

ADC_EMUX_EM1 : SS1 Trigger Select
bits : 4 - 11 (8 bit)

Enumeration:

0x0 : ADC_EMUX_EM1_PROCESSOR

Processor (default)

0x1 : ADC_EMUX_EM1_COMP0

Analog Comparator 0

0x2 : ADC_EMUX_EM1_COMP1

Analog Comparator 1

0x4 : ADC_EMUX_EM1_EXTERNAL

External (GPIO PB4)

0x5 : ADC_EMUX_EM1_TIMER

Timer

0xf : ADC_EMUX_EM1_ALWAYS

Always (continuously sample)

End of enumeration elements list.

ADC_EMUX_EM2 : SS2 Trigger Select
bits : 8 - 19 (12 bit)

Enumeration:

0x0 : ADC_EMUX_EM2_PROCESSOR

Processor (default)

0x1 : ADC_EMUX_EM2_COMP0

Analog Comparator 0

0x2 : ADC_EMUX_EM2_COMP1

Analog Comparator 1

0x4 : ADC_EMUX_EM2_EXTERNAL

External (GPIO PB4)

0x5 : ADC_EMUX_EM2_TIMER

Timer

0xf : ADC_EMUX_EM2_ALWAYS

Always (continuously sample)

End of enumeration elements list.

ADC_EMUX_EM3 : SS3 Trigger Select
bits : 12 - 27 (16 bit)

Enumeration:

0x0 : ADC_EMUX_EM3_PROCESSOR

Processor (default)

0x1 : ADC_EMUX_EM3_COMP0

Analog Comparator 0

0x2 : ADC_EMUX_EM3_COMP1

Analog Comparator 1

0x4 : ADC_EMUX_EM3_EXTERNAL

External (GPIO PB4)

0x5 : ADC_EMUX_EM3_TIMER

Timer

0xf : ADC_EMUX_EM3_ALWAYS

Always (continuously sample)

End of enumeration elements list.


ADC0USTAT

ADC Underflow Status
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0USTAT ADC0USTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_USTAT_UV0 ADC_USTAT_UV1 ADC_USTAT_UV2 ADC_USTAT_UV3

ADC_USTAT_UV0 : SS0 FIFO Underflow
bits : 0 - 0 (1 bit)

ADC_USTAT_UV1 : SS1 FIFO Underflow
bits : 1 - 2 (2 bit)

ADC_USTAT_UV2 : SS2 FIFO Underflow
bits : 2 - 4 (3 bit)

ADC_USTAT_UV3 : SS3 FIFO Underflow
bits : 3 - 6 (4 bit)


USTAT

ADC Underflow Status
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USTAT USTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_USTAT_UV0 ADC_USTAT_UV1 ADC_USTAT_UV2 ADC_USTAT_UV3

ADC_USTAT_UV0 : SS0 FIFO Underflow
bits : 0 - 0 (1 bit)

ADC_USTAT_UV1 : SS1 FIFO Underflow
bits : 1 - 2 (2 bit)

ADC_USTAT_UV2 : SS2 FIFO Underflow
bits : 2 - 4 (3 bit)

ADC_USTAT_UV3 : SS3 FIFO Underflow
bits : 3 - 6 (4 bit)


ADC0SSPRI

ADC Sample Sequencer Priority
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSPRI ADC0SSPRI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSPRI_SS0 ADC_SSPRI_SS1 ADC_SSPRI_SS2 ADC_SSPRI_SS3

ADC_SSPRI_SS0 : SS0 Priority
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : ADC_SSPRI_SS0_1ST

First priority

0x1 : ADC_SSPRI_SS0_2ND

Second priority

0x2 : ADC_SSPRI_SS0_3RD

Third priority

0x3 : ADC_SSPRI_SS0_4TH

Fourth priority

End of enumeration elements list.

ADC_SSPRI_SS1 : SS1 Priority
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : ADC_SSPRI_SS1_1ST

First priority

0x1 : ADC_SSPRI_SS1_2ND

Second priority

0x2 : ADC_SSPRI_SS1_3RD

Third priority

0x3 : ADC_SSPRI_SS1_4TH

Fourth priority

End of enumeration elements list.

ADC_SSPRI_SS2 : SS2 Priority
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : ADC_SSPRI_SS2_1ST

First priority

0x1 : ADC_SSPRI_SS2_2ND

Second priority

0x2 : ADC_SSPRI_SS2_3RD

Third priority

0x3 : ADC_SSPRI_SS2_4TH

Fourth priority

End of enumeration elements list.

ADC_SSPRI_SS3 : SS3 Priority
bits : 12 - 25 (14 bit)

Enumeration:

0x0 : ADC_SSPRI_SS3_1ST

First priority

0x1 : ADC_SSPRI_SS3_2ND

Second priority

0x2 : ADC_SSPRI_SS3_3RD

Third priority

0x3 : ADC_SSPRI_SS3_4TH

Fourth priority

End of enumeration elements list.


SSPRI

ADC Sample Sequencer Priority
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPRI SSPRI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSPRI_SS0 ADC_SSPRI_SS1 ADC_SSPRI_SS2 ADC_SSPRI_SS3

ADC_SSPRI_SS0 : SS0 Priority
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : ADC_SSPRI_SS0_1ST

First priority

0x1 : ADC_SSPRI_SS0_2ND

Second priority

0x2 : ADC_SSPRI_SS0_3RD

Third priority

0x3 : ADC_SSPRI_SS0_4TH

Fourth priority

End of enumeration elements list.

ADC_SSPRI_SS1 : SS1 Priority
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : ADC_SSPRI_SS1_1ST

First priority

0x1 : ADC_SSPRI_SS1_2ND

Second priority

0x2 : ADC_SSPRI_SS1_3RD

Third priority

0x3 : ADC_SSPRI_SS1_4TH

Fourth priority

End of enumeration elements list.

ADC_SSPRI_SS2 : SS2 Priority
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : ADC_SSPRI_SS2_1ST

First priority

0x1 : ADC_SSPRI_SS2_2ND

Second priority

0x2 : ADC_SSPRI_SS2_3RD

Third priority

0x3 : ADC_SSPRI_SS2_4TH

Fourth priority

End of enumeration elements list.

ADC_SSPRI_SS3 : SS3 Priority
bits : 12 - 25 (14 bit)

Enumeration:

0x0 : ADC_SSPRI_SS3_1ST

First priority

0x1 : ADC_SSPRI_SS3_2ND

Second priority

0x2 : ADC_SSPRI_SS3_3RD

Third priority

0x3 : ADC_SSPRI_SS3_4TH

Fourth priority

End of enumeration elements list.


ADC0SPC

ADC Sample Phase Control
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SPC ADC0SPC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SPC_PHASE

ADC_SPC_PHASE : Phase Difference
bits : 0 - 3 (4 bit)

Enumeration:

0x0 : ADC_SPC_PHASE_0

ADC sample lags by 0.0

0x1 : ADC_SPC_PHASE_22_5

ADC sample lags by 22.5

0x2 : ADC_SPC_PHASE_45

ADC sample lags by 45.0

0x3 : ADC_SPC_PHASE_67_5

ADC sample lags by 67.5

0x4 : ADC_SPC_PHASE_90

ADC sample lags by 90.0

0x5 : ADC_SPC_PHASE_112_5

ADC sample lags by 112.5

0x6 : ADC_SPC_PHASE_135

ADC sample lags by 135.0

0x7 : ADC_SPC_PHASE_157_5

ADC sample lags by 157.5

0x8 : ADC_SPC_PHASE_180

ADC sample lags by 180.0

0x9 : ADC_SPC_PHASE_202_5

ADC sample lags by 202.5

0xa : ADC_SPC_PHASE_225

ADC sample lags by 225.0

0xb : ADC_SPC_PHASE_247_5

ADC sample lags by 247.5

0xc : ADC_SPC_PHASE_270

ADC sample lags by 270.0

0xd : ADC_SPC_PHASE_292_5

ADC sample lags by 292.5

0xe : ADC_SPC_PHASE_315

ADC sample lags by 315.0

0xf : ADC_SPC_PHASE_337_5

ADC sample lags by 337.5

End of enumeration elements list.


SPC

ADC Sample Phase Control
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPC SPC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SPC_PHASE

ADC_SPC_PHASE : Phase Difference
bits : 0 - 3 (4 bit)

Enumeration:

0x0 : ADC_SPC_PHASE_0

ADC sample lags by 0.0

0x1 : ADC_SPC_PHASE_22_5

ADC sample lags by 22.5

0x2 : ADC_SPC_PHASE_45

ADC sample lags by 45.0

0x3 : ADC_SPC_PHASE_67_5

ADC sample lags by 67.5

0x4 : ADC_SPC_PHASE_90

ADC sample lags by 90.0

0x5 : ADC_SPC_PHASE_112_5

ADC sample lags by 112.5

0x6 : ADC_SPC_PHASE_135

ADC sample lags by 135.0

0x7 : ADC_SPC_PHASE_157_5

ADC sample lags by 157.5

0x8 : ADC_SPC_PHASE_180

ADC sample lags by 180.0

0x9 : ADC_SPC_PHASE_202_5

ADC sample lags by 202.5

0xa : ADC_SPC_PHASE_225

ADC sample lags by 225.0

0xb : ADC_SPC_PHASE_247_5

ADC sample lags by 247.5

0xc : ADC_SPC_PHASE_270

ADC sample lags by 270.0

0xd : ADC_SPC_PHASE_292_5

ADC sample lags by 292.5

0xe : ADC_SPC_PHASE_315

ADC sample lags by 315.0

0xf : ADC_SPC_PHASE_337_5

ADC sample lags by 337.5

End of enumeration elements list.


ADC0PSSI

ADC Processor Sample Sequence Initiate
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0PSSI ADC0PSSI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_PSSI_SS0 ADC_PSSI_SS1 ADC_PSSI_SS2 ADC_PSSI_SS3

ADC_PSSI_SS0 : SS0 Initiate
bits : 0 - 0 (1 bit)

ADC_PSSI_SS1 : SS1 Initiate
bits : 1 - 2 (2 bit)

ADC_PSSI_SS2 : SS2 Initiate
bits : 2 - 4 (3 bit)

ADC_PSSI_SS3 : SS3 Initiate
bits : 3 - 6 (4 bit)


PSSI

ADC Processor Sample Sequence Initiate
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSSI PSSI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_PSSI_SS0 ADC_PSSI_SS1 ADC_PSSI_SS2 ADC_PSSI_SS3

ADC_PSSI_SS0 : SS0 Initiate
bits : 0 - 0 (1 bit)

ADC_PSSI_SS1 : SS1 Initiate
bits : 1 - 2 (2 bit)

ADC_PSSI_SS2 : SS2 Initiate
bits : 2 - 4 (3 bit)

ADC_PSSI_SS3 : SS3 Initiate
bits : 3 - 6 (4 bit)


ADC0SAC

ADC Sample Averaging Control
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SAC ADC0SAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SAC_AVG

ADC_SAC_AVG : Hardware Averaging Control
bits : 0 - 2 (3 bit)

Enumeration:

0x0 : ADC_SAC_AVG_OFF

No hardware oversampling

0x1 : ADC_SAC_AVG_2X

2x hardware oversampling

0x2 : ADC_SAC_AVG_4X

4x hardware oversampling

0x3 : ADC_SAC_AVG_8X

8x hardware oversampling

0x4 : ADC_SAC_AVG_16X

16x hardware oversampling

0x5 : ADC_SAC_AVG_32X

32x hardware oversampling

0x6 : ADC_SAC_AVG_64X

64x hardware oversampling

End of enumeration elements list.


SAC

ADC Sample Averaging Control
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAC SAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SAC_AVG

ADC_SAC_AVG : Hardware Averaging Control
bits : 0 - 2 (3 bit)

Enumeration:

0x0 : ADC_SAC_AVG_OFF

No hardware oversampling

0x1 : ADC_SAC_AVG_2X

2x hardware oversampling

0x2 : ADC_SAC_AVG_4X

4x hardware oversampling

0x3 : ADC_SAC_AVG_8X

8x hardware oversampling

0x4 : ADC_SAC_AVG_16X

16x hardware oversampling

0x5 : ADC_SAC_AVG_32X

32x hardware oversampling

0x6 : ADC_SAC_AVG_64X

64x hardware oversampling

End of enumeration elements list.


ADC0DCISC

ADC Digital Comparator Interrupt Status and Clear
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0DCISC ADC0DCISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCISC_DCINT0 ADC_DCISC_DCINT1 ADC_DCISC_DCINT2 ADC_DCISC_DCINT3 ADC_DCISC_DCINT4 ADC_DCISC_DCINT5 ADC_DCISC_DCINT6 ADC_DCISC_DCINT7

ADC_DCISC_DCINT0 : Digital Comparator 0 Interrupt Status and Clear
bits : 0 - 0 (1 bit)

ADC_DCISC_DCINT1 : Digital Comparator 1 Interrupt Status and Clear
bits : 1 - 2 (2 bit)

ADC_DCISC_DCINT2 : Digital Comparator 2 Interrupt Status and Clear
bits : 2 - 4 (3 bit)

ADC_DCISC_DCINT3 : Digital Comparator 3 Interrupt Status and Clear
bits : 3 - 6 (4 bit)

ADC_DCISC_DCINT4 : Digital Comparator 4 Interrupt Status and Clear
bits : 4 - 8 (5 bit)

ADC_DCISC_DCINT5 : Digital Comparator 5 Interrupt Status and Clear
bits : 5 - 10 (6 bit)

ADC_DCISC_DCINT6 : Digital Comparator 6 Interrupt Status and Clear
bits : 6 - 12 (7 bit)

ADC_DCISC_DCINT7 : Digital Comparator 7 Interrupt Status and Clear
bits : 7 - 14 (8 bit)


DCISC

ADC Digital Comparator Interrupt Status and Clear
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCISC DCISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCISC_DCINT0 ADC_DCISC_DCINT1 ADC_DCISC_DCINT2 ADC_DCISC_DCINT3 ADC_DCISC_DCINT4 ADC_DCISC_DCINT5 ADC_DCISC_DCINT6 ADC_DCISC_DCINT7

ADC_DCISC_DCINT0 : Digital Comparator 0 Interrupt Status and Clear
bits : 0 - 0 (1 bit)

ADC_DCISC_DCINT1 : Digital Comparator 1 Interrupt Status and Clear
bits : 1 - 2 (2 bit)

ADC_DCISC_DCINT2 : Digital Comparator 2 Interrupt Status and Clear
bits : 2 - 4 (3 bit)

ADC_DCISC_DCINT3 : Digital Comparator 3 Interrupt Status and Clear
bits : 3 - 6 (4 bit)

ADC_DCISC_DCINT4 : Digital Comparator 4 Interrupt Status and Clear
bits : 4 - 8 (5 bit)

ADC_DCISC_DCINT5 : Digital Comparator 5 Interrupt Status and Clear
bits : 5 - 10 (6 bit)

ADC_DCISC_DCINT6 : Digital Comparator 6 Interrupt Status and Clear
bits : 6 - 12 (7 bit)

ADC_DCISC_DCINT7 : Digital Comparator 7 Interrupt Status and Clear
bits : 7 - 14 (8 bit)


ADC0CTL

ADC Control
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0CTL ADC0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_CTL_VREF

ADC_CTL_VREF : Voltage Reference Select
bits : 0 - 0 (1 bit)


CTL

ADC Control
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_CTL_VREF

ADC_CTL_VREF : Voltage Reference Select
bits : 0 - 0 (1 bit)


ADC0RIS

ADC Raw Interrupt Status
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0RIS ADC0RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_RIS_INR0 ADC_RIS_INR1 ADC_RIS_INR2 ADC_RIS_INR3 ADC_RIS_INRDC

ADC_RIS_INR0 : SS0 Raw Interrupt Status
bits : 0 - 0 (1 bit)

ADC_RIS_INR1 : SS1 Raw Interrupt Status
bits : 1 - 2 (2 bit)

ADC_RIS_INR2 : SS2 Raw Interrupt Status
bits : 2 - 4 (3 bit)

ADC_RIS_INR3 : SS3 Raw Interrupt Status
bits : 3 - 6 (4 bit)

ADC_RIS_INRDC : Digital Comparator Raw Interrupt Status
bits : 16 - 32 (17 bit)


RIS

ADC Raw Interrupt Status
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_RIS_INR0 ADC_RIS_INR1 ADC_RIS_INR2 ADC_RIS_INR3 ADC_RIS_INRDC

ADC_RIS_INR0 : SS0 Raw Interrupt Status
bits : 0 - 0 (1 bit)

ADC_RIS_INR1 : SS1 Raw Interrupt Status
bits : 1 - 2 (2 bit)

ADC_RIS_INR2 : SS2 Raw Interrupt Status
bits : 2 - 4 (3 bit)

ADC_RIS_INR3 : SS3 Raw Interrupt Status
bits : 3 - 6 (4 bit)

ADC_RIS_INRDC : Digital Comparator Raw Interrupt Status
bits : 16 - 32 (17 bit)


ADC0SSMUX0

ADC Sample Sequence Input Multiplexer Select 0
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSMUX0 ADC0SSMUX0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSMUX0_MUX0 ADC_SSMUX0_MUX1 ADC_SSMUX0_MUX2 ADC_SSMUX0_MUX3 ADC_SSMUX0_MUX4 ADC_SSMUX0_MUX5 ADC_SSMUX0_MUX6 ADC_SSMUX0_MUX7

ADC_SSMUX0_MUX0 : 1st Sample Input Select
bits : 0 - 2 (3 bit)

ADC_SSMUX0_MUX1 : 2nd Sample Input Select
bits : 4 - 10 (7 bit)

ADC_SSMUX0_MUX2 : 3rd Sample Input Select
bits : 8 - 18 (11 bit)

ADC_SSMUX0_MUX3 : 4th Sample Input Select
bits : 12 - 26 (15 bit)

ADC_SSMUX0_MUX4 : 5th Sample Input Select
bits : 16 - 34 (19 bit)

ADC_SSMUX0_MUX5 : 6th Sample Input Select
bits : 20 - 42 (23 bit)

ADC_SSMUX0_MUX6 : 7th Sample Input Select
bits : 24 - 50 (27 bit)

ADC_SSMUX0_MUX7 : 8th Sample Input Select
bits : 28 - 58 (31 bit)


SSMUX0

ADC Sample Sequence Input Multiplexer Select 0
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSMUX0 SSMUX0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSMUX0_MUX0 ADC_SSMUX0_MUX1 ADC_SSMUX0_MUX2 ADC_SSMUX0_MUX3 ADC_SSMUX0_MUX4 ADC_SSMUX0_MUX5 ADC_SSMUX0_MUX6 ADC_SSMUX0_MUX7

ADC_SSMUX0_MUX0 : 1st Sample Input Select
bits : 0 - 2 (3 bit)

ADC_SSMUX0_MUX1 : 2nd Sample Input Select
bits : 4 - 10 (7 bit)

ADC_SSMUX0_MUX2 : 3rd Sample Input Select
bits : 8 - 18 (11 bit)

ADC_SSMUX0_MUX3 : 4th Sample Input Select
bits : 12 - 26 (15 bit)

ADC_SSMUX0_MUX4 : 5th Sample Input Select
bits : 16 - 34 (19 bit)

ADC_SSMUX0_MUX5 : 6th Sample Input Select
bits : 20 - 42 (23 bit)

ADC_SSMUX0_MUX6 : 7th Sample Input Select
bits : 24 - 50 (27 bit)

ADC_SSMUX0_MUX7 : 8th Sample Input Select
bits : 28 - 58 (31 bit)


ADC0SSCTL0

ADC Sample Sequence Control 0
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSCTL0 ADC0SSCTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSCTL0_D0 ADC_SSCTL0_END0 ADC_SSCTL0_IE0 ADC_SSCTL0_TS0 ADC_SSCTL0_D1 ADC_SSCTL0_END1 ADC_SSCTL0_IE1 ADC_SSCTL0_TS1 ADC_SSCTL0_D2 ADC_SSCTL0_END2 ADC_SSCTL0_IE2 ADC_SSCTL0_TS2 ADC_SSCTL0_D3 ADC_SSCTL0_END3 ADC_SSCTL0_IE3 ADC_SSCTL0_TS3 ADC_SSCTL0_D4 ADC_SSCTL0_END4 ADC_SSCTL0_IE4 ADC_SSCTL0_TS4 ADC_SSCTL0_D5 ADC_SSCTL0_END5 ADC_SSCTL0_IE5 ADC_SSCTL0_TS5 ADC_SSCTL0_D6 ADC_SSCTL0_END6 ADC_SSCTL0_IE6 ADC_SSCTL0_TS6 ADC_SSCTL0_D7 ADC_SSCTL0_END7 ADC_SSCTL0_IE7 ADC_SSCTL0_TS7

ADC_SSCTL0_D0 : 1st Sample Diff Input Select
bits : 0 - 0 (1 bit)

ADC_SSCTL0_END0 : 1st Sample is End of Sequence
bits : 1 - 2 (2 bit)

ADC_SSCTL0_IE0 : 1st Sample Interrupt Enable
bits : 2 - 4 (3 bit)

ADC_SSCTL0_TS0 : 1st Sample Temp Sensor Select
bits : 3 - 6 (4 bit)

ADC_SSCTL0_D1 : 2nd Sample Diff Input Select
bits : 4 - 8 (5 bit)

ADC_SSCTL0_END1 : 2nd Sample is End of Sequence
bits : 5 - 10 (6 bit)

ADC_SSCTL0_IE1 : 2nd Sample Interrupt Enable
bits : 6 - 12 (7 bit)

ADC_SSCTL0_TS1 : 2nd Sample Temp Sensor Select
bits : 7 - 14 (8 bit)

ADC_SSCTL0_D2 : 3rd Sample Diff Input Select
bits : 8 - 16 (9 bit)

ADC_SSCTL0_END2 : 3rd Sample is End of Sequence
bits : 9 - 18 (10 bit)

ADC_SSCTL0_IE2 : 3rd Sample Interrupt Enable
bits : 10 - 20 (11 bit)

ADC_SSCTL0_TS2 : 3rd Sample Temp Sensor Select
bits : 11 - 22 (12 bit)

ADC_SSCTL0_D3 : 4th Sample Diff Input Select
bits : 12 - 24 (13 bit)

ADC_SSCTL0_END3 : 4th Sample is End of Sequence
bits : 13 - 26 (14 bit)

ADC_SSCTL0_IE3 : 4th Sample Interrupt Enable
bits : 14 - 28 (15 bit)

ADC_SSCTL0_TS3 : 4th Sample Temp Sensor Select
bits : 15 - 30 (16 bit)

ADC_SSCTL0_D4 : 5th Sample Diff Input Select
bits : 16 - 32 (17 bit)

ADC_SSCTL0_END4 : 5th Sample is End of Sequence
bits : 17 - 34 (18 bit)

ADC_SSCTL0_IE4 : 5th Sample Interrupt Enable
bits : 18 - 36 (19 bit)

ADC_SSCTL0_TS4 : 5th Sample Temp Sensor Select
bits : 19 - 38 (20 bit)

ADC_SSCTL0_D5 : 6th Sample Diff Input Select
bits : 20 - 40 (21 bit)

ADC_SSCTL0_END5 : 6th Sample is End of Sequence
bits : 21 - 42 (22 bit)

ADC_SSCTL0_IE5 : 6th Sample Interrupt Enable
bits : 22 - 44 (23 bit)

ADC_SSCTL0_TS5 : 6th Sample Temp Sensor Select
bits : 23 - 46 (24 bit)

ADC_SSCTL0_D6 : 7th Sample Diff Input Select
bits : 24 - 48 (25 bit)

ADC_SSCTL0_END6 : 7th Sample is End of Sequence
bits : 25 - 50 (26 bit)

ADC_SSCTL0_IE6 : 7th Sample Interrupt Enable
bits : 26 - 52 (27 bit)

ADC_SSCTL0_TS6 : 7th Sample Temp Sensor Select
bits : 27 - 54 (28 bit)

ADC_SSCTL0_D7 : 8th Sample Diff Input Select
bits : 28 - 56 (29 bit)

ADC_SSCTL0_END7 : 8th Sample is End of Sequence
bits : 29 - 58 (30 bit)

ADC_SSCTL0_IE7 : 8th Sample Interrupt Enable
bits : 30 - 60 (31 bit)

ADC_SSCTL0_TS7 : 8th Sample Temp Sensor Select
bits : 31 - 62 (32 bit)


SSCTL0

ADC Sample Sequence Control 0
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSCTL0 SSCTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSCTL0_D0 ADC_SSCTL0_END0 ADC_SSCTL0_IE0 ADC_SSCTL0_TS0 ADC_SSCTL0_D1 ADC_SSCTL0_END1 ADC_SSCTL0_IE1 ADC_SSCTL0_TS1 ADC_SSCTL0_D2 ADC_SSCTL0_END2 ADC_SSCTL0_IE2 ADC_SSCTL0_TS2 ADC_SSCTL0_D3 ADC_SSCTL0_END3 ADC_SSCTL0_IE3 ADC_SSCTL0_TS3 ADC_SSCTL0_D4 ADC_SSCTL0_END4 ADC_SSCTL0_IE4 ADC_SSCTL0_TS4 ADC_SSCTL0_D5 ADC_SSCTL0_END5 ADC_SSCTL0_IE5 ADC_SSCTL0_TS5 ADC_SSCTL0_D6 ADC_SSCTL0_END6 ADC_SSCTL0_IE6 ADC_SSCTL0_TS6 ADC_SSCTL0_D7 ADC_SSCTL0_END7 ADC_SSCTL0_IE7 ADC_SSCTL0_TS7

ADC_SSCTL0_D0 : 1st Sample Diff Input Select
bits : 0 - 0 (1 bit)

ADC_SSCTL0_END0 : 1st Sample is End of Sequence
bits : 1 - 2 (2 bit)

ADC_SSCTL0_IE0 : 1st Sample Interrupt Enable
bits : 2 - 4 (3 bit)

ADC_SSCTL0_TS0 : 1st Sample Temp Sensor Select
bits : 3 - 6 (4 bit)

ADC_SSCTL0_D1 : 2nd Sample Diff Input Select
bits : 4 - 8 (5 bit)

ADC_SSCTL0_END1 : 2nd Sample is End of Sequence
bits : 5 - 10 (6 bit)

ADC_SSCTL0_IE1 : 2nd Sample Interrupt Enable
bits : 6 - 12 (7 bit)

ADC_SSCTL0_TS1 : 2nd Sample Temp Sensor Select
bits : 7 - 14 (8 bit)

ADC_SSCTL0_D2 : 3rd Sample Diff Input Select
bits : 8 - 16 (9 bit)

ADC_SSCTL0_END2 : 3rd Sample is End of Sequence
bits : 9 - 18 (10 bit)

ADC_SSCTL0_IE2 : 3rd Sample Interrupt Enable
bits : 10 - 20 (11 bit)

ADC_SSCTL0_TS2 : 3rd Sample Temp Sensor Select
bits : 11 - 22 (12 bit)

ADC_SSCTL0_D3 : 4th Sample Diff Input Select
bits : 12 - 24 (13 bit)

ADC_SSCTL0_END3 : 4th Sample is End of Sequence
bits : 13 - 26 (14 bit)

ADC_SSCTL0_IE3 : 4th Sample Interrupt Enable
bits : 14 - 28 (15 bit)

ADC_SSCTL0_TS3 : 4th Sample Temp Sensor Select
bits : 15 - 30 (16 bit)

ADC_SSCTL0_D4 : 5th Sample Diff Input Select
bits : 16 - 32 (17 bit)

ADC_SSCTL0_END4 : 5th Sample is End of Sequence
bits : 17 - 34 (18 bit)

ADC_SSCTL0_IE4 : 5th Sample Interrupt Enable
bits : 18 - 36 (19 bit)

ADC_SSCTL0_TS4 : 5th Sample Temp Sensor Select
bits : 19 - 38 (20 bit)

ADC_SSCTL0_D5 : 6th Sample Diff Input Select
bits : 20 - 40 (21 bit)

ADC_SSCTL0_END5 : 6th Sample is End of Sequence
bits : 21 - 42 (22 bit)

ADC_SSCTL0_IE5 : 6th Sample Interrupt Enable
bits : 22 - 44 (23 bit)

ADC_SSCTL0_TS5 : 6th Sample Temp Sensor Select
bits : 23 - 46 (24 bit)

ADC_SSCTL0_D6 : 7th Sample Diff Input Select
bits : 24 - 48 (25 bit)

ADC_SSCTL0_END6 : 7th Sample is End of Sequence
bits : 25 - 50 (26 bit)

ADC_SSCTL0_IE6 : 7th Sample Interrupt Enable
bits : 26 - 52 (27 bit)

ADC_SSCTL0_TS6 : 7th Sample Temp Sensor Select
bits : 27 - 54 (28 bit)

ADC_SSCTL0_D7 : 8th Sample Diff Input Select
bits : 28 - 56 (29 bit)

ADC_SSCTL0_END7 : 8th Sample is End of Sequence
bits : 29 - 58 (30 bit)

ADC_SSCTL0_IE7 : 8th Sample Interrupt Enable
bits : 30 - 60 (31 bit)

ADC_SSCTL0_TS7 : 8th Sample Temp Sensor Select
bits : 31 - 62 (32 bit)


ADC0SSFIFO0

ADC Sample Sequence Result FIFO 0
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSFIFO0 ADC0SSFIFO0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSFIFO0_DATA

ADC_SSFIFO0_DATA : Conversion Result Data
bits : 0 - 9 (10 bit)


SSFIFO0

ADC Sample Sequence Result FIFO 0
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSFIFO0 SSFIFO0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSFIFO0_DATA

ADC_SSFIFO0_DATA : Conversion Result Data
bits : 0 - 9 (10 bit)


ADC0SSFSTAT0

ADC Sample Sequence FIFO 0 Status
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSFSTAT0 ADC0SSFSTAT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSFSTAT0_TPTR ADC_SSFSTAT0_HPTR ADC_SSFSTAT0_EMPTY ADC_SSFSTAT0_FULL

ADC_SSFSTAT0_TPTR : FIFO Tail Pointer
bits : 0 - 3 (4 bit)

ADC_SSFSTAT0_HPTR : FIFO Head Pointer
bits : 4 - 11 (8 bit)

ADC_SSFSTAT0_EMPTY : FIFO Empty
bits : 8 - 16 (9 bit)

ADC_SSFSTAT0_FULL : FIFO Full
bits : 12 - 24 (13 bit)


SSFSTAT0

ADC Sample Sequence FIFO 0 Status
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSFSTAT0 SSFSTAT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSFSTAT0_TPTR ADC_SSFSTAT0_HPTR ADC_SSFSTAT0_EMPTY ADC_SSFSTAT0_FULL

ADC_SSFSTAT0_TPTR : FIFO Tail Pointer
bits : 0 - 3 (4 bit)

ADC_SSFSTAT0_HPTR : FIFO Head Pointer
bits : 4 - 11 (8 bit)

ADC_SSFSTAT0_EMPTY : FIFO Empty
bits : 8 - 16 (9 bit)

ADC_SSFSTAT0_FULL : FIFO Full
bits : 12 - 24 (13 bit)


ADC0SSOP0

ADC Sample Sequence 0 Operation
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSOP0 ADC0SSOP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSOP0_S0DCOP ADC_SSOP0_S1DCOP ADC_SSOP0_S2DCOP ADC_SSOP0_S3DCOP ADC_SSOP0_S4DCOP ADC_SSOP0_S5DCOP ADC_SSOP0_S6DCOP ADC_SSOP0_S7DCOP

ADC_SSOP0_S0DCOP : Sample 0 Digital Comparator Operation
bits : 0 - 0 (1 bit)

ADC_SSOP0_S1DCOP : Sample 1 Digital Comparator Operation
bits : 4 - 8 (5 bit)

ADC_SSOP0_S2DCOP : Sample 2 Digital Comparator Operation
bits : 8 - 16 (9 bit)

ADC_SSOP0_S3DCOP : Sample 3 Digital Comparator Operation
bits : 12 - 24 (13 bit)

ADC_SSOP0_S4DCOP : Sample 4 Digital Comparator Operation
bits : 16 - 32 (17 bit)

ADC_SSOP0_S5DCOP : Sample 5 Digital Comparator Operation
bits : 20 - 40 (21 bit)

ADC_SSOP0_S6DCOP : Sample 6 Digital Comparator Operation
bits : 24 - 48 (25 bit)

ADC_SSOP0_S7DCOP : Sample 7 Digital Comparator Operation
bits : 28 - 56 (29 bit)


SSOP0

ADC Sample Sequence 0 Operation
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSOP0 SSOP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSOP0_S0DCOP ADC_SSOP0_S1DCOP ADC_SSOP0_S2DCOP ADC_SSOP0_S3DCOP ADC_SSOP0_S4DCOP ADC_SSOP0_S5DCOP ADC_SSOP0_S6DCOP ADC_SSOP0_S7DCOP

ADC_SSOP0_S0DCOP : Sample 0 Digital Comparator Operation
bits : 0 - 0 (1 bit)

ADC_SSOP0_S1DCOP : Sample 1 Digital Comparator Operation
bits : 4 - 8 (5 bit)

ADC_SSOP0_S2DCOP : Sample 2 Digital Comparator Operation
bits : 8 - 16 (9 bit)

ADC_SSOP0_S3DCOP : Sample 3 Digital Comparator Operation
bits : 12 - 24 (13 bit)

ADC_SSOP0_S4DCOP : Sample 4 Digital Comparator Operation
bits : 16 - 32 (17 bit)

ADC_SSOP0_S5DCOP : Sample 5 Digital Comparator Operation
bits : 20 - 40 (21 bit)

ADC_SSOP0_S6DCOP : Sample 6 Digital Comparator Operation
bits : 24 - 48 (25 bit)

ADC_SSOP0_S7DCOP : Sample 7 Digital Comparator Operation
bits : 28 - 56 (29 bit)


ADC0SSDC0

ADC Sample Sequence 0 Digital Comparator Select
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSDC0 ADC0SSDC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSDC0_S0DCSEL ADC_SSDC0_S1DCSEL ADC_SSDC0_S2DCSEL ADC_SSDC0_S3DCSEL ADC_SSDC0_S4DCSEL ADC_SSDC0_S5DCSEL ADC_SSDC0_S6DCSEL ADC_SSDC0_S7DCSEL

ADC_SSDC0_S0DCSEL : Sample 0 Digital Comparator Select
bits : 0 - 3 (4 bit)

ADC_SSDC0_S1DCSEL : Sample 1 Digital Comparator Select
bits : 4 - 11 (8 bit)

ADC_SSDC0_S2DCSEL : Sample 2 Digital Comparator Select
bits : 8 - 19 (12 bit)

ADC_SSDC0_S3DCSEL : Sample 3 Digital Comparator Select
bits : 12 - 27 (16 bit)

ADC_SSDC0_S4DCSEL : Sample 4 Digital Comparator Select
bits : 16 - 35 (20 bit)

ADC_SSDC0_S5DCSEL : Sample 5 Digital Comparator Select
bits : 20 - 43 (24 bit)

ADC_SSDC0_S6DCSEL : Sample 6 Digital Comparator Select
bits : 24 - 51 (28 bit)

ADC_SSDC0_S7DCSEL : Sample 7 Digital Comparator Select
bits : 28 - 59 (32 bit)


SSDC0

ADC Sample Sequence 0 Digital Comparator Select
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSDC0 SSDC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSDC0_S0DCSEL ADC_SSDC0_S1DCSEL ADC_SSDC0_S2DCSEL ADC_SSDC0_S3DCSEL ADC_SSDC0_S4DCSEL ADC_SSDC0_S5DCSEL ADC_SSDC0_S6DCSEL ADC_SSDC0_S7DCSEL

ADC_SSDC0_S0DCSEL : Sample 0 Digital Comparator Select
bits : 0 - 3 (4 bit)

ADC_SSDC0_S1DCSEL : Sample 1 Digital Comparator Select
bits : 4 - 11 (8 bit)

ADC_SSDC0_S2DCSEL : Sample 2 Digital Comparator Select
bits : 8 - 19 (12 bit)

ADC_SSDC0_S3DCSEL : Sample 3 Digital Comparator Select
bits : 12 - 27 (16 bit)

ADC_SSDC0_S4DCSEL : Sample 4 Digital Comparator Select
bits : 16 - 35 (20 bit)

ADC_SSDC0_S5DCSEL : Sample 5 Digital Comparator Select
bits : 20 - 43 (24 bit)

ADC_SSDC0_S6DCSEL : Sample 6 Digital Comparator Select
bits : 24 - 51 (28 bit)

ADC_SSDC0_S7DCSEL : Sample 7 Digital Comparator Select
bits : 28 - 59 (32 bit)


ADC0SSMUX1

ADC Sample Sequence Input Multiplexer Select 1
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSMUX1 ADC0SSMUX1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSMUX1_MUX0 ADC_SSMUX1_MUX1 ADC_SSMUX1_MUX2 ADC_SSMUX1_MUX3

ADC_SSMUX1_MUX0 : 1st Sample Input Select
bits : 0 - 2 (3 bit)

ADC_SSMUX1_MUX1 : 2nd Sample Input Select
bits : 4 - 10 (7 bit)

ADC_SSMUX1_MUX2 : 3rd Sample Input Select
bits : 8 - 18 (11 bit)

ADC_SSMUX1_MUX3 : 4th Sample Input Select
bits : 12 - 26 (15 bit)


SSMUX1

ADC Sample Sequence Input Multiplexer Select 1
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSMUX1 SSMUX1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSMUX1_MUX0 ADC_SSMUX1_MUX1 ADC_SSMUX1_MUX2 ADC_SSMUX1_MUX3

ADC_SSMUX1_MUX0 : 1st Sample Input Select
bits : 0 - 2 (3 bit)

ADC_SSMUX1_MUX1 : 2nd Sample Input Select
bits : 4 - 10 (7 bit)

ADC_SSMUX1_MUX2 : 3rd Sample Input Select
bits : 8 - 18 (11 bit)

ADC_SSMUX1_MUX3 : 4th Sample Input Select
bits : 12 - 26 (15 bit)


ADC0SSCTL1

ADC Sample Sequence Control 1
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSCTL1 ADC0SSCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSCTL1_D0 ADC_SSCTL1_END0 ADC_SSCTL1_IE0 ADC_SSCTL1_TS0 ADC_SSCTL1_D1 ADC_SSCTL1_END1 ADC_SSCTL1_IE1 ADC_SSCTL1_TS1 ADC_SSCTL1_D2 ADC_SSCTL1_END2 ADC_SSCTL1_IE2 ADC_SSCTL1_TS2 ADC_SSCTL1_D3 ADC_SSCTL1_END3 ADC_SSCTL1_IE3 ADC_SSCTL1_TS3

ADC_SSCTL1_D0 : 1st Sample Diff Input Select
bits : 0 - 0 (1 bit)

ADC_SSCTL1_END0 : 1st Sample is End of Sequence
bits : 1 - 2 (2 bit)

ADC_SSCTL1_IE0 : 1st Sample Interrupt Enable
bits : 2 - 4 (3 bit)

ADC_SSCTL1_TS0 : 1st Sample Temp Sensor Select
bits : 3 - 6 (4 bit)

ADC_SSCTL1_D1 : 2nd Sample Diff Input Select
bits : 4 - 8 (5 bit)

ADC_SSCTL1_END1 : 2nd Sample is End of Sequence
bits : 5 - 10 (6 bit)

ADC_SSCTL1_IE1 : 2nd Sample Interrupt Enable
bits : 6 - 12 (7 bit)

ADC_SSCTL1_TS1 : 2nd Sample Temp Sensor Select
bits : 7 - 14 (8 bit)

ADC_SSCTL1_D2 : 3rd Sample Diff Input Select
bits : 8 - 16 (9 bit)

ADC_SSCTL1_END2 : 3rd Sample is End of Sequence
bits : 9 - 18 (10 bit)

ADC_SSCTL1_IE2 : 3rd Sample Interrupt Enable
bits : 10 - 20 (11 bit)

ADC_SSCTL1_TS2 : 3rd Sample Temp Sensor Select
bits : 11 - 22 (12 bit)

ADC_SSCTL1_D3 : 4th Sample Diff Input Select
bits : 12 - 24 (13 bit)

ADC_SSCTL1_END3 : 4th Sample is End of Sequence
bits : 13 - 26 (14 bit)

ADC_SSCTL1_IE3 : 4th Sample Interrupt Enable
bits : 14 - 28 (15 bit)

ADC_SSCTL1_TS3 : 4th Sample Temp Sensor Select
bits : 15 - 30 (16 bit)


SSCTL1

ADC Sample Sequence Control 1
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSCTL1 SSCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSCTL1_D0 ADC_SSCTL1_END0 ADC_SSCTL1_IE0 ADC_SSCTL1_TS0 ADC_SSCTL1_D1 ADC_SSCTL1_END1 ADC_SSCTL1_IE1 ADC_SSCTL1_TS1 ADC_SSCTL1_D2 ADC_SSCTL1_END2 ADC_SSCTL1_IE2 ADC_SSCTL1_TS2 ADC_SSCTL1_D3 ADC_SSCTL1_END3 ADC_SSCTL1_IE3 ADC_SSCTL1_TS3

ADC_SSCTL1_D0 : 1st Sample Diff Input Select
bits : 0 - 0 (1 bit)

ADC_SSCTL1_END0 : 1st Sample is End of Sequence
bits : 1 - 2 (2 bit)

ADC_SSCTL1_IE0 : 1st Sample Interrupt Enable
bits : 2 - 4 (3 bit)

ADC_SSCTL1_TS0 : 1st Sample Temp Sensor Select
bits : 3 - 6 (4 bit)

ADC_SSCTL1_D1 : 2nd Sample Diff Input Select
bits : 4 - 8 (5 bit)

ADC_SSCTL1_END1 : 2nd Sample is End of Sequence
bits : 5 - 10 (6 bit)

ADC_SSCTL1_IE1 : 2nd Sample Interrupt Enable
bits : 6 - 12 (7 bit)

ADC_SSCTL1_TS1 : 2nd Sample Temp Sensor Select
bits : 7 - 14 (8 bit)

ADC_SSCTL1_D2 : 3rd Sample Diff Input Select
bits : 8 - 16 (9 bit)

ADC_SSCTL1_END2 : 3rd Sample is End of Sequence
bits : 9 - 18 (10 bit)

ADC_SSCTL1_IE2 : 3rd Sample Interrupt Enable
bits : 10 - 20 (11 bit)

ADC_SSCTL1_TS2 : 3rd Sample Temp Sensor Select
bits : 11 - 22 (12 bit)

ADC_SSCTL1_D3 : 4th Sample Diff Input Select
bits : 12 - 24 (13 bit)

ADC_SSCTL1_END3 : 4th Sample is End of Sequence
bits : 13 - 26 (14 bit)

ADC_SSCTL1_IE3 : 4th Sample Interrupt Enable
bits : 14 - 28 (15 bit)

ADC_SSCTL1_TS3 : 4th Sample Temp Sensor Select
bits : 15 - 30 (16 bit)


ADC0SSFIFO1

ADC Sample Sequence Result FIFO 1
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSFIFO1 ADC0SSFIFO1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSFIFO1_DATA

ADC_SSFIFO1_DATA : Conversion Result Data
bits : 0 - 9 (10 bit)


SSFIFO1

ADC Sample Sequence Result FIFO 1
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSFIFO1 SSFIFO1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSFIFO1_DATA

ADC_SSFIFO1_DATA : Conversion Result Data
bits : 0 - 9 (10 bit)


ADC0SSFSTAT1

ADC Sample Sequence FIFO 1 Status
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSFSTAT1 ADC0SSFSTAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSFSTAT1_TPTR ADC_SSFSTAT1_HPTR ADC_SSFSTAT1_EMPTY ADC_SSFSTAT1_FULL

ADC_SSFSTAT1_TPTR : FIFO Tail Pointer
bits : 0 - 3 (4 bit)

ADC_SSFSTAT1_HPTR : FIFO Head Pointer
bits : 4 - 11 (8 bit)

ADC_SSFSTAT1_EMPTY : FIFO Empty
bits : 8 - 16 (9 bit)

ADC_SSFSTAT1_FULL : FIFO Full
bits : 12 - 24 (13 bit)


SSFSTAT1

ADC Sample Sequence FIFO 1 Status
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSFSTAT1 SSFSTAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSFSTAT1_TPTR ADC_SSFSTAT1_HPTR ADC_SSFSTAT1_EMPTY ADC_SSFSTAT1_FULL

ADC_SSFSTAT1_TPTR : FIFO Tail Pointer
bits : 0 - 3 (4 bit)

ADC_SSFSTAT1_HPTR : FIFO Head Pointer
bits : 4 - 11 (8 bit)

ADC_SSFSTAT1_EMPTY : FIFO Empty
bits : 8 - 16 (9 bit)

ADC_SSFSTAT1_FULL : FIFO Full
bits : 12 - 24 (13 bit)


ADC0SSOP1

ADC Sample Sequence 1 Operation
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSOP1 ADC0SSOP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSOP1_S0DCOP ADC_SSOP1_S1DCOP ADC_SSOP1_S2DCOP ADC_SSOP1_S3DCOP

ADC_SSOP1_S0DCOP : Sample 0 Digital Comparator Operation
bits : 0 - 0 (1 bit)

ADC_SSOP1_S1DCOP : Sample 1 Digital Comparator Operation
bits : 4 - 8 (5 bit)

ADC_SSOP1_S2DCOP : Sample 2 Digital Comparator Operation
bits : 8 - 16 (9 bit)

ADC_SSOP1_S3DCOP : Sample 3 Digital Comparator Operation
bits : 12 - 24 (13 bit)


SSOP1

ADC Sample Sequence 1 Operation
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSOP1 SSOP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSOP1_S0DCOP ADC_SSOP1_S1DCOP ADC_SSOP1_S2DCOP ADC_SSOP1_S3DCOP

ADC_SSOP1_S0DCOP : Sample 0 Digital Comparator Operation
bits : 0 - 0 (1 bit)

ADC_SSOP1_S1DCOP : Sample 1 Digital Comparator Operation
bits : 4 - 8 (5 bit)

ADC_SSOP1_S2DCOP : Sample 2 Digital Comparator Operation
bits : 8 - 16 (9 bit)

ADC_SSOP1_S3DCOP : Sample 3 Digital Comparator Operation
bits : 12 - 24 (13 bit)


ADC0SSDC1

ADC Sample Sequence 1 Digital Comparator Select
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSDC1 ADC0SSDC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSDC1_S0DCSEL ADC_SSDC1_S1DCSEL ADC_SSDC1_S2DCSEL ADC_SSDC1_S3DCSEL

ADC_SSDC1_S0DCSEL : Sample 0 Digital Comparator Select
bits : 0 - 3 (4 bit)

ADC_SSDC1_S1DCSEL : Sample 1 Digital Comparator Select
bits : 4 - 11 (8 bit)

ADC_SSDC1_S2DCSEL : Sample 2 Digital Comparator Select
bits : 8 - 19 (12 bit)

ADC_SSDC1_S3DCSEL : Sample 3 Digital Comparator Select
bits : 12 - 27 (16 bit)


SSDC1

ADC Sample Sequence 1 Digital Comparator Select
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSDC1 SSDC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSDC1_S0DCSEL ADC_SSDC1_S1DCSEL ADC_SSDC1_S2DCSEL ADC_SSDC1_S3DCSEL

ADC_SSDC1_S0DCSEL : Sample 0 Digital Comparator Select
bits : 0 - 3 (4 bit)

ADC_SSDC1_S1DCSEL : Sample 1 Digital Comparator Select
bits : 4 - 11 (8 bit)

ADC_SSDC1_S2DCSEL : Sample 2 Digital Comparator Select
bits : 8 - 19 (12 bit)

ADC_SSDC1_S3DCSEL : Sample 3 Digital Comparator Select
bits : 12 - 27 (16 bit)


ADC0IM

ADC Interrupt Mask
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0IM ADC0IM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_IM_MASK0 ADC_IM_MASK1 ADC_IM_MASK2 ADC_IM_MASK3 ADC_IM_DCONSS0 ADC_IM_DCONSS1 ADC_IM_DCONSS2 ADC_IM_DCONSS3

ADC_IM_MASK0 : SS0 Interrupt Mask
bits : 0 - 0 (1 bit)

ADC_IM_MASK1 : SS1 Interrupt Mask
bits : 1 - 2 (2 bit)

ADC_IM_MASK2 : SS2 Interrupt Mask
bits : 2 - 4 (3 bit)

ADC_IM_MASK3 : SS3 Interrupt Mask
bits : 3 - 6 (4 bit)

ADC_IM_DCONSS0 : Digital Comparator Interrupt on SS0
bits : 16 - 32 (17 bit)

ADC_IM_DCONSS1 : Digital Comparator Interrupt on SS1
bits : 17 - 34 (18 bit)

ADC_IM_DCONSS2 : Digital Comparator Interrupt on SS2
bits : 18 - 36 (19 bit)

ADC_IM_DCONSS3 : Digital Comparator Interrupt on SS3
bits : 19 - 38 (20 bit)


IM

ADC Interrupt Mask
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IM IM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_IM_MASK0 ADC_IM_MASK1 ADC_IM_MASK2 ADC_IM_MASK3 ADC_IM_DCONSS0 ADC_IM_DCONSS1 ADC_IM_DCONSS2 ADC_IM_DCONSS3

ADC_IM_MASK0 : SS0 Interrupt Mask
bits : 0 - 0 (1 bit)

ADC_IM_MASK1 : SS1 Interrupt Mask
bits : 1 - 2 (2 bit)

ADC_IM_MASK2 : SS2 Interrupt Mask
bits : 2 - 4 (3 bit)

ADC_IM_MASK3 : SS3 Interrupt Mask
bits : 3 - 6 (4 bit)

ADC_IM_DCONSS0 : Digital Comparator Interrupt on SS0
bits : 16 - 32 (17 bit)

ADC_IM_DCONSS1 : Digital Comparator Interrupt on SS1
bits : 17 - 34 (18 bit)

ADC_IM_DCONSS2 : Digital Comparator Interrupt on SS2
bits : 18 - 36 (19 bit)

ADC_IM_DCONSS3 : Digital Comparator Interrupt on SS3
bits : 19 - 38 (20 bit)


ADC0SSMUX2

ADC Sample Sequence Input Multiplexer Select 2
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSMUX2 ADC0SSMUX2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSMUX2_MUX0 ADC_SSMUX2_MUX1 ADC_SSMUX2_MUX2 ADC_SSMUX2_MUX3

ADC_SSMUX2_MUX0 : 1st Sample Input Select
bits : 0 - 2 (3 bit)

ADC_SSMUX2_MUX1 : 2nd Sample Input Select
bits : 4 - 10 (7 bit)

ADC_SSMUX2_MUX2 : 3rd Sample Input Select
bits : 8 - 18 (11 bit)

ADC_SSMUX2_MUX3 : 4th Sample Input Select
bits : 12 - 26 (15 bit)


SSMUX2

ADC Sample Sequence Input Multiplexer Select 2
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSMUX2 SSMUX2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSMUX2_MUX0 ADC_SSMUX2_MUX1 ADC_SSMUX2_MUX2 ADC_SSMUX2_MUX3

ADC_SSMUX2_MUX0 : 1st Sample Input Select
bits : 0 - 2 (3 bit)

ADC_SSMUX2_MUX1 : 2nd Sample Input Select
bits : 4 - 10 (7 bit)

ADC_SSMUX2_MUX2 : 3rd Sample Input Select
bits : 8 - 18 (11 bit)

ADC_SSMUX2_MUX3 : 4th Sample Input Select
bits : 12 - 26 (15 bit)


ADC0SSCTL2

ADC Sample Sequence Control 2
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSCTL2 ADC0SSCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSCTL2_D0 ADC_SSCTL2_END0 ADC_SSCTL2_IE0 ADC_SSCTL2_TS0 ADC_SSCTL2_D1 ADC_SSCTL2_END1 ADC_SSCTL2_IE1 ADC_SSCTL2_TS1 ADC_SSCTL2_D2 ADC_SSCTL2_END2 ADC_SSCTL2_IE2 ADC_SSCTL2_TS2 ADC_SSCTL2_D3 ADC_SSCTL2_END3 ADC_SSCTL2_IE3 ADC_SSCTL2_TS3

ADC_SSCTL2_D0 : 1st Sample Diff Input Select
bits : 0 - 0 (1 bit)

ADC_SSCTL2_END0 : 1st Sample is End of Sequence
bits : 1 - 2 (2 bit)

ADC_SSCTL2_IE0 : 1st Sample Interrupt Enable
bits : 2 - 4 (3 bit)

ADC_SSCTL2_TS0 : 1st Sample Temp Sensor Select
bits : 3 - 6 (4 bit)

ADC_SSCTL2_D1 : 2nd Sample Diff Input Select
bits : 4 - 8 (5 bit)

ADC_SSCTL2_END1 : 2nd Sample is End of Sequence
bits : 5 - 10 (6 bit)

ADC_SSCTL2_IE1 : 2nd Sample Interrupt Enable
bits : 6 - 12 (7 bit)

ADC_SSCTL2_TS1 : 2nd Sample Temp Sensor Select
bits : 7 - 14 (8 bit)

ADC_SSCTL2_D2 : 3rd Sample Diff Input Select
bits : 8 - 16 (9 bit)

ADC_SSCTL2_END2 : 3rd Sample is End of Sequence
bits : 9 - 18 (10 bit)

ADC_SSCTL2_IE2 : 3rd Sample Interrupt Enable
bits : 10 - 20 (11 bit)

ADC_SSCTL2_TS2 : 3rd Sample Temp Sensor Select
bits : 11 - 22 (12 bit)

ADC_SSCTL2_D3 : 4th Sample Diff Input Select
bits : 12 - 24 (13 bit)

ADC_SSCTL2_END3 : 4th Sample is End of Sequence
bits : 13 - 26 (14 bit)

ADC_SSCTL2_IE3 : 4th Sample Interrupt Enable
bits : 14 - 28 (15 bit)

ADC_SSCTL2_TS3 : 4th Sample Temp Sensor Select
bits : 15 - 30 (16 bit)


SSCTL2

ADC Sample Sequence Control 2
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSCTL2 SSCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSCTL2_D0 ADC_SSCTL2_END0 ADC_SSCTL2_IE0 ADC_SSCTL2_TS0 ADC_SSCTL2_D1 ADC_SSCTL2_END1 ADC_SSCTL2_IE1 ADC_SSCTL2_TS1 ADC_SSCTL2_D2 ADC_SSCTL2_END2 ADC_SSCTL2_IE2 ADC_SSCTL2_TS2 ADC_SSCTL2_D3 ADC_SSCTL2_END3 ADC_SSCTL2_IE3 ADC_SSCTL2_TS3

ADC_SSCTL2_D0 : 1st Sample Diff Input Select
bits : 0 - 0 (1 bit)

ADC_SSCTL2_END0 : 1st Sample is End of Sequence
bits : 1 - 2 (2 bit)

ADC_SSCTL2_IE0 : 1st Sample Interrupt Enable
bits : 2 - 4 (3 bit)

ADC_SSCTL2_TS0 : 1st Sample Temp Sensor Select
bits : 3 - 6 (4 bit)

ADC_SSCTL2_D1 : 2nd Sample Diff Input Select
bits : 4 - 8 (5 bit)

ADC_SSCTL2_END1 : 2nd Sample is End of Sequence
bits : 5 - 10 (6 bit)

ADC_SSCTL2_IE1 : 2nd Sample Interrupt Enable
bits : 6 - 12 (7 bit)

ADC_SSCTL2_TS1 : 2nd Sample Temp Sensor Select
bits : 7 - 14 (8 bit)

ADC_SSCTL2_D2 : 3rd Sample Diff Input Select
bits : 8 - 16 (9 bit)

ADC_SSCTL2_END2 : 3rd Sample is End of Sequence
bits : 9 - 18 (10 bit)

ADC_SSCTL2_IE2 : 3rd Sample Interrupt Enable
bits : 10 - 20 (11 bit)

ADC_SSCTL2_TS2 : 3rd Sample Temp Sensor Select
bits : 11 - 22 (12 bit)

ADC_SSCTL2_D3 : 4th Sample Diff Input Select
bits : 12 - 24 (13 bit)

ADC_SSCTL2_END3 : 4th Sample is End of Sequence
bits : 13 - 26 (14 bit)

ADC_SSCTL2_IE3 : 4th Sample Interrupt Enable
bits : 14 - 28 (15 bit)

ADC_SSCTL2_TS3 : 4th Sample Temp Sensor Select
bits : 15 - 30 (16 bit)


ADC0SSFIFO2

ADC Sample Sequence Result FIFO 2
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSFIFO2 ADC0SSFIFO2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSFIFO2_DATA

ADC_SSFIFO2_DATA : Conversion Result Data
bits : 0 - 9 (10 bit)


SSFIFO2

ADC Sample Sequence Result FIFO 2
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSFIFO2 SSFIFO2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSFIFO2_DATA

ADC_SSFIFO2_DATA : Conversion Result Data
bits : 0 - 9 (10 bit)


ADC0SSFSTAT2

ADC Sample Sequence FIFO 2 Status
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSFSTAT2 ADC0SSFSTAT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSFSTAT2_TPTR ADC_SSFSTAT2_HPTR ADC_SSFSTAT2_EMPTY ADC_SSFSTAT2_FULL

ADC_SSFSTAT2_TPTR : FIFO Tail Pointer
bits : 0 - 3 (4 bit)

ADC_SSFSTAT2_HPTR : FIFO Head Pointer
bits : 4 - 11 (8 bit)

ADC_SSFSTAT2_EMPTY : FIFO Empty
bits : 8 - 16 (9 bit)

ADC_SSFSTAT2_FULL : FIFO Full
bits : 12 - 24 (13 bit)


SSFSTAT2

ADC Sample Sequence FIFO 2 Status
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSFSTAT2 SSFSTAT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSFSTAT2_TPTR ADC_SSFSTAT2_HPTR ADC_SSFSTAT2_EMPTY ADC_SSFSTAT2_FULL

ADC_SSFSTAT2_TPTR : FIFO Tail Pointer
bits : 0 - 3 (4 bit)

ADC_SSFSTAT2_HPTR : FIFO Head Pointer
bits : 4 - 11 (8 bit)

ADC_SSFSTAT2_EMPTY : FIFO Empty
bits : 8 - 16 (9 bit)

ADC_SSFSTAT2_FULL : FIFO Full
bits : 12 - 24 (13 bit)


ADC0SSOP2

ADC Sample Sequence 2 Operation
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSOP2 ADC0SSOP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSOP2_S0DCOP ADC_SSOP2_S1DCOP ADC_SSOP2_S2DCOP ADC_SSOP2_S3DCOP

ADC_SSOP2_S0DCOP : Sample 0 Digital Comparator Operation
bits : 0 - 0 (1 bit)

ADC_SSOP2_S1DCOP : Sample 1 Digital Comparator Operation
bits : 4 - 8 (5 bit)

ADC_SSOP2_S2DCOP : Sample 2 Digital Comparator Operation
bits : 8 - 16 (9 bit)

ADC_SSOP2_S3DCOP : Sample 3 Digital Comparator Operation
bits : 12 - 24 (13 bit)


SSOP2

ADC Sample Sequence 2 Operation
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSOP2 SSOP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSOP2_S0DCOP ADC_SSOP2_S1DCOP ADC_SSOP2_S2DCOP ADC_SSOP2_S3DCOP

ADC_SSOP2_S0DCOP : Sample 0 Digital Comparator Operation
bits : 0 - 0 (1 bit)

ADC_SSOP2_S1DCOP : Sample 1 Digital Comparator Operation
bits : 4 - 8 (5 bit)

ADC_SSOP2_S2DCOP : Sample 2 Digital Comparator Operation
bits : 8 - 16 (9 bit)

ADC_SSOP2_S3DCOP : Sample 3 Digital Comparator Operation
bits : 12 - 24 (13 bit)


ADC0SSDC2

ADC Sample Sequence 2 Digital Comparator Select
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSDC2 ADC0SSDC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSDC2_S0DCSEL ADC_SSDC2_S1DCSEL ADC_SSDC2_S2DCSEL ADC_SSDC2_S3DCSEL

ADC_SSDC2_S0DCSEL : Sample 0 Digital Comparator Select
bits : 0 - 3 (4 bit)

ADC_SSDC2_S1DCSEL : Sample 1 Digital Comparator Select
bits : 4 - 11 (8 bit)

ADC_SSDC2_S2DCSEL : Sample 2 Digital Comparator Select
bits : 8 - 19 (12 bit)

ADC_SSDC2_S3DCSEL : Sample 3 Digital Comparator Select
bits : 12 - 27 (16 bit)


SSDC2

ADC Sample Sequence 2 Digital Comparator Select
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSDC2 SSDC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSDC2_S0DCSEL ADC_SSDC2_S1DCSEL ADC_SSDC2_S2DCSEL ADC_SSDC2_S3DCSEL

ADC_SSDC2_S0DCSEL : Sample 0 Digital Comparator Select
bits : 0 - 3 (4 bit)

ADC_SSDC2_S1DCSEL : Sample 1 Digital Comparator Select
bits : 4 - 11 (8 bit)

ADC_SSDC2_S2DCSEL : Sample 2 Digital Comparator Select
bits : 8 - 19 (12 bit)

ADC_SSDC2_S3DCSEL : Sample 3 Digital Comparator Select
bits : 12 - 27 (16 bit)


ADC0SSMUX3

ADC Sample Sequence Input Multiplexer Select 3
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSMUX3 ADC0SSMUX3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSMUX3_MUX0

ADC_SSMUX3_MUX0 : 1st Sample Input Select
bits : 0 - 2 (3 bit)


SSMUX3

ADC Sample Sequence Input Multiplexer Select 3
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSMUX3 SSMUX3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSMUX3_MUX0

ADC_SSMUX3_MUX0 : 1st Sample Input Select
bits : 0 - 2 (3 bit)


ADC0SSCTL3

ADC Sample Sequence Control 3
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSCTL3 ADC0SSCTL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSCTL3_D0 ADC_SSCTL3_END0 ADC_SSCTL3_IE0 ADC_SSCTL3_TS0

ADC_SSCTL3_D0 : 1st Sample Diff Input Select
bits : 0 - 0 (1 bit)

ADC_SSCTL3_END0 : 1st Sample is End of Sequence
bits : 1 - 2 (2 bit)

ADC_SSCTL3_IE0 : 1st Sample Interrupt Enable
bits : 2 - 4 (3 bit)

ADC_SSCTL3_TS0 : 1st Sample Temp Sensor Select
bits : 3 - 6 (4 bit)


SSCTL3

ADC Sample Sequence Control 3
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSCTL3 SSCTL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSCTL3_D0 ADC_SSCTL3_END0 ADC_SSCTL3_IE0 ADC_SSCTL3_TS0

ADC_SSCTL3_D0 : 1st Sample Diff Input Select
bits : 0 - 0 (1 bit)

ADC_SSCTL3_END0 : 1st Sample is End of Sequence
bits : 1 - 2 (2 bit)

ADC_SSCTL3_IE0 : 1st Sample Interrupt Enable
bits : 2 - 4 (3 bit)

ADC_SSCTL3_TS0 : 1st Sample Temp Sensor Select
bits : 3 - 6 (4 bit)


ADC0SSFIFO3

ADC Sample Sequence Result FIFO 3
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSFIFO3 ADC0SSFIFO3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSFIFO3_DATA

ADC_SSFIFO3_DATA : Conversion Result Data
bits : 0 - 9 (10 bit)


SSFIFO3

ADC Sample Sequence Result FIFO 3
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSFIFO3 SSFIFO3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSFIFO3_DATA

ADC_SSFIFO3_DATA : Conversion Result Data
bits : 0 - 9 (10 bit)


ADC0SSFSTAT3

ADC Sample Sequence FIFO 3 Status
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSFSTAT3 ADC0SSFSTAT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSFSTAT3_TPTR ADC_SSFSTAT3_HPTR ADC_SSFSTAT3_EMPTY ADC_SSFSTAT3_FULL

ADC_SSFSTAT3_TPTR : FIFO Tail Pointer
bits : 0 - 3 (4 bit)

ADC_SSFSTAT3_HPTR : FIFO Head Pointer
bits : 4 - 11 (8 bit)

ADC_SSFSTAT3_EMPTY : FIFO Empty
bits : 8 - 16 (9 bit)

ADC_SSFSTAT3_FULL : FIFO Full
bits : 12 - 24 (13 bit)


SSFSTAT3

ADC Sample Sequence FIFO 3 Status
address_offset : 0xAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSFSTAT3 SSFSTAT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSFSTAT3_TPTR ADC_SSFSTAT3_HPTR ADC_SSFSTAT3_EMPTY ADC_SSFSTAT3_FULL

ADC_SSFSTAT3_TPTR : FIFO Tail Pointer
bits : 0 - 3 (4 bit)

ADC_SSFSTAT3_HPTR : FIFO Head Pointer
bits : 4 - 11 (8 bit)

ADC_SSFSTAT3_EMPTY : FIFO Empty
bits : 8 - 16 (9 bit)

ADC_SSFSTAT3_FULL : FIFO Full
bits : 12 - 24 (13 bit)


ADC0SSOP3

ADC Sample Sequence 3 Operation
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSOP3 ADC0SSOP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSOP3_S0DCOP

ADC_SSOP3_S0DCOP : Sample 0 Digital Comparator Operation
bits : 0 - 0 (1 bit)


SSOP3

ADC Sample Sequence 3 Operation
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSOP3 SSOP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSOP3_S0DCOP

ADC_SSOP3_S0DCOP : Sample 0 Digital Comparator Operation
bits : 0 - 0 (1 bit)


ADC0SSDC3

ADC Sample Sequence 3 Digital Comparator Select
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0SSDC3 ADC0SSDC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSDC3_S0DCSEL

ADC_SSDC3_S0DCSEL : Sample 0 Digital Comparator Select
bits : 0 - 3 (4 bit)


SSDC3

ADC Sample Sequence 3 Digital Comparator Select
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSDC3 SSDC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SSDC3_S0DCSEL

ADC_SSDC3_S0DCSEL : Sample 0 Digital Comparator Select
bits : 0 - 3 (4 bit)


ADC0ISC

ADC Interrupt Status and Clear
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0ISC ADC0ISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_ISC_IN0 ADC_ISC_IN1 ADC_ISC_IN2 ADC_ISC_IN3 ADC_ISC_DCINSS0 ADC_ISC_DCINSS1 ADC_ISC_DCINSS2 ADC_ISC_DCINSS3

ADC_ISC_IN0 : SS0 Interrupt Status and Clear
bits : 0 - 0 (1 bit)

ADC_ISC_IN1 : SS1 Interrupt Status and Clear
bits : 1 - 2 (2 bit)

ADC_ISC_IN2 : SS2 Interrupt Status and Clear
bits : 2 - 4 (3 bit)

ADC_ISC_IN3 : SS3 Interrupt Status and Clear
bits : 3 - 6 (4 bit)

ADC_ISC_DCINSS0 : Digital Comparator Interrupt Status on SS0
bits : 16 - 32 (17 bit)

ADC_ISC_DCINSS1 : Digital Comparator Interrupt Status on SS1
bits : 17 - 34 (18 bit)

ADC_ISC_DCINSS2 : Digital Comparator Interrupt Status on SS2
bits : 18 - 36 (19 bit)

ADC_ISC_DCINSS3 : Digital Comparator Interrupt Status on SS3
bits : 19 - 38 (20 bit)


ISC

ADC Interrupt Status and Clear
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISC ISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_ISC_IN0 ADC_ISC_IN1 ADC_ISC_IN2 ADC_ISC_IN3 ADC_ISC_DCINSS0 ADC_ISC_DCINSS1 ADC_ISC_DCINSS2 ADC_ISC_DCINSS3

ADC_ISC_IN0 : SS0 Interrupt Status and Clear
bits : 0 - 0 (1 bit)

ADC_ISC_IN1 : SS1 Interrupt Status and Clear
bits : 1 - 2 (2 bit)

ADC_ISC_IN2 : SS2 Interrupt Status and Clear
bits : 2 - 4 (3 bit)

ADC_ISC_IN3 : SS3 Interrupt Status and Clear
bits : 3 - 6 (4 bit)

ADC_ISC_DCINSS0 : Digital Comparator Interrupt Status on SS0
bits : 16 - 32 (17 bit)

ADC_ISC_DCINSS1 : Digital Comparator Interrupt Status on SS1
bits : 17 - 34 (18 bit)

ADC_ISC_DCINSS2 : Digital Comparator Interrupt Status on SS2
bits : 18 - 36 (19 bit)

ADC_ISC_DCINSS3 : Digital Comparator Interrupt Status on SS3
bits : 19 - 38 (20 bit)


ADC0DCRIC

ADC Digital Comparator Reset Initial Conditions
address_offset : 0xD00 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0DCRIC ADC0DCRIC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCRIC_DCINT0 ADC_DCRIC_DCINT1 ADC_DCRIC_DCINT2 ADC_DCRIC_DCINT3 ADC_DCRIC_DCINT4 ADC_DCRIC_DCINT5 ADC_DCRIC_DCINT6 ADC_DCRIC_DCINT7 ADC_DCRIC_DCTRIG0 ADC_DCRIC_DCTRIG1 ADC_DCRIC_DCTRIG2 ADC_DCRIC_DCTRIG3 ADC_DCRIC_DCTRIG4 ADC_DCRIC_DCTRIG5 ADC_DCRIC_DCTRIG6 ADC_DCRIC_DCTRIG7

ADC_DCRIC_DCINT0 : Digital Comparator Interrupt 0
bits : 0 - 0 (1 bit)

ADC_DCRIC_DCINT1 : Digital Comparator Interrupt 1
bits : 1 - 2 (2 bit)

ADC_DCRIC_DCINT2 : Digital Comparator Interrupt 2
bits : 2 - 4 (3 bit)

ADC_DCRIC_DCINT3 : Digital Comparator Interrupt 3
bits : 3 - 6 (4 bit)

ADC_DCRIC_DCINT4 : Digital Comparator Interrupt 4
bits : 4 - 8 (5 bit)

ADC_DCRIC_DCINT5 : Digital Comparator Interrupt 5
bits : 5 - 10 (6 bit)

ADC_DCRIC_DCINT6 : Digital Comparator Interrupt 6
bits : 6 - 12 (7 bit)

ADC_DCRIC_DCINT7 : Digital Comparator Interrupt 7
bits : 7 - 14 (8 bit)

ADC_DCRIC_DCTRIG0 : Digital Comparator Trigger 0
bits : 16 - 32 (17 bit)

ADC_DCRIC_DCTRIG1 : Digital Comparator Trigger 1
bits : 17 - 34 (18 bit)

ADC_DCRIC_DCTRIG2 : Digital Comparator Trigger 2
bits : 18 - 36 (19 bit)

ADC_DCRIC_DCTRIG3 : Digital Comparator Trigger 3
bits : 19 - 38 (20 bit)

ADC_DCRIC_DCTRIG4 : Digital Comparator Trigger 4
bits : 20 - 40 (21 bit)

ADC_DCRIC_DCTRIG5 : Digital Comparator Trigger 5
bits : 21 - 42 (22 bit)

ADC_DCRIC_DCTRIG6 : Digital Comparator Trigger 6
bits : 22 - 44 (23 bit)

ADC_DCRIC_DCTRIG7 : Digital Comparator Trigger 7
bits : 23 - 46 (24 bit)


DCRIC

ADC Digital Comparator Reset Initial Conditions
address_offset : 0xD00 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCRIC DCRIC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCRIC_DCINT0 ADC_DCRIC_DCINT1 ADC_DCRIC_DCINT2 ADC_DCRIC_DCINT3 ADC_DCRIC_DCINT4 ADC_DCRIC_DCINT5 ADC_DCRIC_DCINT6 ADC_DCRIC_DCINT7 ADC_DCRIC_DCTRIG0 ADC_DCRIC_DCTRIG1 ADC_DCRIC_DCTRIG2 ADC_DCRIC_DCTRIG3 ADC_DCRIC_DCTRIG4 ADC_DCRIC_DCTRIG5 ADC_DCRIC_DCTRIG6 ADC_DCRIC_DCTRIG7

ADC_DCRIC_DCINT0 : Digital Comparator Interrupt 0
bits : 0 - 0 (1 bit)

ADC_DCRIC_DCINT1 : Digital Comparator Interrupt 1
bits : 1 - 2 (2 bit)

ADC_DCRIC_DCINT2 : Digital Comparator Interrupt 2
bits : 2 - 4 (3 bit)

ADC_DCRIC_DCINT3 : Digital Comparator Interrupt 3
bits : 3 - 6 (4 bit)

ADC_DCRIC_DCINT4 : Digital Comparator Interrupt 4
bits : 4 - 8 (5 bit)

ADC_DCRIC_DCINT5 : Digital Comparator Interrupt 5
bits : 5 - 10 (6 bit)

ADC_DCRIC_DCINT6 : Digital Comparator Interrupt 6
bits : 6 - 12 (7 bit)

ADC_DCRIC_DCINT7 : Digital Comparator Interrupt 7
bits : 7 - 14 (8 bit)

ADC_DCRIC_DCTRIG0 : Digital Comparator Trigger 0
bits : 16 - 32 (17 bit)

ADC_DCRIC_DCTRIG1 : Digital Comparator Trigger 1
bits : 17 - 34 (18 bit)

ADC_DCRIC_DCTRIG2 : Digital Comparator Trigger 2
bits : 18 - 36 (19 bit)

ADC_DCRIC_DCTRIG3 : Digital Comparator Trigger 3
bits : 19 - 38 (20 bit)

ADC_DCRIC_DCTRIG4 : Digital Comparator Trigger 4
bits : 20 - 40 (21 bit)

ADC_DCRIC_DCTRIG5 : Digital Comparator Trigger 5
bits : 21 - 42 (22 bit)

ADC_DCRIC_DCTRIG6 : Digital Comparator Trigger 6
bits : 22 - 44 (23 bit)

ADC_DCRIC_DCTRIG7 : Digital Comparator Trigger 7
bits : 23 - 46 (24 bit)


ADC0DCCTL0

ADC Digital Comparator Control 0
address_offset : 0xE00 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0DCCTL0 ADC0DCCTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCTL0_CIM ADC_DCCTL0_CIC ADC_DCCTL0_CIE ADC_DCCTL0_CTM ADC_DCCTL0_CTC ADC_DCCTL0_CTE

ADC_DCCTL0_CIM : Comparison Interrupt Mode
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : ADC_DCCTL0_CIM_ALWAYS

Always

0x1 : ADC_DCCTL0_CIM_ONCE

Once

0x2 : ADC_DCCTL0_CIM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL0_CIM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL0_CIC : Comparison Interrupt Condition
bits : 2 - 5 (4 bit)

Enumeration:

0x0 : ADC_DCCTL0_CIC_LOW

Low Band

0x1 : ADC_DCCTL0_CIC_MID

Mid Band

0x3 : ADC_DCCTL0_CIC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL0_CIE : Comparison Interrupt Enable
bits : 4 - 8 (5 bit)

ADC_DCCTL0_CTM : Comparison Trigger Mode
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : ADC_DCCTL0_CTM_ALWAYS

Always

0x1 : ADC_DCCTL0_CTM_ONCE

Once

0x2 : ADC_DCCTL0_CTM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL0_CTM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL0_CTC : Comparison Trigger Condition
bits : 10 - 21 (12 bit)

Enumeration:

0x0 : ADC_DCCTL0_CTC_LOW

Low Band

0x1 : ADC_DCCTL0_CTC_MID

Mid Band

0x3 : ADC_DCCTL0_CTC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL0_CTE : Comparison Trigger Enable
bits : 12 - 24 (13 bit)


DCCTL0

ADC Digital Comparator Control 0
address_offset : 0xE00 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCCTL0 DCCTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCTL0_CIM ADC_DCCTL0_CIC ADC_DCCTL0_CIE ADC_DCCTL0_CTM ADC_DCCTL0_CTC ADC_DCCTL0_CTE

ADC_DCCTL0_CIM : Comparison Interrupt Mode
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : ADC_DCCTL0_CIM_ALWAYS

Always

0x1 : ADC_DCCTL0_CIM_ONCE

Once

0x2 : ADC_DCCTL0_CIM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL0_CIM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL0_CIC : Comparison Interrupt Condition
bits : 2 - 5 (4 bit)

Enumeration:

0x0 : ADC_DCCTL0_CIC_LOW

Low Band

0x1 : ADC_DCCTL0_CIC_MID

Mid Band

0x3 : ADC_DCCTL0_CIC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL0_CIE : Comparison Interrupt Enable
bits : 4 - 8 (5 bit)

ADC_DCCTL0_CTM : Comparison Trigger Mode
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : ADC_DCCTL0_CTM_ALWAYS

Always

0x1 : ADC_DCCTL0_CTM_ONCE

Once

0x2 : ADC_DCCTL0_CTM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL0_CTM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL0_CTC : Comparison Trigger Condition
bits : 10 - 21 (12 bit)

Enumeration:

0x0 : ADC_DCCTL0_CTC_LOW

Low Band

0x1 : ADC_DCCTL0_CTC_MID

Mid Band

0x3 : ADC_DCCTL0_CTC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL0_CTE : Comparison Trigger Enable
bits : 12 - 24 (13 bit)


ADC0DCCTL1

ADC Digital Comparator Control 1
address_offset : 0xE04 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0DCCTL1 ADC0DCCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCTL1_CIM ADC_DCCTL1_CIC ADC_DCCTL1_CIE ADC_DCCTL1_CTM ADC_DCCTL1_CTC ADC_DCCTL1_CTE

ADC_DCCTL1_CIM : Comparison Interrupt Mode
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : ADC_DCCTL1_CIM_ALWAYS

Always

0x1 : ADC_DCCTL1_CIM_ONCE

Once

0x2 : ADC_DCCTL1_CIM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL1_CIM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL1_CIC : Comparison Interrupt Condition
bits : 2 - 5 (4 bit)

Enumeration:

0x0 : ADC_DCCTL1_CIC_LOW

Low Band

0x1 : ADC_DCCTL1_CIC_MID

Mid Band

0x3 : ADC_DCCTL1_CIC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL1_CIE : Comparison Interrupt Enable
bits : 4 - 8 (5 bit)

ADC_DCCTL1_CTM : Comparison Trigger Mode
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : ADC_DCCTL1_CTM_ALWAYS

Always

0x1 : ADC_DCCTL1_CTM_ONCE

Once

0x2 : ADC_DCCTL1_CTM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL1_CTM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL1_CTC : Comparison Trigger Condition
bits : 10 - 21 (12 bit)

Enumeration:

0x0 : ADC_DCCTL1_CTC_LOW

Low Band

0x1 : ADC_DCCTL1_CTC_MID

Mid Band

0x3 : ADC_DCCTL1_CTC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL1_CTE : Comparison Trigger Enable
bits : 12 - 24 (13 bit)


DCCTL1

ADC Digital Comparator Control 1
address_offset : 0xE04 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCCTL1 DCCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCTL1_CIM ADC_DCCTL1_CIC ADC_DCCTL1_CIE ADC_DCCTL1_CTM ADC_DCCTL1_CTC ADC_DCCTL1_CTE

ADC_DCCTL1_CIM : Comparison Interrupt Mode
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : ADC_DCCTL1_CIM_ALWAYS

Always

0x1 : ADC_DCCTL1_CIM_ONCE

Once

0x2 : ADC_DCCTL1_CIM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL1_CIM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL1_CIC : Comparison Interrupt Condition
bits : 2 - 5 (4 bit)

Enumeration:

0x0 : ADC_DCCTL1_CIC_LOW

Low Band

0x1 : ADC_DCCTL1_CIC_MID

Mid Band

0x3 : ADC_DCCTL1_CIC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL1_CIE : Comparison Interrupt Enable
bits : 4 - 8 (5 bit)

ADC_DCCTL1_CTM : Comparison Trigger Mode
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : ADC_DCCTL1_CTM_ALWAYS

Always

0x1 : ADC_DCCTL1_CTM_ONCE

Once

0x2 : ADC_DCCTL1_CTM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL1_CTM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL1_CTC : Comparison Trigger Condition
bits : 10 - 21 (12 bit)

Enumeration:

0x0 : ADC_DCCTL1_CTC_LOW

Low Band

0x1 : ADC_DCCTL1_CTC_MID

Mid Band

0x3 : ADC_DCCTL1_CTC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL1_CTE : Comparison Trigger Enable
bits : 12 - 24 (13 bit)


ADC0DCCTL2

ADC Digital Comparator Control 2
address_offset : 0xE08 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0DCCTL2 ADC0DCCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCTL2_CIM ADC_DCCTL2_CIC ADC_DCCTL2_CIE ADC_DCCTL2_CTM ADC_DCCTL2_CTC ADC_DCCTL2_CTE

ADC_DCCTL2_CIM : Comparison Interrupt Mode
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : ADC_DCCTL2_CIM_ALWAYS

Always

0x1 : ADC_DCCTL2_CIM_ONCE

Once

0x2 : ADC_DCCTL2_CIM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL2_CIM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL2_CIC : Comparison Interrupt Condition
bits : 2 - 5 (4 bit)

Enumeration:

0x0 : ADC_DCCTL2_CIC_LOW

Low Band

0x1 : ADC_DCCTL2_CIC_MID

Mid Band

0x3 : ADC_DCCTL2_CIC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL2_CIE : Comparison Interrupt Enable
bits : 4 - 8 (5 bit)

ADC_DCCTL2_CTM : Comparison Trigger Mode
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : ADC_DCCTL2_CTM_ALWAYS

Always

0x1 : ADC_DCCTL2_CTM_ONCE

Once

0x2 : ADC_DCCTL2_CTM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL2_CTM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL2_CTC : Comparison Trigger Condition
bits : 10 - 21 (12 bit)

Enumeration:

0x0 : ADC_DCCTL2_CTC_LOW

Low Band

0x1 : ADC_DCCTL2_CTC_MID

Mid Band

0x3 : ADC_DCCTL2_CTC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL2_CTE : Comparison Trigger Enable
bits : 12 - 24 (13 bit)


DCCTL2

ADC Digital Comparator Control 2
address_offset : 0xE08 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCCTL2 DCCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCTL2_CIM ADC_DCCTL2_CIC ADC_DCCTL2_CIE ADC_DCCTL2_CTM ADC_DCCTL2_CTC ADC_DCCTL2_CTE

ADC_DCCTL2_CIM : Comparison Interrupt Mode
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : ADC_DCCTL2_CIM_ALWAYS

Always

0x1 : ADC_DCCTL2_CIM_ONCE

Once

0x2 : ADC_DCCTL2_CIM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL2_CIM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL2_CIC : Comparison Interrupt Condition
bits : 2 - 5 (4 bit)

Enumeration:

0x0 : ADC_DCCTL2_CIC_LOW

Low Band

0x1 : ADC_DCCTL2_CIC_MID

Mid Band

0x3 : ADC_DCCTL2_CIC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL2_CIE : Comparison Interrupt Enable
bits : 4 - 8 (5 bit)

ADC_DCCTL2_CTM : Comparison Trigger Mode
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : ADC_DCCTL2_CTM_ALWAYS

Always

0x1 : ADC_DCCTL2_CTM_ONCE

Once

0x2 : ADC_DCCTL2_CTM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL2_CTM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL2_CTC : Comparison Trigger Condition
bits : 10 - 21 (12 bit)

Enumeration:

0x0 : ADC_DCCTL2_CTC_LOW

Low Band

0x1 : ADC_DCCTL2_CTC_MID

Mid Band

0x3 : ADC_DCCTL2_CTC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL2_CTE : Comparison Trigger Enable
bits : 12 - 24 (13 bit)


ADC0DCCTL3

ADC Digital Comparator Control 3
address_offset : 0xE0C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0DCCTL3 ADC0DCCTL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCTL3_CIM ADC_DCCTL3_CIC ADC_DCCTL3_CIE ADC_DCCTL3_CTM ADC_DCCTL3_CTC ADC_DCCTL3_CTE

ADC_DCCTL3_CIM : Comparison Interrupt Mode
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : ADC_DCCTL3_CIM_ALWAYS

Always

0x1 : ADC_DCCTL3_CIM_ONCE

Once

0x2 : ADC_DCCTL3_CIM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL3_CIM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL3_CIC : Comparison Interrupt Condition
bits : 2 - 5 (4 bit)

Enumeration:

0x0 : ADC_DCCTL3_CIC_LOW

Low Band

0x1 : ADC_DCCTL3_CIC_MID

Mid Band

0x3 : ADC_DCCTL3_CIC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL3_CIE : Comparison Interrupt Enable
bits : 4 - 8 (5 bit)

ADC_DCCTL3_CTM : Comparison Trigger Mode
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : ADC_DCCTL3_CTM_ALWAYS

Always

0x1 : ADC_DCCTL3_CTM_ONCE

Once

0x2 : ADC_DCCTL3_CTM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL3_CTM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL3_CTC : Comparison Trigger Condition
bits : 10 - 21 (12 bit)

Enumeration:

0x0 : ADC_DCCTL3_CTC_LOW

Low Band

0x1 : ADC_DCCTL3_CTC_MID

Mid Band

0x3 : ADC_DCCTL3_CTC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL3_CTE : Comparison Trigger Enable
bits : 12 - 24 (13 bit)


DCCTL3

ADC Digital Comparator Control 3
address_offset : 0xE0C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCCTL3 DCCTL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCTL3_CIM ADC_DCCTL3_CIC ADC_DCCTL3_CIE ADC_DCCTL3_CTM ADC_DCCTL3_CTC ADC_DCCTL3_CTE

ADC_DCCTL3_CIM : Comparison Interrupt Mode
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : ADC_DCCTL3_CIM_ALWAYS

Always

0x1 : ADC_DCCTL3_CIM_ONCE

Once

0x2 : ADC_DCCTL3_CIM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL3_CIM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL3_CIC : Comparison Interrupt Condition
bits : 2 - 5 (4 bit)

Enumeration:

0x0 : ADC_DCCTL3_CIC_LOW

Low Band

0x1 : ADC_DCCTL3_CIC_MID

Mid Band

0x3 : ADC_DCCTL3_CIC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL3_CIE : Comparison Interrupt Enable
bits : 4 - 8 (5 bit)

ADC_DCCTL3_CTM : Comparison Trigger Mode
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : ADC_DCCTL3_CTM_ALWAYS

Always

0x1 : ADC_DCCTL3_CTM_ONCE

Once

0x2 : ADC_DCCTL3_CTM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL3_CTM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL3_CTC : Comparison Trigger Condition
bits : 10 - 21 (12 bit)

Enumeration:

0x0 : ADC_DCCTL3_CTC_LOW

Low Band

0x1 : ADC_DCCTL3_CTC_MID

Mid Band

0x3 : ADC_DCCTL3_CTC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL3_CTE : Comparison Trigger Enable
bits : 12 - 24 (13 bit)


ADC0DCCTL4

ADC Digital Comparator Control 4
address_offset : 0xE10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0DCCTL4 ADC0DCCTL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCTL4_CIM ADC_DCCTL4_CIC ADC_DCCTL4_CIE ADC_DCCTL4_CTM ADC_DCCTL4_CTC ADC_DCCTL4_CTE

ADC_DCCTL4_CIM : Comparison Interrupt Mode
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : ADC_DCCTL4_CIM_ALWAYS

Always

0x1 : ADC_DCCTL4_CIM_ONCE

Once

0x2 : ADC_DCCTL4_CIM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL4_CIM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL4_CIC : Comparison Interrupt Condition
bits : 2 - 5 (4 bit)

Enumeration:

0x0 : ADC_DCCTL4_CIC_LOW

Low Band

0x1 : ADC_DCCTL4_CIC_MID

Mid Band

0x3 : ADC_DCCTL4_CIC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL4_CIE : Comparison Interrupt Enable
bits : 4 - 8 (5 bit)

ADC_DCCTL4_CTM : Comparison Trigger Mode
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : ADC_DCCTL4_CTM_ALWAYS

Always

0x1 : ADC_DCCTL4_CTM_ONCE

Once

0x2 : ADC_DCCTL4_CTM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL4_CTM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL4_CTC : Comparison Trigger Condition
bits : 10 - 21 (12 bit)

Enumeration:

0x0 : ADC_DCCTL4_CTC_LOW

Low Band

0x1 : ADC_DCCTL4_CTC_MID

Mid Band

0x3 : ADC_DCCTL4_CTC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL4_CTE : Comparison Trigger Enable
bits : 12 - 24 (13 bit)


DCCTL4

ADC Digital Comparator Control 4
address_offset : 0xE10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCCTL4 DCCTL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCTL4_CIM ADC_DCCTL4_CIC ADC_DCCTL4_CIE ADC_DCCTL4_CTM ADC_DCCTL4_CTC ADC_DCCTL4_CTE

ADC_DCCTL4_CIM : Comparison Interrupt Mode
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : ADC_DCCTL4_CIM_ALWAYS

Always

0x1 : ADC_DCCTL4_CIM_ONCE

Once

0x2 : ADC_DCCTL4_CIM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL4_CIM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL4_CIC : Comparison Interrupt Condition
bits : 2 - 5 (4 bit)

Enumeration:

0x0 : ADC_DCCTL4_CIC_LOW

Low Band

0x1 : ADC_DCCTL4_CIC_MID

Mid Band

0x3 : ADC_DCCTL4_CIC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL4_CIE : Comparison Interrupt Enable
bits : 4 - 8 (5 bit)

ADC_DCCTL4_CTM : Comparison Trigger Mode
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : ADC_DCCTL4_CTM_ALWAYS

Always

0x1 : ADC_DCCTL4_CTM_ONCE

Once

0x2 : ADC_DCCTL4_CTM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL4_CTM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL4_CTC : Comparison Trigger Condition
bits : 10 - 21 (12 bit)

Enumeration:

0x0 : ADC_DCCTL4_CTC_LOW

Low Band

0x1 : ADC_DCCTL4_CTC_MID

Mid Band

0x3 : ADC_DCCTL4_CTC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL4_CTE : Comparison Trigger Enable
bits : 12 - 24 (13 bit)


ADC0DCCTL5

ADC Digital Comparator Control 5
address_offset : 0xE14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0DCCTL5 ADC0DCCTL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCTL5_CIM ADC_DCCTL5_CIC ADC_DCCTL5_CIE ADC_DCCTL5_CTM ADC_DCCTL5_CTC ADC_DCCTL5_CTE

ADC_DCCTL5_CIM : Comparison Interrupt Mode
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : ADC_DCCTL5_CIM_ALWAYS

Always

0x1 : ADC_DCCTL5_CIM_ONCE

Once

0x2 : ADC_DCCTL5_CIM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL5_CIM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL5_CIC : Comparison Interrupt Condition
bits : 2 - 5 (4 bit)

Enumeration:

0x0 : ADC_DCCTL5_CIC_LOW

Low Band

0x1 : ADC_DCCTL5_CIC_MID

Mid Band

0x3 : ADC_DCCTL5_CIC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL5_CIE : Comparison Interrupt Enable
bits : 4 - 8 (5 bit)

ADC_DCCTL5_CTM : Comparison Trigger Mode
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : ADC_DCCTL5_CTM_ALWAYS

Always

0x1 : ADC_DCCTL5_CTM_ONCE

Once

0x2 : ADC_DCCTL5_CTM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL5_CTM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL5_CTC : Comparison Trigger Condition
bits : 10 - 21 (12 bit)

Enumeration:

0x0 : ADC_DCCTL5_CTC_LOW

Low Band

0x1 : ADC_DCCTL5_CTC_MID

Mid Band

0x3 : ADC_DCCTL5_CTC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL5_CTE : Comparison Trigger Enable
bits : 12 - 24 (13 bit)


DCCTL5

ADC Digital Comparator Control 5
address_offset : 0xE14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCCTL5 DCCTL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCTL5_CIM ADC_DCCTL5_CIC ADC_DCCTL5_CIE ADC_DCCTL5_CTM ADC_DCCTL5_CTC ADC_DCCTL5_CTE

ADC_DCCTL5_CIM : Comparison Interrupt Mode
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : ADC_DCCTL5_CIM_ALWAYS

Always

0x1 : ADC_DCCTL5_CIM_ONCE

Once

0x2 : ADC_DCCTL5_CIM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL5_CIM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL5_CIC : Comparison Interrupt Condition
bits : 2 - 5 (4 bit)

Enumeration:

0x0 : ADC_DCCTL5_CIC_LOW

Low Band

0x1 : ADC_DCCTL5_CIC_MID

Mid Band

0x3 : ADC_DCCTL5_CIC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL5_CIE : Comparison Interrupt Enable
bits : 4 - 8 (5 bit)

ADC_DCCTL5_CTM : Comparison Trigger Mode
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : ADC_DCCTL5_CTM_ALWAYS

Always

0x1 : ADC_DCCTL5_CTM_ONCE

Once

0x2 : ADC_DCCTL5_CTM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL5_CTM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL5_CTC : Comparison Trigger Condition
bits : 10 - 21 (12 bit)

Enumeration:

0x0 : ADC_DCCTL5_CTC_LOW

Low Band

0x1 : ADC_DCCTL5_CTC_MID

Mid Band

0x3 : ADC_DCCTL5_CTC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL5_CTE : Comparison Trigger Enable
bits : 12 - 24 (13 bit)


ADC0DCCTL6

ADC Digital Comparator Control 6
address_offset : 0xE18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0DCCTL6 ADC0DCCTL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCTL6_CIM ADC_DCCTL6_CIC ADC_DCCTL6_CIE ADC_DCCTL6_CTM ADC_DCCTL6_CTC ADC_DCCTL6_CTE

ADC_DCCTL6_CIM : Comparison Interrupt Mode
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : ADC_DCCTL6_CIM_ALWAYS

Always

0x1 : ADC_DCCTL6_CIM_ONCE

Once

0x2 : ADC_DCCTL6_CIM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL6_CIM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL6_CIC : Comparison Interrupt Condition
bits : 2 - 5 (4 bit)

Enumeration:

0x0 : ADC_DCCTL6_CIC_LOW

Low Band

0x1 : ADC_DCCTL6_CIC_MID

Mid Band

0x3 : ADC_DCCTL6_CIC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL6_CIE : Comparison Interrupt Enable
bits : 4 - 8 (5 bit)

ADC_DCCTL6_CTM : Comparison Trigger Mode
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : ADC_DCCTL6_CTM_ALWAYS

Always

0x1 : ADC_DCCTL6_CTM_ONCE

Once

0x2 : ADC_DCCTL6_CTM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL6_CTM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL6_CTC : Comparison Trigger Condition
bits : 10 - 21 (12 bit)

Enumeration:

0x0 : ADC_DCCTL6_CTC_LOW

Low Band

0x1 : ADC_DCCTL6_CTC_MID

Mid Band

0x3 : ADC_DCCTL6_CTC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL6_CTE : Comparison Trigger Enable
bits : 12 - 24 (13 bit)


DCCTL6

ADC Digital Comparator Control 6
address_offset : 0xE18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCCTL6 DCCTL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCTL6_CIM ADC_DCCTL6_CIC ADC_DCCTL6_CIE ADC_DCCTL6_CTM ADC_DCCTL6_CTC ADC_DCCTL6_CTE

ADC_DCCTL6_CIM : Comparison Interrupt Mode
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : ADC_DCCTL6_CIM_ALWAYS

Always

0x1 : ADC_DCCTL6_CIM_ONCE

Once

0x2 : ADC_DCCTL6_CIM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL6_CIM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL6_CIC : Comparison Interrupt Condition
bits : 2 - 5 (4 bit)

Enumeration:

0x0 : ADC_DCCTL6_CIC_LOW

Low Band

0x1 : ADC_DCCTL6_CIC_MID

Mid Band

0x3 : ADC_DCCTL6_CIC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL6_CIE : Comparison Interrupt Enable
bits : 4 - 8 (5 bit)

ADC_DCCTL6_CTM : Comparison Trigger Mode
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : ADC_DCCTL6_CTM_ALWAYS

Always

0x1 : ADC_DCCTL6_CTM_ONCE

Once

0x2 : ADC_DCCTL6_CTM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL6_CTM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL6_CTC : Comparison Trigger Condition
bits : 10 - 21 (12 bit)

Enumeration:

0x0 : ADC_DCCTL6_CTC_LOW

Low Band

0x1 : ADC_DCCTL6_CTC_MID

Mid Band

0x3 : ADC_DCCTL6_CTC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL6_CTE : Comparison Trigger Enable
bits : 12 - 24 (13 bit)


ADC0DCCTL7

ADC Digital Comparator Control 7
address_offset : 0xE1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0DCCTL7 ADC0DCCTL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCTL7_CIM ADC_DCCTL7_CIC ADC_DCCTL7_CIE ADC_DCCTL7_CTM ADC_DCCTL7_CTC ADC_DCCTL7_CTE

ADC_DCCTL7_CIM : Comparison Interrupt Mode
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : ADC_DCCTL7_CIM_ALWAYS

Always

0x1 : ADC_DCCTL7_CIM_ONCE

Once

0x2 : ADC_DCCTL7_CIM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL7_CIM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL7_CIC : Comparison Interrupt Condition
bits : 2 - 5 (4 bit)

Enumeration:

0x0 : ADC_DCCTL7_CIC_LOW

Low Band

0x1 : ADC_DCCTL7_CIC_MID

Mid Band

0x3 : ADC_DCCTL7_CIC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL7_CIE : Comparison Interrupt Enable
bits : 4 - 8 (5 bit)

ADC_DCCTL7_CTM : Comparison Trigger Mode
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : ADC_DCCTL7_CTM_ALWAYS

Always

0x1 : ADC_DCCTL7_CTM_ONCE

Once

0x2 : ADC_DCCTL7_CTM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL7_CTM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL7_CTC : Comparison Trigger Condition
bits : 10 - 21 (12 bit)

Enumeration:

0x0 : ADC_DCCTL7_CTC_LOW

Low Band

0x1 : ADC_DCCTL7_CTC_MID

Mid Band

0x3 : ADC_DCCTL7_CTC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL7_CTE : Comparison Trigger Enable
bits : 12 - 24 (13 bit)


DCCTL7

ADC Digital Comparator Control 7
address_offset : 0xE1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCCTL7 DCCTL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCTL7_CIM ADC_DCCTL7_CIC ADC_DCCTL7_CIE ADC_DCCTL7_CTM ADC_DCCTL7_CTC ADC_DCCTL7_CTE

ADC_DCCTL7_CIM : Comparison Interrupt Mode
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : ADC_DCCTL7_CIM_ALWAYS

Always

0x1 : ADC_DCCTL7_CIM_ONCE

Once

0x2 : ADC_DCCTL7_CIM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL7_CIM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL7_CIC : Comparison Interrupt Condition
bits : 2 - 5 (4 bit)

Enumeration:

0x0 : ADC_DCCTL7_CIC_LOW

Low Band

0x1 : ADC_DCCTL7_CIC_MID

Mid Band

0x3 : ADC_DCCTL7_CIC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL7_CIE : Comparison Interrupt Enable
bits : 4 - 8 (5 bit)

ADC_DCCTL7_CTM : Comparison Trigger Mode
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : ADC_DCCTL7_CTM_ALWAYS

Always

0x1 : ADC_DCCTL7_CTM_ONCE

Once

0x2 : ADC_DCCTL7_CTM_HALWAYS

Hysteresis Always

0x3 : ADC_DCCTL7_CTM_HONCE

Hysteresis Once

End of enumeration elements list.

ADC_DCCTL7_CTC : Comparison Trigger Condition
bits : 10 - 21 (12 bit)

Enumeration:

0x0 : ADC_DCCTL7_CTC_LOW

Low Band

0x1 : ADC_DCCTL7_CTC_MID

Mid Band

0x3 : ADC_DCCTL7_CTC_HIGH

High Band

End of enumeration elements list.

ADC_DCCTL7_CTE : Comparison Trigger Enable
bits : 12 - 24 (13 bit)


ADC0DCCMP0

ADC Digital Comparator Range 0
address_offset : 0xE40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0DCCMP0 ADC0DCCMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCMP0_COMP0 ADC_DCCMP0_COMP1

ADC_DCCMP0_COMP0 : Compare 0
bits : 0 - 9 (10 bit)

ADC_DCCMP0_COMP1 : Compare 1
bits : 16 - 41 (26 bit)


DCCMP0

ADC Digital Comparator Range 0
address_offset : 0xE40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCCMP0 DCCMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCMP0_COMP0 ADC_DCCMP0_COMP1

ADC_DCCMP0_COMP0 : Compare 0
bits : 0 - 9 (10 bit)

ADC_DCCMP0_COMP1 : Compare 1
bits : 16 - 41 (26 bit)


ADC0DCCMP1

ADC Digital Comparator Range 1
address_offset : 0xE44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0DCCMP1 ADC0DCCMP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCMP1_COMP0 ADC_DCCMP1_COMP1

ADC_DCCMP1_COMP0 : Compare 0
bits : 0 - 9 (10 bit)

ADC_DCCMP1_COMP1 : Compare 1
bits : 16 - 41 (26 bit)


DCCMP1

ADC Digital Comparator Range 1
address_offset : 0xE44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCCMP1 DCCMP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCMP1_COMP0 ADC_DCCMP1_COMP1

ADC_DCCMP1_COMP0 : Compare 0
bits : 0 - 9 (10 bit)

ADC_DCCMP1_COMP1 : Compare 1
bits : 16 - 41 (26 bit)


ADC0DCCMP2

ADC Digital Comparator Range 2
address_offset : 0xE48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0DCCMP2 ADC0DCCMP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCMP2_COMP0 ADC_DCCMP2_COMP1

ADC_DCCMP2_COMP0 : Compare 0
bits : 0 - 9 (10 bit)

ADC_DCCMP2_COMP1 : Compare 1
bits : 16 - 41 (26 bit)


DCCMP2

ADC Digital Comparator Range 2
address_offset : 0xE48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCCMP2 DCCMP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCMP2_COMP0 ADC_DCCMP2_COMP1

ADC_DCCMP2_COMP0 : Compare 0
bits : 0 - 9 (10 bit)

ADC_DCCMP2_COMP1 : Compare 1
bits : 16 - 41 (26 bit)


ADC0DCCMP3

ADC Digital Comparator Range 3
address_offset : 0xE4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0DCCMP3 ADC0DCCMP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCMP3_COMP0 ADC_DCCMP3_COMP1

ADC_DCCMP3_COMP0 : Compare 0
bits : 0 - 9 (10 bit)

ADC_DCCMP3_COMP1 : Compare 1
bits : 16 - 41 (26 bit)


DCCMP3

ADC Digital Comparator Range 3
address_offset : 0xE4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCCMP3 DCCMP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCMP3_COMP0 ADC_DCCMP3_COMP1

ADC_DCCMP3_COMP0 : Compare 0
bits : 0 - 9 (10 bit)

ADC_DCCMP3_COMP1 : Compare 1
bits : 16 - 41 (26 bit)


ADC0DCCMP4

ADC Digital Comparator Range 4
address_offset : 0xE50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0DCCMP4 ADC0DCCMP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCMP4_COMP0 ADC_DCCMP4_COMP1

ADC_DCCMP4_COMP0 : Compare 0
bits : 0 - 9 (10 bit)

ADC_DCCMP4_COMP1 : Compare 1
bits : 16 - 41 (26 bit)


DCCMP4

ADC Digital Comparator Range 4
address_offset : 0xE50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCCMP4 DCCMP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCMP4_COMP0 ADC_DCCMP4_COMP1

ADC_DCCMP4_COMP0 : Compare 0
bits : 0 - 9 (10 bit)

ADC_DCCMP4_COMP1 : Compare 1
bits : 16 - 41 (26 bit)


ADC0DCCMP5

ADC Digital Comparator Range 5
address_offset : 0xE54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0DCCMP5 ADC0DCCMP5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCMP5_COMP0 ADC_DCCMP5_COMP1

ADC_DCCMP5_COMP0 : Compare 0
bits : 0 - 9 (10 bit)

ADC_DCCMP5_COMP1 : Compare 1
bits : 16 - 41 (26 bit)


DCCMP5

ADC Digital Comparator Range 5
address_offset : 0xE54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCCMP5 DCCMP5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCMP5_COMP0 ADC_DCCMP5_COMP1

ADC_DCCMP5_COMP0 : Compare 0
bits : 0 - 9 (10 bit)

ADC_DCCMP5_COMP1 : Compare 1
bits : 16 - 41 (26 bit)


ADC0DCCMP6

ADC Digital Comparator Range 6
address_offset : 0xE58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0DCCMP6 ADC0DCCMP6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCMP6_COMP0 ADC_DCCMP6_COMP1

ADC_DCCMP6_COMP0 : Compare 0
bits : 0 - 9 (10 bit)

ADC_DCCMP6_COMP1 : Compare 1
bits : 16 - 41 (26 bit)


DCCMP6

ADC Digital Comparator Range 6
address_offset : 0xE58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCCMP6 DCCMP6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCMP6_COMP0 ADC_DCCMP6_COMP1

ADC_DCCMP6_COMP0 : Compare 0
bits : 0 - 9 (10 bit)

ADC_DCCMP6_COMP1 : Compare 1
bits : 16 - 41 (26 bit)


ADC0DCCMP7

ADC Digital Comparator Range 7
address_offset : 0xE5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0DCCMP7 ADC0DCCMP7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCMP7_COMP0 ADC_DCCMP7_COMP1

ADC_DCCMP7_COMP0 : Compare 0
bits : 0 - 9 (10 bit)

ADC_DCCMP7_COMP1 : Compare 1
bits : 16 - 41 (26 bit)


DCCMP7

ADC Digital Comparator Range 7
address_offset : 0xE5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCCMP7 DCCMP7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_DCCMP7_COMP0 ADC_DCCMP7_COMP1

ADC_DCCMP7_COMP0 : Compare 0
bits : 0 - 9 (10 bit)

ADC_DCCMP7_COMP1 : Compare 1
bits : 16 - 41 (26 bit)



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