\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
DMA Status
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_STAT_MASTEN : Master Enable Status
bits : 0 - 0 (1 bit)
UDMA_STAT_STATE : Control State Machine Status
bits : 4 - 11 (8 bit)
Enumeration:
0x0 : UDMA_STAT_STATE_IDLE
Idle
0x1 : UDMA_STAT_STATE_RD_CTRL
Reading channel controller data
0x2 : UDMA_STAT_STATE_RD_SRCENDP
Reading source end pointer
0x3 : UDMA_STAT_STATE_RD_DSTENDP
Reading destination end pointer
0x4 : UDMA_STAT_STATE_RD_SRCDAT
Reading source data
0x5 : UDMA_STAT_STATE_WR_DSTDAT
Writing destination data
0x6 : UDMA_STAT_STATE_WAIT
Waiting for uDMA request to clear
0x7 : UDMA_STAT_STATE_WR_CTRL
Writing channel controller data
0x8 : UDMA_STAT_STATE_STALL
Stalled
0x9 : UDMA_STAT_STATE_DONE
Done
0xa : UDMA_STAT_STATE_UNDEF
Undefined
End of enumeration elements list.
UDMA_STAT_DMACHANS : Available uDMA Channels Minus 1
bits : 16 - 36 (21 bit)
DMA Status
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_STAT_MASTEN : Master Enable Status
bits : 0 - 0 (1 bit)
UDMA_STAT_STATE : Control State Machine Status
bits : 4 - 11 (8 bit)
Enumeration:
0x0 : UDMA_STAT_STATE_IDLE
Idle
0x1 : UDMA_STAT_STATE_RD_CTRL
Reading channel controller data
0x2 : UDMA_STAT_STATE_RD_SRCENDP
Reading source end pointer
0x3 : UDMA_STAT_STATE_RD_DSTENDP
Reading destination end pointer
0x4 : UDMA_STAT_STATE_RD_SRCDAT
Reading source data
0x5 : UDMA_STAT_STATE_WR_DSTDAT
Writing destination data
0x6 : UDMA_STAT_STATE_WAIT
Waiting for uDMA request to clear
0x7 : UDMA_STAT_STATE_WR_CTRL
Writing channel controller data
0x8 : UDMA_STAT_STATE_STALL
Stalled
0x9 : UDMA_STAT_STATE_DONE
Done
0xa : UDMA_STAT_STATE_UNDEF
Undefined
End of enumeration elements list.
UDMA_STAT_DMACHANS : Available uDMA Channels Minus 1
bits : 16 - 36 (21 bit)
DMA Channel Wait-on-Request Status
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_WAITSTAT_WAITREQ : Channel [n] Wait Status
bits : 0 - 31 (32 bit)
DMA Channel Wait-on-Request Status
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_WAITSTAT_WAITREQ : Channel [n] Wait Status
bits : 0 - 31 (32 bit)
DMA Channel Software Request
address_offset : 0x14 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UDMA_SWREQ : Channel [n] Software Request
bits : 0 - 31 (32 bit)
access : write-only
DMA Channel Software Request
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UDMA_SWREQ : Channel [n] Software Request
bits : 0 - 31 (32 bit)
access : write-only
DMA Channel Useburst Set
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_USEBURSTSET_SET : Channel [n] Useburst Set
bits : 0 - 31 (32 bit)
DMA Channel Useburst Set
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_USEBURSTSET_SET : Channel [n] Useburst Set
bits : 0 - 31 (32 bit)
DMA Channel Useburst Clear
address_offset : 0x1C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UDMA_USEBURSTCLR_CLR : Channel [n] Useburst Clear
bits : 0 - 31 (32 bit)
access : write-only
DMA Channel Useburst Clear
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UDMA_USEBURSTCLR_CLR : Channel [n] Useburst Clear
bits : 0 - 31 (32 bit)
access : write-only
DMA Channel Request Mask Set
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_REQMASKSET_SET : Channel [n] Request Mask Set
bits : 0 - 31 (32 bit)
DMA Channel Request Mask Set
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_REQMASKSET_SET : Channel [n] Request Mask Set
bits : 0 - 31 (32 bit)
DMA Channel Request Mask Clear
address_offset : 0x24 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UDMA_REQMASKCLR_CLR : Channel [n] Request Mask Clear
bits : 0 - 31 (32 bit)
access : write-only
DMA Channel Request Mask Clear
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UDMA_REQMASKCLR_CLR : Channel [n] Request Mask Clear
bits : 0 - 31 (32 bit)
access : write-only
DMA Channel Enable Set
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_ENASET_SET : Channel [n] Enable Set
bits : 0 - 31 (32 bit)
DMA Channel Enable Set
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_ENASET_SET : Channel [n] Enable Set
bits : 0 - 31 (32 bit)
DMA Channel Enable Clear
address_offset : 0x2C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UDMA_ENACLR_CLR : Clear Channel [n] Enable Clear
bits : 0 - 31 (32 bit)
access : write-only
DMA Channel Enable Clear
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UDMA_ENACLR_CLR : Clear Channel [n] Enable Clear
bits : 0 - 31 (32 bit)
access : write-only
DMA Channel Primary Alternate Set
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_ALTSET_SET : Channel [n] Alternate Set
bits : 0 - 31 (32 bit)
DMA Channel Primary Alternate Set
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_ALTSET_SET : Channel [n] Alternate Set
bits : 0 - 31 (32 bit)
DMA Channel Primary Alternate Clear
address_offset : 0x34 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UDMA_ALTCLR_CLR : Channel [n] Alternate Clear
bits : 0 - 31 (32 bit)
access : write-only
DMA Channel Primary Alternate Clear
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UDMA_ALTCLR_CLR : Channel [n] Alternate Clear
bits : 0 - 31 (32 bit)
access : write-only
DMA Channel Priority Set
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_PRIOSET_SET : Channel [n] Priority Set
bits : 0 - 31 (32 bit)
DMA Channel Priority Set
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_PRIOSET_SET : Channel [n] Priority Set
bits : 0 - 31 (32 bit)
DMA Channel Priority Clear
address_offset : 0x3C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UDMA_PRIOCLR_CLR : Channel [n] Priority Clear
bits : 0 - 31 (32 bit)
access : write-only
DMA Channel Priority Clear
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UDMA_PRIOCLR_CLR : Channel [n] Priority Clear
bits : 0 - 31 (32 bit)
access : write-only
DMA Configuration
address_offset : 0x4 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UDMA_CFG_MASTEN : Controller Master Enable
bits : 0 - 0 (1 bit)
access : write-only
DMA Configuration
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UDMA_CFG_MASTEN : Controller Master Enable
bits : 0 - 0 (1 bit)
access : write-only
DMA Bus Error Clear
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_ERRCLR_ERRCLR : uDMA Bus Error Status
bits : 0 - 0 (1 bit)
DMA Bus Error Clear
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_ERRCLR_ERRCLR : uDMA Bus Error Status
bits : 0 - 0 (1 bit)
DMA Channel Assignment
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_CHASGN : Channel [n] Assignment Select
bits : 0 - 31 (32 bit)
Enumeration:
0x0 : UDMA_CHASGN_PRIMARY
Use the primary channel assignment
0x1 : UDMA_CHASGN_SECONDARY
Use the secondary channel assignment
End of enumeration elements list.
DMA Channel Assignment
address_offset : 0x500 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_CHASGN : Channel [n] Assignment Select
bits : 0 - 31 (32 bit)
Enumeration:
0x0 : UDMA_CHASGN_PRIMARY
Use the primary channel assignment
0x1 : UDMA_CHASGN_SECONDARY
Use the secondary channel assignment
End of enumeration elements list.
DMA Channel Interrupt Status
address_offset : 0x504 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_CHIS : Channel [n] Interrupt Status
bits : 0 - 31 (32 bit)
DMA Channel Interrupt Status
address_offset : 0x504 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_CHIS : Channel [n] Interrupt Status
bits : 0 - 31 (32 bit)
DMA Channel Control Base Pointer
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_CTLBASE_ADDR : Channel Control Base Address
bits : 10 - 41 (32 bit)
DMA Channel Control Base Pointer
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_CTLBASE_ADDR : Channel Control Base Address
bits : 10 - 41 (32 bit)
DMA Alternate Channel Control Base Pointer
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_ALTBASE_ADDR : Alternate Channel Address Pointer
bits : 0 - 31 (32 bit)
DMA Alternate Channel Control Base Pointer
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDMA_ALTBASE_ADDR : Alternate Channel Address Pointer
bits : 0 - 31 (32 bit)
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