\n

UDM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

UDMASTAT

STAT

UDMAWAITSTAT

WAITSTAT

UDMASWREQ

SWREQ

UDMAUSEBURSTSET

USEBURSTSET

UDMAUSEBURSTCLR

USEBURSTCLR

UDMAREQMASKSET

REQMASKSET

UDMAREQMASKCLR

REQMASKCLR

UDMAENASET

ENASET

UDMAENACLR

ENACLR

UDMAALTSET

ALTSET

UDMAALTCLR

ALTCLR

UDMAPRIOSET

PRIOSET

UDMAPRIOCLR

PRIOCLR

UDMACFG

CFG

UDMAERRCLR

ERRCLR

UDMACHASGN

CHASGN

UDMACHIS

CHIS

UDMACTLBASE

CTLBASE

UDMAALTBASE

ALTBASE


UDMASTAT

DMA Status
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDMASTAT UDMASTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_STAT_MASTEN UDMA_STAT_STATE UDMA_STAT_DMACHANS

UDMA_STAT_MASTEN : Master Enable Status
bits : 0 - 0 (1 bit)

UDMA_STAT_STATE : Control State Machine Status
bits : 4 - 11 (8 bit)

Enumeration:

0x0 : UDMA_STAT_STATE_IDLE

Idle

0x1 : UDMA_STAT_STATE_RD_CTRL

Reading channel controller data

0x2 : UDMA_STAT_STATE_RD_SRCENDP

Reading source end pointer

0x3 : UDMA_STAT_STATE_RD_DSTENDP

Reading destination end pointer

0x4 : UDMA_STAT_STATE_RD_SRCDAT

Reading source data

0x5 : UDMA_STAT_STATE_WR_DSTDAT

Writing destination data

0x6 : UDMA_STAT_STATE_WAIT

Waiting for uDMA request to clear

0x7 : UDMA_STAT_STATE_WR_CTRL

Writing channel controller data

0x8 : UDMA_STAT_STATE_STALL

Stalled

0x9 : UDMA_STAT_STATE_DONE

Done

0xa : UDMA_STAT_STATE_UNDEF

Undefined

End of enumeration elements list.

UDMA_STAT_DMACHANS : Available uDMA Channels Minus 1
bits : 16 - 36 (21 bit)


STAT

DMA Status
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_STAT_MASTEN UDMA_STAT_STATE UDMA_STAT_DMACHANS

UDMA_STAT_MASTEN : Master Enable Status
bits : 0 - 0 (1 bit)

UDMA_STAT_STATE : Control State Machine Status
bits : 4 - 11 (8 bit)

Enumeration:

0x0 : UDMA_STAT_STATE_IDLE

Idle

0x1 : UDMA_STAT_STATE_RD_CTRL

Reading channel controller data

0x2 : UDMA_STAT_STATE_RD_SRCENDP

Reading source end pointer

0x3 : UDMA_STAT_STATE_RD_DSTENDP

Reading destination end pointer

0x4 : UDMA_STAT_STATE_RD_SRCDAT

Reading source data

0x5 : UDMA_STAT_STATE_WR_DSTDAT

Writing destination data

0x6 : UDMA_STAT_STATE_WAIT

Waiting for uDMA request to clear

0x7 : UDMA_STAT_STATE_WR_CTRL

Writing channel controller data

0x8 : UDMA_STAT_STATE_STALL

Stalled

0x9 : UDMA_STAT_STATE_DONE

Done

0xa : UDMA_STAT_STATE_UNDEF

Undefined

End of enumeration elements list.

UDMA_STAT_DMACHANS : Available uDMA Channels Minus 1
bits : 16 - 36 (21 bit)


UDMAWAITSTAT

DMA Channel Wait-on-Request Status
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDMAWAITSTAT UDMAWAITSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_WAITSTAT_WAITREQ

UDMA_WAITSTAT_WAITREQ : Channel [n] Wait Status
bits : 0 - 31 (32 bit)


WAITSTAT

DMA Channel Wait-on-Request Status
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAITSTAT WAITSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_WAITSTAT_WAITREQ

UDMA_WAITSTAT_WAITREQ : Channel [n] Wait Status
bits : 0 - 31 (32 bit)


UDMASWREQ

DMA Channel Software Request
address_offset : 0x14 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UDMASWREQ UDMASWREQ write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_SWREQ

UDMA_SWREQ : Channel [n] Software Request
bits : 0 - 31 (32 bit)
access : write-only


SWREQ

DMA Channel Software Request
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWREQ SWREQ write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_SWREQ

UDMA_SWREQ : Channel [n] Software Request
bits : 0 - 31 (32 bit)
access : write-only


UDMAUSEBURSTSET

DMA Channel Useburst Set
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDMAUSEBURSTSET UDMAUSEBURSTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_USEBURSTSET_SET

UDMA_USEBURSTSET_SET : Channel [n] Useburst Set
bits : 0 - 31 (32 bit)


USEBURSTSET

DMA Channel Useburst Set
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USEBURSTSET USEBURSTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_USEBURSTSET_SET

UDMA_USEBURSTSET_SET : Channel [n] Useburst Set
bits : 0 - 31 (32 bit)


UDMAUSEBURSTCLR

DMA Channel Useburst Clear
address_offset : 0x1C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UDMAUSEBURSTCLR UDMAUSEBURSTCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_USEBURSTCLR_CLR

UDMA_USEBURSTCLR_CLR : Channel [n] Useburst Clear
bits : 0 - 31 (32 bit)
access : write-only


USEBURSTCLR

DMA Channel Useburst Clear
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

USEBURSTCLR USEBURSTCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_USEBURSTCLR_CLR

UDMA_USEBURSTCLR_CLR : Channel [n] Useburst Clear
bits : 0 - 31 (32 bit)
access : write-only


UDMAREQMASKSET

DMA Channel Request Mask Set
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDMAREQMASKSET UDMAREQMASKSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_REQMASKSET_SET

UDMA_REQMASKSET_SET : Channel [n] Request Mask Set
bits : 0 - 31 (32 bit)


REQMASKSET

DMA Channel Request Mask Set
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REQMASKSET REQMASKSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_REQMASKSET_SET

UDMA_REQMASKSET_SET : Channel [n] Request Mask Set
bits : 0 - 31 (32 bit)


UDMAREQMASKCLR

DMA Channel Request Mask Clear
address_offset : 0x24 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UDMAREQMASKCLR UDMAREQMASKCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_REQMASKCLR_CLR

UDMA_REQMASKCLR_CLR : Channel [n] Request Mask Clear
bits : 0 - 31 (32 bit)
access : write-only


REQMASKCLR

DMA Channel Request Mask Clear
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

REQMASKCLR REQMASKCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_REQMASKCLR_CLR

UDMA_REQMASKCLR_CLR : Channel [n] Request Mask Clear
bits : 0 - 31 (32 bit)
access : write-only


UDMAENASET

DMA Channel Enable Set
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDMAENASET UDMAENASET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_ENASET_SET

UDMA_ENASET_SET : Channel [n] Enable Set
bits : 0 - 31 (32 bit)


ENASET

DMA Channel Enable Set
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENASET ENASET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_ENASET_SET

UDMA_ENASET_SET : Channel [n] Enable Set
bits : 0 - 31 (32 bit)


UDMAENACLR

DMA Channel Enable Clear
address_offset : 0x2C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UDMAENACLR UDMAENACLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_ENACLR_CLR

UDMA_ENACLR_CLR : Clear Channel [n] Enable Clear
bits : 0 - 31 (32 bit)
access : write-only


ENACLR

DMA Channel Enable Clear
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ENACLR ENACLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_ENACLR_CLR

UDMA_ENACLR_CLR : Clear Channel [n] Enable Clear
bits : 0 - 31 (32 bit)
access : write-only


UDMAALTSET

DMA Channel Primary Alternate Set
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDMAALTSET UDMAALTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_ALTSET_SET

UDMA_ALTSET_SET : Channel [n] Alternate Set
bits : 0 - 31 (32 bit)


ALTSET

DMA Channel Primary Alternate Set
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALTSET ALTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_ALTSET_SET

UDMA_ALTSET_SET : Channel [n] Alternate Set
bits : 0 - 31 (32 bit)


UDMAALTCLR

DMA Channel Primary Alternate Clear
address_offset : 0x34 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UDMAALTCLR UDMAALTCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_ALTCLR_CLR

UDMA_ALTCLR_CLR : Channel [n] Alternate Clear
bits : 0 - 31 (32 bit)
access : write-only


ALTCLR

DMA Channel Primary Alternate Clear
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ALTCLR ALTCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_ALTCLR_CLR

UDMA_ALTCLR_CLR : Channel [n] Alternate Clear
bits : 0 - 31 (32 bit)
access : write-only


UDMAPRIOSET

DMA Channel Priority Set
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDMAPRIOSET UDMAPRIOSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_PRIOSET_SET

UDMA_PRIOSET_SET : Channel [n] Priority Set
bits : 0 - 31 (32 bit)


PRIOSET

DMA Channel Priority Set
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRIOSET PRIOSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_PRIOSET_SET

UDMA_PRIOSET_SET : Channel [n] Priority Set
bits : 0 - 31 (32 bit)


UDMAPRIOCLR

DMA Channel Priority Clear
address_offset : 0x3C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UDMAPRIOCLR UDMAPRIOCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_PRIOCLR_CLR

UDMA_PRIOCLR_CLR : Channel [n] Priority Clear
bits : 0 - 31 (32 bit)
access : write-only


PRIOCLR

DMA Channel Priority Clear
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PRIOCLR PRIOCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_PRIOCLR_CLR

UDMA_PRIOCLR_CLR : Channel [n] Priority Clear
bits : 0 - 31 (32 bit)
access : write-only


UDMACFG

DMA Configuration
address_offset : 0x4 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UDMACFG UDMACFG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_CFG_MASTEN

UDMA_CFG_MASTEN : Controller Master Enable
bits : 0 - 0 (1 bit)
access : write-only


CFG

DMA Configuration
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CFG CFG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_CFG_MASTEN

UDMA_CFG_MASTEN : Controller Master Enable
bits : 0 - 0 (1 bit)
access : write-only


UDMAERRCLR

DMA Bus Error Clear
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDMAERRCLR UDMAERRCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_ERRCLR_ERRCLR

UDMA_ERRCLR_ERRCLR : uDMA Bus Error Status
bits : 0 - 0 (1 bit)


ERRCLR

DMA Bus Error Clear
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERRCLR ERRCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_ERRCLR_ERRCLR

UDMA_ERRCLR_ERRCLR : uDMA Bus Error Status
bits : 0 - 0 (1 bit)


UDMACHASGN

DMA Channel Assignment
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDMACHASGN UDMACHASGN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_CHASGN

UDMA_CHASGN : Channel [n] Assignment Select
bits : 0 - 31 (32 bit)

Enumeration:

0x0 : UDMA_CHASGN_PRIMARY

Use the primary channel assignment

0x1 : UDMA_CHASGN_SECONDARY

Use the secondary channel assignment

End of enumeration elements list.


CHASGN

DMA Channel Assignment
address_offset : 0x500 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHASGN CHASGN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_CHASGN

UDMA_CHASGN : Channel [n] Assignment Select
bits : 0 - 31 (32 bit)

Enumeration:

0x0 : UDMA_CHASGN_PRIMARY

Use the primary channel assignment

0x1 : UDMA_CHASGN_SECONDARY

Use the secondary channel assignment

End of enumeration elements list.


UDMACHIS

DMA Channel Interrupt Status
address_offset : 0x504 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDMACHIS UDMACHIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_CHIS

UDMA_CHIS : Channel [n] Interrupt Status
bits : 0 - 31 (32 bit)


CHIS

DMA Channel Interrupt Status
address_offset : 0x504 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIS CHIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_CHIS

UDMA_CHIS : Channel [n] Interrupt Status
bits : 0 - 31 (32 bit)


UDMACTLBASE

DMA Channel Control Base Pointer
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDMACTLBASE UDMACTLBASE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_CTLBASE_ADDR

UDMA_CTLBASE_ADDR : Channel Control Base Address
bits : 10 - 41 (32 bit)


CTLBASE

DMA Channel Control Base Pointer
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLBASE CTLBASE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_CTLBASE_ADDR

UDMA_CTLBASE_ADDR : Channel Control Base Address
bits : 10 - 41 (32 bit)


UDMAALTBASE

DMA Alternate Channel Control Base Pointer
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDMAALTBASE UDMAALTBASE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_ALTBASE_ADDR

UDMA_ALTBASE_ADDR : Alternate Channel Address Pointer
bits : 0 - 31 (32 bit)


ALTBASE

DMA Alternate Channel Control Base Pointer
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALTBASE ALTBASE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDMA_ALTBASE_ADDR

UDMA_ALTBASE_ADDR : Alternate Channel Address Pointer
bits : 0 - 31 (32 bit)



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