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SYSCTL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SYSCTLDID0

DID0

SYSCTLDC1

DC1

SYSCTLRCGC0

RCGC0

SYSCTLRCGC1

RCGC1

SYSCTLRCGC2

RCGC2

SYSCTLSCGC0

SCGC0

SYSCTLSCGC1

SCGC1

SYSCTLSCGC2

SCGC2

SYSCTLDCGC0

DCGC0

SYSCTLDCGC1

DCGC1

SYSCTLDCGC2

DCGC2

SYSCTLDC2

DC2

SYSCTLDSLPCLKCFG

DSLPCLKCFG

SYSCTLDC3

DC3

SYSCTLDC4

DC4

SYSCTLDC5

DC5

SYSCTLDC6

DC6

SYSCTLDC7

DC7

SYSCTLPBORCTL

PBORCTL

SYSCTLLDOPCTL

LDOPCTL

SYSCTLDID1

DID1

SYSCTLSRCR0

SRCR0

SYSCTLSRCR1

SRCR1

SYSCTLSRCR2

SRCR2

SYSCTLRIS

RIS

SYSCTLIMC

IMC

SYSCTLMISC

MISC

SYSCTLRESC

RESC

SYSCTLRCC

RCC

SYSCTLPLLCFG

PLLCFG

SYSCTLGPIOHBCTL

GPIOHBCTL

SYSCTLRCC2

RCC2

SYSCTLMOSCCTL

MOSCCTL

SYSCTLDC0

DC0


SYSCTLDID0

Device Identification 0
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLDID0 SYSCTLDID0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DID0_MIN SYSCTL_DID0_MAJ SYSCTL_DID0_CLASS SYSCTL_DID0_VER

SYSCTL_DID0_MIN : Minor Revision
bits : 0 - 7 (8 bit)

Enumeration:

0x0 : SYSCTL_DID0_MIN_0

Initial device, or a major revision update

0x1 : SYSCTL_DID0_MIN_1

First metal layer change

0x2 : SYSCTL_DID0_MIN_2

Second metal layer change

End of enumeration elements list.

SYSCTL_DID0_MAJ : Major Revision
bits : 8 - 23 (16 bit)

Enumeration:

0x0 : SYSCTL_DID0_MAJ_REVA

Revision A (initial device)

0x1 : SYSCTL_DID0_MAJ_REVB

Revision B (first base layer revision)

0x2 : SYSCTL_DID0_MAJ_REVC

Revision C (second base layer revision)

End of enumeration elements list.

SYSCTL_DID0_CLASS : Device Class
bits : 16 - 39 (24 bit)

Enumeration:

0x3 : SYSCTL_DID0_CLASS_DUSTDEVIL

Stellaris(R) DustDevil-class devices

End of enumeration elements list.

SYSCTL_DID0_VER : DID0 Version
bits : 28 - 58 (31 bit)

Enumeration:

0x1 : SYSCTL_DID0_VER_1

Second version of the DID0 register format

End of enumeration elements list.


DID0

Device Identification 0
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DID0 DID0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DID0_MIN SYSCTL_DID0_MAJ SYSCTL_DID0_CLASS SYSCTL_DID0_VER

SYSCTL_DID0_MIN : Minor Revision
bits : 0 - 7 (8 bit)

Enumeration:

0x0 : SYSCTL_DID0_MIN_0

Initial device, or a major revision update

0x1 : SYSCTL_DID0_MIN_1

First metal layer change

0x2 : SYSCTL_DID0_MIN_2

Second metal layer change

End of enumeration elements list.

SYSCTL_DID0_MAJ : Major Revision
bits : 8 - 23 (16 bit)

Enumeration:

0x0 : SYSCTL_DID0_MAJ_REVA

Revision A (initial device)

0x1 : SYSCTL_DID0_MAJ_REVB

Revision B (first base layer revision)

0x2 : SYSCTL_DID0_MAJ_REVC

Revision C (second base layer revision)

End of enumeration elements list.

SYSCTL_DID0_CLASS : Device Class
bits : 16 - 39 (24 bit)

Enumeration:

0x3 : SYSCTL_DID0_CLASS_DUSTDEVIL

Stellaris(R) DustDevil-class devices

End of enumeration elements list.

SYSCTL_DID0_VER : DID0 Version
bits : 28 - 58 (31 bit)

Enumeration:

0x1 : SYSCTL_DID0_VER_1

Second version of the DID0 register format

End of enumeration elements list.


SYSCTLDC1

Device Capabilities 1
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLDC1 SYSCTLDC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DC1_JTAG SYSCTL_DC1_SWD SYSCTL_DC1_SWO SYSCTL_DC1_WDT0 SYSCTL_DC1_PLL SYSCTL_DC1_TEMP SYSCTL_DC1_HIB SYSCTL_DC1_MPU SYSCTL_DC1_MINSYSDIV SYSCTL_DC1_CAN0

SYSCTL_DC1_JTAG : JTAG Present
bits : 0 - 0 (1 bit)

SYSCTL_DC1_SWD : SWD Present
bits : 1 - 2 (2 bit)

SYSCTL_DC1_SWO : SWO Trace Port Present
bits : 2 - 4 (3 bit)

SYSCTL_DC1_WDT0 : Watchdog Timer 0 Present
bits : 3 - 6 (4 bit)

SYSCTL_DC1_PLL : PLL Present
bits : 4 - 8 (5 bit)

SYSCTL_DC1_TEMP : Temp Sensor Present
bits : 5 - 10 (6 bit)

SYSCTL_DC1_HIB : Hibernation Module Present
bits : 6 - 12 (7 bit)

SYSCTL_DC1_MPU : MPU Present
bits : 7 - 14 (8 bit)

SYSCTL_DC1_MINSYSDIV : System Clock Divider
bits : 12 - 27 (16 bit)

Enumeration:

0x3 : SYSCTL_DC1_MINSYSDIV_50

Specifies a 50-MHz CPU clock with a PLL divider of 4

End of enumeration elements list.

SYSCTL_DC1_CAN0 : CAN Module 0 Present
bits : 24 - 48 (25 bit)


DC1

Device Capabilities 1
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DC1 DC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DC1_JTAG SYSCTL_DC1_SWD SYSCTL_DC1_SWO SYSCTL_DC1_WDT0 SYSCTL_DC1_PLL SYSCTL_DC1_TEMP SYSCTL_DC1_HIB SYSCTL_DC1_MPU SYSCTL_DC1_MINSYSDIV SYSCTL_DC1_CAN0

SYSCTL_DC1_JTAG : JTAG Present
bits : 0 - 0 (1 bit)

SYSCTL_DC1_SWD : SWD Present
bits : 1 - 2 (2 bit)

SYSCTL_DC1_SWO : SWO Trace Port Present
bits : 2 - 4 (3 bit)

SYSCTL_DC1_WDT0 : Watchdog Timer 0 Present
bits : 3 - 6 (4 bit)

SYSCTL_DC1_PLL : PLL Present
bits : 4 - 8 (5 bit)

SYSCTL_DC1_TEMP : Temp Sensor Present
bits : 5 - 10 (6 bit)

SYSCTL_DC1_HIB : Hibernation Module Present
bits : 6 - 12 (7 bit)

SYSCTL_DC1_MPU : MPU Present
bits : 7 - 14 (8 bit)

SYSCTL_DC1_MINSYSDIV : System Clock Divider
bits : 12 - 27 (16 bit)

Enumeration:

0x3 : SYSCTL_DC1_MINSYSDIV_50

Specifies a 50-MHz CPU clock with a PLL divider of 4

End of enumeration elements list.

SYSCTL_DC1_CAN0 : CAN Module 0 Present
bits : 24 - 48 (25 bit)


SYSCTLRCGC0

Run Mode Clock Gating Control Register 0
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLRCGC0 SYSCTLRCGC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_RCGC0_HIB SYSCTL_RCGC0_ADCSPD SYSCTL_RCGC0_CAN0

SYSCTL_RCGC0_HIB : HIB Clock Gating Control
bits : 6 - 12 (7 bit)

SYSCTL_RCGC0_ADCSPD : ADC Sample Speed
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : SYSCTL_RCGC0_ADCSPD125K

125K samples/second

0x1 : SYSCTL_RCGC0_ADCSPD250K

250K samples/second

0x2 : SYSCTL_RCGC0_ADCSPD500K

500K samples/second

0x3 : SYSCTL_RCGC0_ADCSPD1M

1M samples/second

End of enumeration elements list.

SYSCTL_RCGC0_CAN0 : CAN0 Clock Gating Control
bits : 24 - 48 (25 bit)


RCGC0

Run Mode Clock Gating Control Register 0
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCGC0 RCGC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_RCGC0_HIB SYSCTL_RCGC0_ADCSPD SYSCTL_RCGC0_CAN0

SYSCTL_RCGC0_HIB : HIB Clock Gating Control
bits : 6 - 12 (7 bit)

SYSCTL_RCGC0_ADCSPD : ADC Sample Speed
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : SYSCTL_RCGC0_ADCSPD125K

125K samples/second

0x1 : SYSCTL_RCGC0_ADCSPD250K

250K samples/second

0x2 : SYSCTL_RCGC0_ADCSPD500K

500K samples/second

0x3 : SYSCTL_RCGC0_ADCSPD1M

1M samples/second

End of enumeration elements list.

SYSCTL_RCGC0_CAN0 : CAN0 Clock Gating Control
bits : 24 - 48 (25 bit)


SYSCTLRCGC1

Run Mode Clock Gating Control Register 1
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLRCGC1 SYSCTLRCGC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_RCGC1_UART0 SYSCTL_RCGC1_SSI0 SYSCTL_RCGC1_I2C0 SYSCTL_RCGC1_TIMER0 SYSCTL_RCGC1_TIMER1 SYSCTL_RCGC1_TIMER2

SYSCTL_RCGC1_UART0 : UART0 Clock Gating Control
bits : 0 - 0 (1 bit)

SYSCTL_RCGC1_SSI0 : SSI0 Clock Gating Control
bits : 4 - 8 (5 bit)

SYSCTL_RCGC1_I2C0 : I2C0 Clock Gating Control
bits : 12 - 24 (13 bit)

SYSCTL_RCGC1_TIMER0 : Timer 0 Clock Gating Control
bits : 16 - 32 (17 bit)

SYSCTL_RCGC1_TIMER1 : Timer 1 Clock Gating Control
bits : 17 - 34 (18 bit)

SYSCTL_RCGC1_TIMER2 : Timer 2 Clock Gating Control
bits : 18 - 36 (19 bit)


RCGC1

Run Mode Clock Gating Control Register 1
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCGC1 RCGC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_RCGC1_UART0 SYSCTL_RCGC1_SSI0 SYSCTL_RCGC1_I2C0 SYSCTL_RCGC1_TIMER0 SYSCTL_RCGC1_TIMER1 SYSCTL_RCGC1_TIMER2

SYSCTL_RCGC1_UART0 : UART0 Clock Gating Control
bits : 0 - 0 (1 bit)

SYSCTL_RCGC1_SSI0 : SSI0 Clock Gating Control
bits : 4 - 8 (5 bit)

SYSCTL_RCGC1_I2C0 : I2C0 Clock Gating Control
bits : 12 - 24 (13 bit)

SYSCTL_RCGC1_TIMER0 : Timer 0 Clock Gating Control
bits : 16 - 32 (17 bit)

SYSCTL_RCGC1_TIMER1 : Timer 1 Clock Gating Control
bits : 17 - 34 (18 bit)

SYSCTL_RCGC1_TIMER2 : Timer 2 Clock Gating Control
bits : 18 - 36 (19 bit)


SYSCTLRCGC2

Run Mode Clock Gating Control Register 2
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLRCGC2 SYSCTLRCGC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_RCGC2_GPIOA SYSCTL_RCGC2_GPIOB SYSCTL_RCGC2_GPIOC SYSCTL_RCGC2_GPIOD SYSCTL_RCGC2_GPIOE SYSCTL_RCGC2_UDMA

SYSCTL_RCGC2_GPIOA : Port A Clock Gating Control
bits : 0 - 0 (1 bit)

SYSCTL_RCGC2_GPIOB : Port B Clock Gating Control
bits : 1 - 2 (2 bit)

SYSCTL_RCGC2_GPIOC : Port C Clock Gating Control
bits : 2 - 4 (3 bit)

SYSCTL_RCGC2_GPIOD : Port D Clock Gating Control
bits : 3 - 6 (4 bit)

SYSCTL_RCGC2_GPIOE : Port E Clock Gating Control
bits : 4 - 8 (5 bit)

SYSCTL_RCGC2_UDMA : Micro-DMA Clock Gating Control
bits : 13 - 26 (14 bit)


RCGC2

Run Mode Clock Gating Control Register 2
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCGC2 RCGC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_RCGC2_GPIOA SYSCTL_RCGC2_GPIOB SYSCTL_RCGC2_GPIOC SYSCTL_RCGC2_GPIOD SYSCTL_RCGC2_GPIOE SYSCTL_RCGC2_UDMA

SYSCTL_RCGC2_GPIOA : Port A Clock Gating Control
bits : 0 - 0 (1 bit)

SYSCTL_RCGC2_GPIOB : Port B Clock Gating Control
bits : 1 - 2 (2 bit)

SYSCTL_RCGC2_GPIOC : Port C Clock Gating Control
bits : 2 - 4 (3 bit)

SYSCTL_RCGC2_GPIOD : Port D Clock Gating Control
bits : 3 - 6 (4 bit)

SYSCTL_RCGC2_GPIOE : Port E Clock Gating Control
bits : 4 - 8 (5 bit)

SYSCTL_RCGC2_UDMA : Micro-DMA Clock Gating Control
bits : 13 - 26 (14 bit)


SYSCTLSCGC0

Sleep Mode Clock Gating Control Register 0
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLSCGC0 SYSCTLSCGC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_SCGC0_HIB SYSCTL_SCGC0_ADCSPD SYSCTL_SCGC0_CAN0

SYSCTL_SCGC0_HIB : HIB Clock Gating Control
bits : 6 - 12 (7 bit)

SYSCTL_SCGC0_ADCSPD : ADC Sample Speed
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : SYSCTL_SCGC0_ADCSPD125K

125K samples/second

0x1 : SYSCTL_SCGC0_ADCSPD250K

250K samples/second

0x2 : SYSCTL_SCGC0_ADCSPD500K

500K samples/second

0x3 : SYSCTL_SCGC0_ADCSPD1M

1M samples/second

End of enumeration elements list.

SYSCTL_SCGC0_CAN0 : CAN0 Clock Gating Control
bits : 24 - 48 (25 bit)


SCGC0

Sleep Mode Clock Gating Control Register 0
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCGC0 SCGC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_SCGC0_HIB SYSCTL_SCGC0_ADCSPD SYSCTL_SCGC0_CAN0

SYSCTL_SCGC0_HIB : HIB Clock Gating Control
bits : 6 - 12 (7 bit)

SYSCTL_SCGC0_ADCSPD : ADC Sample Speed
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : SYSCTL_SCGC0_ADCSPD125K

125K samples/second

0x1 : SYSCTL_SCGC0_ADCSPD250K

250K samples/second

0x2 : SYSCTL_SCGC0_ADCSPD500K

500K samples/second

0x3 : SYSCTL_SCGC0_ADCSPD1M

1M samples/second

End of enumeration elements list.

SYSCTL_SCGC0_CAN0 : CAN0 Clock Gating Control
bits : 24 - 48 (25 bit)


SYSCTLSCGC1

Sleep Mode Clock Gating Control Register 1
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLSCGC1 SYSCTLSCGC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_SCGC1_UART0 SYSCTL_SCGC1_SSI0 SYSCTL_SCGC1_I2C0 SYSCTL_SCGC1_TIMER0 SYSCTL_SCGC1_TIMER1 SYSCTL_SCGC1_TIMER2

SYSCTL_SCGC1_UART0 : UART0 Clock Gating Control
bits : 0 - 0 (1 bit)

SYSCTL_SCGC1_SSI0 : SSI0 Clock Gating Control
bits : 4 - 8 (5 bit)

SYSCTL_SCGC1_I2C0 : I2C0 Clock Gating Control
bits : 12 - 24 (13 bit)

SYSCTL_SCGC1_TIMER0 : Timer 0 Clock Gating Control
bits : 16 - 32 (17 bit)

SYSCTL_SCGC1_TIMER1 : Timer 1 Clock Gating Control
bits : 17 - 34 (18 bit)

SYSCTL_SCGC1_TIMER2 : Timer 2 Clock Gating Control
bits : 18 - 36 (19 bit)


SCGC1

Sleep Mode Clock Gating Control Register 1
address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCGC1 SCGC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_SCGC1_UART0 SYSCTL_SCGC1_SSI0 SYSCTL_SCGC1_I2C0 SYSCTL_SCGC1_TIMER0 SYSCTL_SCGC1_TIMER1 SYSCTL_SCGC1_TIMER2

SYSCTL_SCGC1_UART0 : UART0 Clock Gating Control
bits : 0 - 0 (1 bit)

SYSCTL_SCGC1_SSI0 : SSI0 Clock Gating Control
bits : 4 - 8 (5 bit)

SYSCTL_SCGC1_I2C0 : I2C0 Clock Gating Control
bits : 12 - 24 (13 bit)

SYSCTL_SCGC1_TIMER0 : Timer 0 Clock Gating Control
bits : 16 - 32 (17 bit)

SYSCTL_SCGC1_TIMER1 : Timer 1 Clock Gating Control
bits : 17 - 34 (18 bit)

SYSCTL_SCGC1_TIMER2 : Timer 2 Clock Gating Control
bits : 18 - 36 (19 bit)


SYSCTLSCGC2

Sleep Mode Clock Gating Control Register 2
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLSCGC2 SYSCTLSCGC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_SCGC2_GPIOA SYSCTL_SCGC2_GPIOB SYSCTL_SCGC2_GPIOC SYSCTL_SCGC2_GPIOD SYSCTL_SCGC2_GPIOE SYSCTL_SCGC2_UDMA

SYSCTL_SCGC2_GPIOA : Port A Clock Gating Control
bits : 0 - 0 (1 bit)

SYSCTL_SCGC2_GPIOB : Port B Clock Gating Control
bits : 1 - 2 (2 bit)

SYSCTL_SCGC2_GPIOC : Port C Clock Gating Control
bits : 2 - 4 (3 bit)

SYSCTL_SCGC2_GPIOD : Port D Clock Gating Control
bits : 3 - 6 (4 bit)

SYSCTL_SCGC2_GPIOE : Port E Clock Gating Control
bits : 4 - 8 (5 bit)

SYSCTL_SCGC2_UDMA : Micro-DMA Clock Gating Control
bits : 13 - 26 (14 bit)


SCGC2

Sleep Mode Clock Gating Control Register 2
address_offset : 0x118 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCGC2 SCGC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_SCGC2_GPIOA SYSCTL_SCGC2_GPIOB SYSCTL_SCGC2_GPIOC SYSCTL_SCGC2_GPIOD SYSCTL_SCGC2_GPIOE SYSCTL_SCGC2_UDMA

SYSCTL_SCGC2_GPIOA : Port A Clock Gating Control
bits : 0 - 0 (1 bit)

SYSCTL_SCGC2_GPIOB : Port B Clock Gating Control
bits : 1 - 2 (2 bit)

SYSCTL_SCGC2_GPIOC : Port C Clock Gating Control
bits : 2 - 4 (3 bit)

SYSCTL_SCGC2_GPIOD : Port D Clock Gating Control
bits : 3 - 6 (4 bit)

SYSCTL_SCGC2_GPIOE : Port E Clock Gating Control
bits : 4 - 8 (5 bit)

SYSCTL_SCGC2_UDMA : Micro-DMA Clock Gating Control
bits : 13 - 26 (14 bit)


SYSCTLDCGC0

Deep Sleep Mode Clock Gating Control Register 0
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLDCGC0 SYSCTLDCGC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DCGC0_HIB SYSCTL_DCGC0_CAN0

SYSCTL_DCGC0_HIB : HIB Clock Gating Control
bits : 6 - 12 (7 bit)

SYSCTL_DCGC0_CAN0 : CAN0 Clock Gating Control
bits : 24 - 48 (25 bit)


DCGC0

Deep Sleep Mode Clock Gating Control Register 0
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCGC0 DCGC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DCGC0_HIB SYSCTL_DCGC0_CAN0

SYSCTL_DCGC0_HIB : HIB Clock Gating Control
bits : 6 - 12 (7 bit)

SYSCTL_DCGC0_CAN0 : CAN0 Clock Gating Control
bits : 24 - 48 (25 bit)


SYSCTLDCGC1

Deep-Sleep Mode Clock Gating Control Register 1
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLDCGC1 SYSCTLDCGC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DCGC1_UART0 SYSCTL_DCGC1_SSI0 SYSCTL_DCGC1_I2C0 SYSCTL_DCGC1_TIMER0 SYSCTL_DCGC1_TIMER1 SYSCTL_DCGC1_TIMER2

SYSCTL_DCGC1_UART0 : UART0 Clock Gating Control
bits : 0 - 0 (1 bit)

SYSCTL_DCGC1_SSI0 : SSI0 Clock Gating Control
bits : 4 - 8 (5 bit)

SYSCTL_DCGC1_I2C0 : I2C0 Clock Gating Control
bits : 12 - 24 (13 bit)

SYSCTL_DCGC1_TIMER0 : Timer 0 Clock Gating Control
bits : 16 - 32 (17 bit)

SYSCTL_DCGC1_TIMER1 : Timer 1 Clock Gating Control
bits : 17 - 34 (18 bit)

SYSCTL_DCGC1_TIMER2 : Timer 2 Clock Gating Control
bits : 18 - 36 (19 bit)


DCGC1

Deep-Sleep Mode Clock Gating Control Register 1
address_offset : 0x124 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCGC1 DCGC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DCGC1_UART0 SYSCTL_DCGC1_SSI0 SYSCTL_DCGC1_I2C0 SYSCTL_DCGC1_TIMER0 SYSCTL_DCGC1_TIMER1 SYSCTL_DCGC1_TIMER2

SYSCTL_DCGC1_UART0 : UART0 Clock Gating Control
bits : 0 - 0 (1 bit)

SYSCTL_DCGC1_SSI0 : SSI0 Clock Gating Control
bits : 4 - 8 (5 bit)

SYSCTL_DCGC1_I2C0 : I2C0 Clock Gating Control
bits : 12 - 24 (13 bit)

SYSCTL_DCGC1_TIMER0 : Timer 0 Clock Gating Control
bits : 16 - 32 (17 bit)

SYSCTL_DCGC1_TIMER1 : Timer 1 Clock Gating Control
bits : 17 - 34 (18 bit)

SYSCTL_DCGC1_TIMER2 : Timer 2 Clock Gating Control
bits : 18 - 36 (19 bit)


SYSCTLDCGC2

Deep Sleep Mode Clock Gating Control Register 2
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLDCGC2 SYSCTLDCGC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DCGC2_GPIOA SYSCTL_DCGC2_GPIOB SYSCTL_DCGC2_GPIOC SYSCTL_DCGC2_GPIOD SYSCTL_DCGC2_GPIOE SYSCTL_DCGC2_UDMA

SYSCTL_DCGC2_GPIOA : Port A Clock Gating Control
bits : 0 - 0 (1 bit)

SYSCTL_DCGC2_GPIOB : Port B Clock Gating Control
bits : 1 - 2 (2 bit)

SYSCTL_DCGC2_GPIOC : Port C Clock Gating Control
bits : 2 - 4 (3 bit)

SYSCTL_DCGC2_GPIOD : Port D Clock Gating Control
bits : 3 - 6 (4 bit)

SYSCTL_DCGC2_GPIOE : Port E Clock Gating Control
bits : 4 - 8 (5 bit)

SYSCTL_DCGC2_UDMA : Micro-DMA Clock Gating Control
bits : 13 - 26 (14 bit)


DCGC2

Deep Sleep Mode Clock Gating Control Register 2
address_offset : 0x128 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCGC2 DCGC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DCGC2_GPIOA SYSCTL_DCGC2_GPIOB SYSCTL_DCGC2_GPIOC SYSCTL_DCGC2_GPIOD SYSCTL_DCGC2_GPIOE SYSCTL_DCGC2_UDMA

SYSCTL_DCGC2_GPIOA : Port A Clock Gating Control
bits : 0 - 0 (1 bit)

SYSCTL_DCGC2_GPIOB : Port B Clock Gating Control
bits : 1 - 2 (2 bit)

SYSCTL_DCGC2_GPIOC : Port C Clock Gating Control
bits : 2 - 4 (3 bit)

SYSCTL_DCGC2_GPIOD : Port D Clock Gating Control
bits : 3 - 6 (4 bit)

SYSCTL_DCGC2_GPIOE : Port E Clock Gating Control
bits : 4 - 8 (5 bit)

SYSCTL_DCGC2_UDMA : Micro-DMA Clock Gating Control
bits : 13 - 26 (14 bit)


SYSCTLDC2

Device Capabilities 2
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLDC2 SYSCTLDC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DC2_UART0 SYSCTL_DC2_SSI0 SYSCTL_DC2_I2C0 SYSCTL_DC2_TIMER0 SYSCTL_DC2_TIMER1 SYSCTL_DC2_TIMER2

SYSCTL_DC2_UART0 : UART Module 0 Present
bits : 0 - 0 (1 bit)

SYSCTL_DC2_SSI0 : SSI Module 0 Present
bits : 4 - 8 (5 bit)

SYSCTL_DC2_I2C0 : I2C Module 0 Present
bits : 12 - 24 (13 bit)

SYSCTL_DC2_TIMER0 : Timer Module 0 Present
bits : 16 - 32 (17 bit)

SYSCTL_DC2_TIMER1 : Timer Module 1 Present
bits : 17 - 34 (18 bit)

SYSCTL_DC2_TIMER2 : Timer Module 2 Present
bits : 18 - 36 (19 bit)


DC2

Device Capabilities 2
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DC2 DC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DC2_UART0 SYSCTL_DC2_SSI0 SYSCTL_DC2_I2C0 SYSCTL_DC2_TIMER0 SYSCTL_DC2_TIMER1 SYSCTL_DC2_TIMER2

SYSCTL_DC2_UART0 : UART Module 0 Present
bits : 0 - 0 (1 bit)

SYSCTL_DC2_SSI0 : SSI Module 0 Present
bits : 4 - 8 (5 bit)

SYSCTL_DC2_I2C0 : I2C Module 0 Present
bits : 12 - 24 (13 bit)

SYSCTL_DC2_TIMER0 : Timer Module 0 Present
bits : 16 - 32 (17 bit)

SYSCTL_DC2_TIMER1 : Timer Module 1 Present
bits : 17 - 34 (18 bit)

SYSCTL_DC2_TIMER2 : Timer Module 2 Present
bits : 18 - 36 (19 bit)


SYSCTLDSLPCLKCFG

Deep Sleep Clock Configuration
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLDSLPCLKCFG SYSCTLDSLPCLKCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DSLPCLKCFG_O SYSCTL_DSLPCLKCFG_D

SYSCTL_DSLPCLKCFG_O : Clock Source
bits : 4 - 10 (7 bit)

Enumeration:

0x0 : SYSCTL_DSLPCLKCFG_O_IGN

MOSC

0x1 : SYSCTL_DSLPCLKCFG_O_IO

PIOSC

0x3 : SYSCTL_DSLPCLKCFG_O_30

30 kHz

0x7 : SYSCTL_DSLPCLKCFG_O_32

32.768 kHz

End of enumeration elements list.

SYSCTL_DSLPCLKCFG_D : Divider Field Override
bits : 23 - 51 (29 bit)

Enumeration:

0x0 : SYSCTL_DSLPCLKCFG_D_1

System clock /1

0x1 : SYSCTL_DSLPCLKCFG_D_2

System clock /2

0x2 : SYSCTL_DSLPCLKCFG_D_3

System clock /3

0x3 : SYSCTL_DSLPCLKCFG_D_4

System clock /4

0x4 : SYSCTL_DSLPCLKCFG_D_5

System clock /5

0x5 : SYSCTL_DSLPCLKCFG_D_6

System clock /6

0x6 : SYSCTL_DSLPCLKCFG_D_7

System clock /7

0x7 : SYSCTL_DSLPCLKCFG_D_8

System clock /8

0x8 : SYSCTL_DSLPCLKCFG_D_9

System clock /9

0x9 : SYSCTL_DSLPCLKCFG_D_10

System clock /10

0xa : SYSCTL_DSLPCLKCFG_D_11

System clock /11

0xb : SYSCTL_DSLPCLKCFG_D_12

System clock /12

0xc : SYSCTL_DSLPCLKCFG_D_13

System clock /13

0xd : SYSCTL_DSLPCLKCFG_D_14

System clock /14

0xe : SYSCTL_DSLPCLKCFG_D_15

System clock /15

0xf : SYSCTL_DSLPCLKCFG_D_16

System clock /16

0x10 : SYSCTL_DSLPCLKCFG_D_17

System clock /17

0x11 : SYSCTL_DSLPCLKCFG_D_18

System clock /18

0x12 : SYSCTL_DSLPCLKCFG_D_19

System clock /19

0x13 : SYSCTL_DSLPCLKCFG_D_20

System clock /20

0x14 : SYSCTL_DSLPCLKCFG_D_21

System clock /21

0x15 : SYSCTL_DSLPCLKCFG_D_22

System clock /22

0x16 : SYSCTL_DSLPCLKCFG_D_23

System clock /23

0x17 : SYSCTL_DSLPCLKCFG_D_24

System clock /24

0x18 : SYSCTL_DSLPCLKCFG_D_25

System clock /25

0x19 : SYSCTL_DSLPCLKCFG_D_26

System clock /26

0x1a : SYSCTL_DSLPCLKCFG_D_27

System clock /27

0x1b : SYSCTL_DSLPCLKCFG_D_28

System clock /28

0x1c : SYSCTL_DSLPCLKCFG_D_29

System clock /29

0x1d : SYSCTL_DSLPCLKCFG_D_30

System clock /30

0x1e : SYSCTL_DSLPCLKCFG_D_31

System clock /31

0x1f : SYSCTL_DSLPCLKCFG_D_32

System clock /32

0x20 : SYSCTL_DSLPCLKCFG_D_33

System clock /33

0x21 : SYSCTL_DSLPCLKCFG_D_34

System clock /34

0x22 : SYSCTL_DSLPCLKCFG_D_35

System clock /35

0x23 : SYSCTL_DSLPCLKCFG_D_36

System clock /36

0x24 : SYSCTL_DSLPCLKCFG_D_37

System clock /37

0x25 : SYSCTL_DSLPCLKCFG_D_38

System clock /38

0x26 : SYSCTL_DSLPCLKCFG_D_39

System clock /39

0x27 : SYSCTL_DSLPCLKCFG_D_40

System clock /40

0x28 : SYSCTL_DSLPCLKCFG_D_41

System clock /41

0x29 : SYSCTL_DSLPCLKCFG_D_42

System clock /42

0x2a : SYSCTL_DSLPCLKCFG_D_43

System clock /43

0x2b : SYSCTL_DSLPCLKCFG_D_44

System clock /44

0x2c : SYSCTL_DSLPCLKCFG_D_45

System clock /45

0x2d : SYSCTL_DSLPCLKCFG_D_46

System clock /46

0x2e : SYSCTL_DSLPCLKCFG_D_47

System clock /47

0x2f : SYSCTL_DSLPCLKCFG_D_48

System clock /48

0x30 : SYSCTL_DSLPCLKCFG_D_49

System clock /49

0x31 : SYSCTL_DSLPCLKCFG_D_50

System clock /50

0x32 : SYSCTL_DSLPCLKCFG_D_51

System clock /51

0x33 : SYSCTL_DSLPCLKCFG_D_52

System clock /52

0x34 : SYSCTL_DSLPCLKCFG_D_53

System clock /53

0x35 : SYSCTL_DSLPCLKCFG_D_54

System clock /54

0x36 : SYSCTL_DSLPCLKCFG_D_55

System clock /55

0x37 : SYSCTL_DSLPCLKCFG_D_56

System clock /56

0x38 : SYSCTL_DSLPCLKCFG_D_57

System clock /57

0x39 : SYSCTL_DSLPCLKCFG_D_58

System clock /58

0x3a : SYSCTL_DSLPCLKCFG_D_59

System clock /59

0x3b : SYSCTL_DSLPCLKCFG_D_60

System clock /60

0x3c : SYSCTL_DSLPCLKCFG_D_61

System clock /61

0x3d : SYSCTL_DSLPCLKCFG_D_62

System clock /62

0x3e : SYSCTL_DSLPCLKCFG_D_63

System clock /63

0x3f : SYSCTL_DSLPCLKCFG_D_64

System clock /64

End of enumeration elements list.


DSLPCLKCFG

Deep Sleep Clock Configuration
address_offset : 0x144 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSLPCLKCFG DSLPCLKCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DSLPCLKCFG_O SYSCTL_DSLPCLKCFG_D

SYSCTL_DSLPCLKCFG_O : Clock Source
bits : 4 - 10 (7 bit)

Enumeration:

0x0 : SYSCTL_DSLPCLKCFG_O_IGN

MOSC

0x1 : SYSCTL_DSLPCLKCFG_O_IO

PIOSC

0x3 : SYSCTL_DSLPCLKCFG_O_30

30 kHz

0x7 : SYSCTL_DSLPCLKCFG_O_32

32.768 kHz

End of enumeration elements list.

SYSCTL_DSLPCLKCFG_D : Divider Field Override
bits : 23 - 51 (29 bit)

Enumeration:

0x0 : SYSCTL_DSLPCLKCFG_D_1

System clock /1

0x1 : SYSCTL_DSLPCLKCFG_D_2

System clock /2

0x2 : SYSCTL_DSLPCLKCFG_D_3

System clock /3

0x3 : SYSCTL_DSLPCLKCFG_D_4

System clock /4

0x4 : SYSCTL_DSLPCLKCFG_D_5

System clock /5

0x5 : SYSCTL_DSLPCLKCFG_D_6

System clock /6

0x6 : SYSCTL_DSLPCLKCFG_D_7

System clock /7

0x7 : SYSCTL_DSLPCLKCFG_D_8

System clock /8

0x8 : SYSCTL_DSLPCLKCFG_D_9

System clock /9

0x9 : SYSCTL_DSLPCLKCFG_D_10

System clock /10

0xa : SYSCTL_DSLPCLKCFG_D_11

System clock /11

0xb : SYSCTL_DSLPCLKCFG_D_12

System clock /12

0xc : SYSCTL_DSLPCLKCFG_D_13

System clock /13

0xd : SYSCTL_DSLPCLKCFG_D_14

System clock /14

0xe : SYSCTL_DSLPCLKCFG_D_15

System clock /15

0xf : SYSCTL_DSLPCLKCFG_D_16

System clock /16

0x10 : SYSCTL_DSLPCLKCFG_D_17

System clock /17

0x11 : SYSCTL_DSLPCLKCFG_D_18

System clock /18

0x12 : SYSCTL_DSLPCLKCFG_D_19

System clock /19

0x13 : SYSCTL_DSLPCLKCFG_D_20

System clock /20

0x14 : SYSCTL_DSLPCLKCFG_D_21

System clock /21

0x15 : SYSCTL_DSLPCLKCFG_D_22

System clock /22

0x16 : SYSCTL_DSLPCLKCFG_D_23

System clock /23

0x17 : SYSCTL_DSLPCLKCFG_D_24

System clock /24

0x18 : SYSCTL_DSLPCLKCFG_D_25

System clock /25

0x19 : SYSCTL_DSLPCLKCFG_D_26

System clock /26

0x1a : SYSCTL_DSLPCLKCFG_D_27

System clock /27

0x1b : SYSCTL_DSLPCLKCFG_D_28

System clock /28

0x1c : SYSCTL_DSLPCLKCFG_D_29

System clock /29

0x1d : SYSCTL_DSLPCLKCFG_D_30

System clock /30

0x1e : SYSCTL_DSLPCLKCFG_D_31

System clock /31

0x1f : SYSCTL_DSLPCLKCFG_D_32

System clock /32

0x20 : SYSCTL_DSLPCLKCFG_D_33

System clock /33

0x21 : SYSCTL_DSLPCLKCFG_D_34

System clock /34

0x22 : SYSCTL_DSLPCLKCFG_D_35

System clock /35

0x23 : SYSCTL_DSLPCLKCFG_D_36

System clock /36

0x24 : SYSCTL_DSLPCLKCFG_D_37

System clock /37

0x25 : SYSCTL_DSLPCLKCFG_D_38

System clock /38

0x26 : SYSCTL_DSLPCLKCFG_D_39

System clock /39

0x27 : SYSCTL_DSLPCLKCFG_D_40

System clock /40

0x28 : SYSCTL_DSLPCLKCFG_D_41

System clock /41

0x29 : SYSCTL_DSLPCLKCFG_D_42

System clock /42

0x2a : SYSCTL_DSLPCLKCFG_D_43

System clock /43

0x2b : SYSCTL_DSLPCLKCFG_D_44

System clock /44

0x2c : SYSCTL_DSLPCLKCFG_D_45

System clock /45

0x2d : SYSCTL_DSLPCLKCFG_D_46

System clock /46

0x2e : SYSCTL_DSLPCLKCFG_D_47

System clock /47

0x2f : SYSCTL_DSLPCLKCFG_D_48

System clock /48

0x30 : SYSCTL_DSLPCLKCFG_D_49

System clock /49

0x31 : SYSCTL_DSLPCLKCFG_D_50

System clock /50

0x32 : SYSCTL_DSLPCLKCFG_D_51

System clock /51

0x33 : SYSCTL_DSLPCLKCFG_D_52

System clock /52

0x34 : SYSCTL_DSLPCLKCFG_D_53

System clock /53

0x35 : SYSCTL_DSLPCLKCFG_D_54

System clock /54

0x36 : SYSCTL_DSLPCLKCFG_D_55

System clock /55

0x37 : SYSCTL_DSLPCLKCFG_D_56

System clock /56

0x38 : SYSCTL_DSLPCLKCFG_D_57

System clock /57

0x39 : SYSCTL_DSLPCLKCFG_D_58

System clock /58

0x3a : SYSCTL_DSLPCLKCFG_D_59

System clock /59

0x3b : SYSCTL_DSLPCLKCFG_D_60

System clock /60

0x3c : SYSCTL_DSLPCLKCFG_D_61

System clock /61

0x3d : SYSCTL_DSLPCLKCFG_D_62

System clock /62

0x3e : SYSCTL_DSLPCLKCFG_D_63

System clock /63

0x3f : SYSCTL_DSLPCLKCFG_D_64

System clock /64

End of enumeration elements list.


SYSCTLDC3

Device Capabilities 3
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLDC3 SYSCTLDC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DC3_PWM0 SYSCTL_DC3_PWM1 SYSCTL_DC3_PWM2 SYSCTL_DC3_PWM3 SYSCTL_DC3_PWM4 SYSCTL_DC3_PWM5 SYSCTL_DC3_PWMFAULT SYSCTL_DC3_CCP0 SYSCTL_DC3_32KHZ

SYSCTL_DC3_PWM0 : PWM0 Pin Present
bits : 0 - 0 (1 bit)

SYSCTL_DC3_PWM1 : PWM1 Pin Present
bits : 1 - 2 (2 bit)

SYSCTL_DC3_PWM2 : PWM2 Pin Present
bits : 2 - 4 (3 bit)

SYSCTL_DC3_PWM3 : PWM3 Pin Present
bits : 3 - 6 (4 bit)

SYSCTL_DC3_PWM4 : PWM4 Pin Present
bits : 4 - 8 (5 bit)

SYSCTL_DC3_PWM5 : PWM5 Pin Present
bits : 5 - 10 (6 bit)

SYSCTL_DC3_PWMFAULT : PWM Fault Pin Present
bits : 15 - 30 (16 bit)

SYSCTL_DC3_CCP0 : CCP0 Pin Present
bits : 24 - 48 (25 bit)

SYSCTL_DC3_32KHZ : 32KHz Input Clock Available
bits : 31 - 62 (32 bit)


DC3

Device Capabilities 3
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DC3 DC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DC3_PWM0 SYSCTL_DC3_PWM1 SYSCTL_DC3_PWM2 SYSCTL_DC3_PWM3 SYSCTL_DC3_PWM4 SYSCTL_DC3_PWM5 SYSCTL_DC3_PWMFAULT SYSCTL_DC3_CCP0 SYSCTL_DC3_32KHZ

SYSCTL_DC3_PWM0 : PWM0 Pin Present
bits : 0 - 0 (1 bit)

SYSCTL_DC3_PWM1 : PWM1 Pin Present
bits : 1 - 2 (2 bit)

SYSCTL_DC3_PWM2 : PWM2 Pin Present
bits : 2 - 4 (3 bit)

SYSCTL_DC3_PWM3 : PWM3 Pin Present
bits : 3 - 6 (4 bit)

SYSCTL_DC3_PWM4 : PWM4 Pin Present
bits : 4 - 8 (5 bit)

SYSCTL_DC3_PWM5 : PWM5 Pin Present
bits : 5 - 10 (6 bit)

SYSCTL_DC3_PWMFAULT : PWM Fault Pin Present
bits : 15 - 30 (16 bit)

SYSCTL_DC3_CCP0 : CCP0 Pin Present
bits : 24 - 48 (25 bit)

SYSCTL_DC3_32KHZ : 32KHz Input Clock Available
bits : 31 - 62 (32 bit)


SYSCTLDC4

Device Capabilities 4
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLDC4 SYSCTLDC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DC4_GPIOA SYSCTL_DC4_GPIOB SYSCTL_DC4_GPIOC SYSCTL_DC4_GPIOD SYSCTL_DC4_GPIOE SYSCTL_DC4_ROM SYSCTL_DC4_UDMA

SYSCTL_DC4_GPIOA : GPIO Port A Present
bits : 0 - 0 (1 bit)

SYSCTL_DC4_GPIOB : GPIO Port B Present
bits : 1 - 2 (2 bit)

SYSCTL_DC4_GPIOC : GPIO Port C Present
bits : 2 - 4 (3 bit)

SYSCTL_DC4_GPIOD : GPIO Port D Present
bits : 3 - 6 (4 bit)

SYSCTL_DC4_GPIOE : GPIO Port E Present
bits : 4 - 8 (5 bit)

SYSCTL_DC4_ROM : Internal Code ROM Present
bits : 12 - 24 (13 bit)

SYSCTL_DC4_UDMA : Micro-DMA Module Present
bits : 13 - 26 (14 bit)


DC4

Device Capabilities 4
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DC4 DC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DC4_GPIOA SYSCTL_DC4_GPIOB SYSCTL_DC4_GPIOC SYSCTL_DC4_GPIOD SYSCTL_DC4_GPIOE SYSCTL_DC4_ROM SYSCTL_DC4_UDMA

SYSCTL_DC4_GPIOA : GPIO Port A Present
bits : 0 - 0 (1 bit)

SYSCTL_DC4_GPIOB : GPIO Port B Present
bits : 1 - 2 (2 bit)

SYSCTL_DC4_GPIOC : GPIO Port C Present
bits : 2 - 4 (3 bit)

SYSCTL_DC4_GPIOD : GPIO Port D Present
bits : 3 - 6 (4 bit)

SYSCTL_DC4_GPIOE : GPIO Port E Present
bits : 4 - 8 (5 bit)

SYSCTL_DC4_ROM : Internal Code ROM Present
bits : 12 - 24 (13 bit)

SYSCTL_DC4_UDMA : Micro-DMA Module Present
bits : 13 - 26 (14 bit)


SYSCTLDC5

Device Capabilities 5
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLDC5 SYSCTLDC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DC5_PWM0 SYSCTL_DC5_PWM1 SYSCTL_DC5_PWM2 SYSCTL_DC5_PWM3 SYSCTL_DC5_PWM4 SYSCTL_DC5_PWM5 SYSCTL_DC5_PWM6 SYSCTL_DC5_PWM7 SYSCTL_DC5_PWMESYNC SYSCTL_DC5_PWMEFLT SYSCTL_DC5_PWMFAULT0 SYSCTL_DC5_PWMFAULT1 SYSCTL_DC5_PWMFAULT2

SYSCTL_DC5_PWM0 : PWM0 Pin Present
bits : 0 - 0 (1 bit)

SYSCTL_DC5_PWM1 : PWM1 Pin Present
bits : 1 - 2 (2 bit)

SYSCTL_DC5_PWM2 : PWM2 Pin Present
bits : 2 - 4 (3 bit)

SYSCTL_DC5_PWM3 : PWM3 Pin Present
bits : 3 - 6 (4 bit)

SYSCTL_DC5_PWM4 : PWM4 Pin Present
bits : 4 - 8 (5 bit)

SYSCTL_DC5_PWM5 : PWM5 Pin Present
bits : 5 - 10 (6 bit)

SYSCTL_DC5_PWM6 : PWM6 Pin Present
bits : 6 - 12 (7 bit)

SYSCTL_DC5_PWM7 : PWM7 Pin Present
bits : 7 - 14 (8 bit)

SYSCTL_DC5_PWMESYNC : PWM Extended SYNC Active
bits : 20 - 40 (21 bit)

SYSCTL_DC5_PWMEFLT : PWM Extended Fault Active
bits : 21 - 42 (22 bit)

SYSCTL_DC5_PWMFAULT0 : PWM Fault 0 Pin Present
bits : 24 - 48 (25 bit)

SYSCTL_DC5_PWMFAULT1 : PWM Fault 1 Pin Present
bits : 25 - 50 (26 bit)

SYSCTL_DC5_PWMFAULT2 : PWM Fault 2 Pin Present
bits : 26 - 52 (27 bit)


DC5

Device Capabilities 5
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DC5 DC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DC5_PWM0 SYSCTL_DC5_PWM1 SYSCTL_DC5_PWM2 SYSCTL_DC5_PWM3 SYSCTL_DC5_PWM4 SYSCTL_DC5_PWM5 SYSCTL_DC5_PWM6 SYSCTL_DC5_PWM7 SYSCTL_DC5_PWMESYNC SYSCTL_DC5_PWMEFLT SYSCTL_DC5_PWMFAULT0 SYSCTL_DC5_PWMFAULT1 SYSCTL_DC5_PWMFAULT2

SYSCTL_DC5_PWM0 : PWM0 Pin Present
bits : 0 - 0 (1 bit)

SYSCTL_DC5_PWM1 : PWM1 Pin Present
bits : 1 - 2 (2 bit)

SYSCTL_DC5_PWM2 : PWM2 Pin Present
bits : 2 - 4 (3 bit)

SYSCTL_DC5_PWM3 : PWM3 Pin Present
bits : 3 - 6 (4 bit)

SYSCTL_DC5_PWM4 : PWM4 Pin Present
bits : 4 - 8 (5 bit)

SYSCTL_DC5_PWM5 : PWM5 Pin Present
bits : 5 - 10 (6 bit)

SYSCTL_DC5_PWM6 : PWM6 Pin Present
bits : 6 - 12 (7 bit)

SYSCTL_DC5_PWM7 : PWM7 Pin Present
bits : 7 - 14 (8 bit)

SYSCTL_DC5_PWMESYNC : PWM Extended SYNC Active
bits : 20 - 40 (21 bit)

SYSCTL_DC5_PWMEFLT : PWM Extended Fault Active
bits : 21 - 42 (22 bit)

SYSCTL_DC5_PWMFAULT0 : PWM Fault 0 Pin Present
bits : 24 - 48 (25 bit)

SYSCTL_DC5_PWMFAULT1 : PWM Fault 1 Pin Present
bits : 25 - 50 (26 bit)

SYSCTL_DC5_PWMFAULT2 : PWM Fault 2 Pin Present
bits : 26 - 52 (27 bit)


SYSCTLDC6

Device Capabilities 6
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLDC6 SYSCTLDC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DC6

Device Capabilities 6
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DC6 DC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYSCTLDC7

Device Capabilities 7
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLDC7 SYSCTLDC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DC7_UART0_RX SYSCTL_DC7_UART0_TX SYSCTL_DC7_SSI0_RX SYSCTL_DC7_SSI0_TX SYSCTL_DC7_SW

SYSCTL_DC7_UART0_RX : UART0 RX on uDMA Ch8
bits : 8 - 16 (9 bit)

SYSCTL_DC7_UART0_TX : UART0 TX on uDMA Ch9
bits : 9 - 18 (10 bit)

SYSCTL_DC7_SSI0_RX : SSI0 RX on uDMA Ch10
bits : 10 - 20 (11 bit)

SYSCTL_DC7_SSI0_TX : SSI0 TX on uDMA Ch11
bits : 11 - 22 (12 bit)

SYSCTL_DC7_SW : Software transfer on uDMA Ch30
bits : 30 - 60 (31 bit)


DC7

Device Capabilities 7
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DC7 DC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DC7_UART0_RX SYSCTL_DC7_UART0_TX SYSCTL_DC7_SSI0_RX SYSCTL_DC7_SSI0_TX SYSCTL_DC7_SW

SYSCTL_DC7_UART0_RX : UART0 RX on uDMA Ch8
bits : 8 - 16 (9 bit)

SYSCTL_DC7_UART0_TX : UART0 TX on uDMA Ch9
bits : 9 - 18 (10 bit)

SYSCTL_DC7_SSI0_RX : SSI0 RX on uDMA Ch10
bits : 10 - 20 (11 bit)

SYSCTL_DC7_SSI0_TX : SSI0 TX on uDMA Ch11
bits : 11 - 22 (12 bit)

SYSCTL_DC7_SW : Software transfer on uDMA Ch30
bits : 30 - 60 (31 bit)


SYSCTLPBORCTL

Brown-Out Reset Control
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLPBORCTL SYSCTLPBORCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_PBORCTL_BORIOR

SYSCTL_PBORCTL_BORIOR : BOR Interrupt or Reset
bits : 1 - 2 (2 bit)


PBORCTL

Brown-Out Reset Control
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PBORCTL PBORCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_PBORCTL_BORIOR

SYSCTL_PBORCTL_BORIOR : BOR Interrupt or Reset
bits : 1 - 2 (2 bit)


SYSCTLLDOPCTL

LDO Power Control
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLLDOPCTL SYSCTLLDOPCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_LDOPCTL

SYSCTL_LDOPCTL : LDO Output Voltage
bits : 0 - 5 (6 bit)

Enumeration:

0x0 : SYSCTL_LDOPCTL_2_50V

2.50

0x1 : SYSCTL_LDOPCTL_2_45V

2.45

0x2 : SYSCTL_LDOPCTL_2_40V

2.40

0x3 : SYSCTL_LDOPCTL_2_35V

2.35

0x4 : SYSCTL_LDOPCTL_2_30V

2.30

0x5 : SYSCTL_LDOPCTL_2_25V

2.25

0x1b : SYSCTL_LDOPCTL_2_75V

2.75

0x1c : SYSCTL_LDOPCTL_2_70V

2.70

0x1d : SYSCTL_LDOPCTL_2_65V

2.65

0x1e : SYSCTL_LDOPCTL_2_60V

2.60

0x1f : SYSCTL_LDOPCTL_2_55V

2.55

End of enumeration elements list.


LDOPCTL

LDO Power Control
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LDOPCTL LDOPCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_LDOPCTL

SYSCTL_LDOPCTL : LDO Output Voltage
bits : 0 - 5 (6 bit)

Enumeration:

0x0 : SYSCTL_LDOPCTL_2_50V

2.50

0x1 : SYSCTL_LDOPCTL_2_45V

2.45

0x2 : SYSCTL_LDOPCTL_2_40V

2.40

0x3 : SYSCTL_LDOPCTL_2_35V

2.35

0x4 : SYSCTL_LDOPCTL_2_30V

2.30

0x5 : SYSCTL_LDOPCTL_2_25V

2.25

0x1b : SYSCTL_LDOPCTL_2_75V

2.75

0x1c : SYSCTL_LDOPCTL_2_70V

2.70

0x1d : SYSCTL_LDOPCTL_2_65V

2.65

0x1e : SYSCTL_LDOPCTL_2_60V

2.60

0x1f : SYSCTL_LDOPCTL_2_55V

2.55

End of enumeration elements list.


SYSCTLDID1

Device Identification 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLDID1 SYSCTLDID1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DID1_QUAL SYSCTL_DID1_ROHS SYSCTL_DID1_PKG SYSCTL_DID1_TEMP SYSCTL_DID1_PINCNT SYSCTL_DID1_PRTNO SYSCTL_DID1_FAM SYSCTL_DID1_VER

SYSCTL_DID1_QUAL : Qualification Status
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : SYSCTL_DID1_QUAL_ES

Engineering Sample (unqualified)

0x1 : SYSCTL_DID1_QUAL_PP

Pilot Production (unqualified)

0x2 : SYSCTL_DID1_QUAL_FQ

Fully Qualified

End of enumeration elements list.

SYSCTL_DID1_ROHS : RoHS-Compliance
bits : 2 - 4 (3 bit)

SYSCTL_DID1_PKG : Package Type
bits : 3 - 7 (5 bit)

Enumeration:

0x0 : SYSCTL_DID1_PKG_SOIC

SOIC package

0x1 : SYSCTL_DID1_PKG_QFP

LQFP package

0x2 : SYSCTL_DID1_PKG_BGA

BGA package

End of enumeration elements list.

SYSCTL_DID1_TEMP : Temperature Range
bits : 5 - 12 (8 bit)

Enumeration:

0x0 : SYSCTL_DID1_TEMP_C

Commercial temperature range (0C to 70C)

0x1 : SYSCTL_DID1_TEMP_I

Industrial temperature range (-40C to 85C)

0x2 : SYSCTL_DID1_TEMP_E

Extended temperature range (-40C to 105C)

End of enumeration elements list.

SYSCTL_DID1_PINCNT : Package Pin Count
bits : 13 - 28 (16 bit)

Enumeration:

0x3 : SYSCTL_DID1_PINCNT_64

64-pin package

End of enumeration elements list.

SYSCTL_DID1_PRTNO : Part Number
bits : 16 - 39 (24 bit)

Enumeration:

0x39 : SYSCTL_DID1_PRTNO_2276

LM3S2276

End of enumeration elements list.

SYSCTL_DID1_FAM : Family
bits : 24 - 51 (28 bit)

Enumeration:

0x0 : SYSCTL_DID1_FAM_STELLARIS

Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S

End of enumeration elements list.

SYSCTL_DID1_VER : DID1 Version
bits : 28 - 59 (32 bit)

Enumeration:

0x1 : SYSCTL_DID1_VER_1

Second version of the DID1 register format

End of enumeration elements list.


DID1

Device Identification 1
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DID1 DID1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DID1_QUAL SYSCTL_DID1_ROHS SYSCTL_DID1_PKG SYSCTL_DID1_TEMP SYSCTL_DID1_PINCNT SYSCTL_DID1_PRTNO SYSCTL_DID1_FAM SYSCTL_DID1_VER

SYSCTL_DID1_QUAL : Qualification Status
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : SYSCTL_DID1_QUAL_ES

Engineering Sample (unqualified)

0x1 : SYSCTL_DID1_QUAL_PP

Pilot Production (unqualified)

0x2 : SYSCTL_DID1_QUAL_FQ

Fully Qualified

End of enumeration elements list.

SYSCTL_DID1_ROHS : RoHS-Compliance
bits : 2 - 4 (3 bit)

SYSCTL_DID1_PKG : Package Type
bits : 3 - 7 (5 bit)

Enumeration:

0x0 : SYSCTL_DID1_PKG_SOIC

SOIC package

0x1 : SYSCTL_DID1_PKG_QFP

LQFP package

0x2 : SYSCTL_DID1_PKG_BGA

BGA package

End of enumeration elements list.

SYSCTL_DID1_TEMP : Temperature Range
bits : 5 - 12 (8 bit)

Enumeration:

0x0 : SYSCTL_DID1_TEMP_C

Commercial temperature range (0C to 70C)

0x1 : SYSCTL_DID1_TEMP_I

Industrial temperature range (-40C to 85C)

0x2 : SYSCTL_DID1_TEMP_E

Extended temperature range (-40C to 105C)

End of enumeration elements list.

SYSCTL_DID1_PINCNT : Package Pin Count
bits : 13 - 28 (16 bit)

Enumeration:

0x3 : SYSCTL_DID1_PINCNT_64

64-pin package

End of enumeration elements list.

SYSCTL_DID1_PRTNO : Part Number
bits : 16 - 39 (24 bit)

Enumeration:

0x39 : SYSCTL_DID1_PRTNO_2276

LM3S2276

End of enumeration elements list.

SYSCTL_DID1_FAM : Family
bits : 24 - 51 (28 bit)

Enumeration:

0x0 : SYSCTL_DID1_FAM_STELLARIS

Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S

End of enumeration elements list.

SYSCTL_DID1_VER : DID1 Version
bits : 28 - 59 (32 bit)

Enumeration:

0x1 : SYSCTL_DID1_VER_1

Second version of the DID1 register format

End of enumeration elements list.


SYSCTLSRCR0

Software Reset Control 0
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLSRCR0 SYSCTLSRCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_SRCR0_HIB SYSCTL_SRCR0_CAN0

SYSCTL_SRCR0_HIB : HIB Reset Control
bits : 6 - 12 (7 bit)

SYSCTL_SRCR0_CAN0 : CAN0 Reset Control
bits : 24 - 48 (25 bit)


SRCR0

Software Reset Control 0
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRCR0 SRCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_SRCR0_HIB SYSCTL_SRCR0_CAN0

SYSCTL_SRCR0_HIB : HIB Reset Control
bits : 6 - 12 (7 bit)

SYSCTL_SRCR0_CAN0 : CAN0 Reset Control
bits : 24 - 48 (25 bit)


SYSCTLSRCR1

Software Reset Control 1
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLSRCR1 SYSCTLSRCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_SRCR1_UART0 SYSCTL_SRCR1_SSI0 SYSCTL_SRCR1_I2C0 SYSCTL_SRCR1_TIMER0 SYSCTL_SRCR1_TIMER1 SYSCTL_SRCR1_TIMER2

SYSCTL_SRCR1_UART0 : UART0 Reset Control
bits : 0 - 0 (1 bit)

SYSCTL_SRCR1_SSI0 : SSI0 Reset Control
bits : 4 - 8 (5 bit)

SYSCTL_SRCR1_I2C0 : I2C0 Reset Control
bits : 12 - 24 (13 bit)

SYSCTL_SRCR1_TIMER0 : Timer 0 Reset Control
bits : 16 - 32 (17 bit)

SYSCTL_SRCR1_TIMER1 : Timer 1 Reset Control
bits : 17 - 34 (18 bit)

SYSCTL_SRCR1_TIMER2 : Timer 2 Reset Control
bits : 18 - 36 (19 bit)


SRCR1

Software Reset Control 1
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRCR1 SRCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_SRCR1_UART0 SYSCTL_SRCR1_SSI0 SYSCTL_SRCR1_I2C0 SYSCTL_SRCR1_TIMER0 SYSCTL_SRCR1_TIMER1 SYSCTL_SRCR1_TIMER2

SYSCTL_SRCR1_UART0 : UART0 Reset Control
bits : 0 - 0 (1 bit)

SYSCTL_SRCR1_SSI0 : SSI0 Reset Control
bits : 4 - 8 (5 bit)

SYSCTL_SRCR1_I2C0 : I2C0 Reset Control
bits : 12 - 24 (13 bit)

SYSCTL_SRCR1_TIMER0 : Timer 0 Reset Control
bits : 16 - 32 (17 bit)

SYSCTL_SRCR1_TIMER1 : Timer 1 Reset Control
bits : 17 - 34 (18 bit)

SYSCTL_SRCR1_TIMER2 : Timer 2 Reset Control
bits : 18 - 36 (19 bit)


SYSCTLSRCR2

Software Reset Control 2
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLSRCR2 SYSCTLSRCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_SRCR2_GPIOA SYSCTL_SRCR2_GPIOB SYSCTL_SRCR2_GPIOC SYSCTL_SRCR2_GPIOD SYSCTL_SRCR2_GPIOE SYSCTL_SRCR2_UDMA

SYSCTL_SRCR2_GPIOA : Port A Reset Control
bits : 0 - 0 (1 bit)

SYSCTL_SRCR2_GPIOB : Port B Reset Control
bits : 1 - 2 (2 bit)

SYSCTL_SRCR2_GPIOC : Port C Reset Control
bits : 2 - 4 (3 bit)

SYSCTL_SRCR2_GPIOD : Port D Reset Control
bits : 3 - 6 (4 bit)

SYSCTL_SRCR2_GPIOE : Port E Reset Control
bits : 4 - 8 (5 bit)

SYSCTL_SRCR2_UDMA : Micro-DMA Reset Control
bits : 13 - 26 (14 bit)


SRCR2

Software Reset Control 2
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRCR2 SRCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_SRCR2_GPIOA SYSCTL_SRCR2_GPIOB SYSCTL_SRCR2_GPIOC SYSCTL_SRCR2_GPIOD SYSCTL_SRCR2_GPIOE SYSCTL_SRCR2_UDMA

SYSCTL_SRCR2_GPIOA : Port A Reset Control
bits : 0 - 0 (1 bit)

SYSCTL_SRCR2_GPIOB : Port B Reset Control
bits : 1 - 2 (2 bit)

SYSCTL_SRCR2_GPIOC : Port C Reset Control
bits : 2 - 4 (3 bit)

SYSCTL_SRCR2_GPIOD : Port D Reset Control
bits : 3 - 6 (4 bit)

SYSCTL_SRCR2_GPIOE : Port E Reset Control
bits : 4 - 8 (5 bit)

SYSCTL_SRCR2_UDMA : Micro-DMA Reset Control
bits : 13 - 26 (14 bit)


SYSCTLRIS

Raw Interrupt Status
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLRIS SYSCTLRIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_RIS_BORRIS SYSCTL_RIS_PLLLRIS SYSCTL_RIS_MOSCPUPRIS

SYSCTL_RIS_BORRIS : Brown-Out Reset Raw Interrupt Status
bits : 1 - 2 (2 bit)

SYSCTL_RIS_PLLLRIS : PLL Lock Raw Interrupt Status
bits : 6 - 12 (7 bit)

SYSCTL_RIS_MOSCPUPRIS : MOSC Power Up Raw Interrupt Status
bits : 8 - 16 (9 bit)


RIS

Raw Interrupt Status
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_RIS_BORRIS SYSCTL_RIS_PLLLRIS SYSCTL_RIS_MOSCPUPRIS

SYSCTL_RIS_BORRIS : Brown-Out Reset Raw Interrupt Status
bits : 1 - 2 (2 bit)

SYSCTL_RIS_PLLLRIS : PLL Lock Raw Interrupt Status
bits : 6 - 12 (7 bit)

SYSCTL_RIS_MOSCPUPRIS : MOSC Power Up Raw Interrupt Status
bits : 8 - 16 (9 bit)


SYSCTLIMC

Interrupt Mask Control
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLIMC SYSCTLIMC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_IMC_BORIM SYSCTL_IMC_PLLLIM SYSCTL_IMC_MOSCPUPIM

SYSCTL_IMC_BORIM : Brown-Out Reset Interrupt Mask
bits : 1 - 2 (2 bit)

SYSCTL_IMC_PLLLIM : PLL Lock Interrupt Mask
bits : 6 - 12 (7 bit)

SYSCTL_IMC_MOSCPUPIM : MOSC Power Up Interrupt Mask
bits : 8 - 16 (9 bit)


IMC

Interrupt Mask Control
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMC IMC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_IMC_BORIM SYSCTL_IMC_PLLLIM SYSCTL_IMC_MOSCPUPIM

SYSCTL_IMC_BORIM : Brown-Out Reset Interrupt Mask
bits : 1 - 2 (2 bit)

SYSCTL_IMC_PLLLIM : PLL Lock Interrupt Mask
bits : 6 - 12 (7 bit)

SYSCTL_IMC_MOSCPUPIM : MOSC Power Up Interrupt Mask
bits : 8 - 16 (9 bit)


SYSCTLMISC

Masked Interrupt Status and Clear
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLMISC SYSCTLMISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_MISC_BORMIS SYSCTL_MISC_PLLLMIS SYSCTL_MISC_MOSCPUPMIS

SYSCTL_MISC_BORMIS : BOR Masked Interrupt Status
bits : 1 - 2 (2 bit)

SYSCTL_MISC_PLLLMIS : PLL Lock Masked Interrupt Status
bits : 6 - 12 (7 bit)

SYSCTL_MISC_MOSCPUPMIS : MOSC Power Up Masked Interrupt Status
bits : 8 - 16 (9 bit)


MISC

Masked Interrupt Status and Clear
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MISC MISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_MISC_BORMIS SYSCTL_MISC_PLLLMIS SYSCTL_MISC_MOSCPUPMIS

SYSCTL_MISC_BORMIS : BOR Masked Interrupt Status
bits : 1 - 2 (2 bit)

SYSCTL_MISC_PLLLMIS : PLL Lock Masked Interrupt Status
bits : 6 - 12 (7 bit)

SYSCTL_MISC_MOSCPUPMIS : MOSC Power Up Masked Interrupt Status
bits : 8 - 16 (9 bit)


SYSCTLRESC

Reset Cause
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLRESC SYSCTLRESC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_RESC_EXT SYSCTL_RESC_POR SYSCTL_RESC_BOR SYSCTL_RESC_SW SYSCTL_RESC_MOSCFAIL

SYSCTL_RESC_EXT : External Reset
bits : 0 - 0 (1 bit)

SYSCTL_RESC_POR : Power-On Reset
bits : 1 - 2 (2 bit)

SYSCTL_RESC_BOR : Brown-Out Reset
bits : 2 - 4 (3 bit)

SYSCTL_RESC_SW : Software Reset
bits : 4 - 8 (5 bit)

SYSCTL_RESC_MOSCFAIL : MOSC Failure Reset
bits : 16 - 32 (17 bit)


RESC

Reset Cause
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESC RESC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_RESC_EXT SYSCTL_RESC_POR SYSCTL_RESC_BOR SYSCTL_RESC_SW SYSCTL_RESC_MOSCFAIL

SYSCTL_RESC_EXT : External Reset
bits : 0 - 0 (1 bit)

SYSCTL_RESC_POR : Power-On Reset
bits : 1 - 2 (2 bit)

SYSCTL_RESC_BOR : Brown-Out Reset
bits : 2 - 4 (3 bit)

SYSCTL_RESC_SW : Software Reset
bits : 4 - 8 (5 bit)

SYSCTL_RESC_MOSCFAIL : MOSC Failure Reset
bits : 16 - 32 (17 bit)


SYSCTLRCC

Run-Mode Clock Configuration
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLRCC SYSCTLRCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_RCC_MOSCDIS SYSCTL_RCC_IOSCDIS SYSCTL_RCC_OSCSRC SYSCTL_RCC_XTAL SYSCTL_RCC_BYPASS SYSCTL_RCC_PWRDN SYSCTL_RCC_PWMDIV SYSCTL_RCC_USEPWMDIV SYSCTL_RCC_USESYSDIV SYSCTL_RCC_SYSDIV SYSCTL_RCC_ACG

SYSCTL_RCC_MOSCDIS : Main Oscillator Disable
bits : 0 - 0 (1 bit)

SYSCTL_RCC_IOSCDIS : Internal Oscillator Disable
bits : 1 - 2 (2 bit)

SYSCTL_RCC_OSCSRC : Oscillator Source
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : SYSCTL_RCC_OSCSRC_MAIN

MOSC

0x1 : SYSCTL_RCC_OSCSRC_INT

IOSC

0x2 : SYSCTL_RCC_OSCSRC_INT4

IOSC/4

0x3 : SYSCTL_RCC_OSCSRC_30

30 kHz

End of enumeration elements list.

SYSCTL_RCC_XTAL : Crystal Value
bits : 6 - 16 (11 bit)

Enumeration:

0x0 : SYSCTL_RCC_XTAL_1MHZ

1 MHz

0x1 : SYSCTL_RCC_XTAL_1_84MHZ

1.8432 MHz

0x2 : SYSCTL_RCC_XTAL_2MHZ

2 MHz

0x3 : SYSCTL_RCC_XTAL_2_45MHZ

2.4576 MHz

0x4 : SYSCTL_RCC_XTAL_3_57MHZ

3.579545 MHz

0x5 : SYSCTL_RCC_XTAL_3_68MHZ

3.6864 MHz

0x6 : SYSCTL_RCC_XTAL_4MHZ

4 MHz

0x7 : SYSCTL_RCC_XTAL_4_09MHZ

4.096 MHz

0x8 : SYSCTL_RCC_XTAL_4_91MHZ

4.9152 MHz

0x9 : SYSCTL_RCC_XTAL_5MHZ

5 MHz

0xa : SYSCTL_RCC_XTAL_5_12MHZ

5.12 MHz

0xb : SYSCTL_RCC_XTAL_6MHZ

6 MHz

0xc : SYSCTL_RCC_XTAL_6_14MHZ

6.144 MHz

0xd : SYSCTL_RCC_XTAL_7_37MHZ

7.3728 MHz

0xe : SYSCTL_RCC_XTAL_8MHZ

8 MHz

0xf : SYSCTL_RCC_XTAL_8_19MHZ

8.192 MHz

0x10 : SYSCTL_RCC_XTAL_10MHZ

10 MHz

0x11 : SYSCTL_RCC_XTAL_12MHZ

12 MHz

0x12 : SYSCTL_RCC_XTAL_12_2MHZ

12.288 MHz

0x13 : SYSCTL_RCC_XTAL_13_5MHZ

13.56 MHz

0x14 : SYSCTL_RCC_XTAL_14_3MHZ

14.31818 MHz

0x15 : SYSCTL_RCC_XTAL_16MHZ

16 MHz

0x16 : SYSCTL_RCC_XTAL_16_3MHZ

16.384 MHz

End of enumeration elements list.

SYSCTL_RCC_BYPASS : PLL Bypass
bits : 11 - 22 (12 bit)

SYSCTL_RCC_PWRDN : PLL Power Down
bits : 13 - 26 (14 bit)

SYSCTL_RCC_PWMDIV : PWM Unit Clock Divisor
bits : 17 - 36 (20 bit)

Enumeration:

0x0 : SYSCTL_RCC_PWMDIV_2

PWM clock /2

0x1 : SYSCTL_RCC_PWMDIV_4

PWM clock /4

0x2 : SYSCTL_RCC_PWMDIV_8

PWM clock /8

0x3 : SYSCTL_RCC_PWMDIV_16

PWM clock /16

0x4 : SYSCTL_RCC_PWMDIV_32

PWM clock /32

0x5 : SYSCTL_RCC_PWMDIV_64

PWM clock /64

End of enumeration elements list.

SYSCTL_RCC_USEPWMDIV : Enable PWM Clock Divisor
bits : 20 - 40 (21 bit)

SYSCTL_RCC_USESYSDIV : Enable System Clock Divider
bits : 22 - 44 (23 bit)

SYSCTL_RCC_SYSDIV : System Clock Divisor
bits : 23 - 49 (27 bit)

Enumeration:

0x1 : SYSCTL_RCC_SYSDIV_2

System clock /2

0x2 : SYSCTL_RCC_SYSDIV_3

System clock /3

0x3 : SYSCTL_RCC_SYSDIV_4

System clock /4

0x4 : SYSCTL_RCC_SYSDIV_5

System clock /5

0x5 : SYSCTL_RCC_SYSDIV_6

System clock /6

0x6 : SYSCTL_RCC_SYSDIV_7

System clock /7

0x7 : SYSCTL_RCC_SYSDIV_8

System clock /8

0x8 : SYSCTL_RCC_SYSDIV_9

System clock /9

0x9 : SYSCTL_RCC_SYSDIV_10

System clock /10

0xa : SYSCTL_RCC_SYSDIV_11

System clock /11

0xb : SYSCTL_RCC_SYSDIV_12

System clock /12

0xc : SYSCTL_RCC_SYSDIV_13

System clock /13

0xd : SYSCTL_RCC_SYSDIV_14

System clock /14

0xe : SYSCTL_RCC_SYSDIV_15

System clock /15

0xf : SYSCTL_RCC_SYSDIV_16

System clock /16

End of enumeration elements list.

SYSCTL_RCC_ACG : Auto Clock Gating
bits : 27 - 54 (28 bit)


RCC

Run-Mode Clock Configuration
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCC RCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_RCC_MOSCDIS SYSCTL_RCC_IOSCDIS SYSCTL_RCC_OSCSRC SYSCTL_RCC_XTAL SYSCTL_RCC_BYPASS SYSCTL_RCC_PWRDN SYSCTL_RCC_PWMDIV SYSCTL_RCC_USEPWMDIV SYSCTL_RCC_USESYSDIV SYSCTL_RCC_SYSDIV SYSCTL_RCC_ACG

SYSCTL_RCC_MOSCDIS : Main Oscillator Disable
bits : 0 - 0 (1 bit)

SYSCTL_RCC_IOSCDIS : Internal Oscillator Disable
bits : 1 - 2 (2 bit)

SYSCTL_RCC_OSCSRC : Oscillator Source
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : SYSCTL_RCC_OSCSRC_MAIN

MOSC

0x1 : SYSCTL_RCC_OSCSRC_INT

IOSC

0x2 : SYSCTL_RCC_OSCSRC_INT4

IOSC/4

0x3 : SYSCTL_RCC_OSCSRC_30

30 kHz

End of enumeration elements list.

SYSCTL_RCC_XTAL : Crystal Value
bits : 6 - 16 (11 bit)

Enumeration:

0x0 : SYSCTL_RCC_XTAL_1MHZ

1 MHz

0x1 : SYSCTL_RCC_XTAL_1_84MHZ

1.8432 MHz

0x2 : SYSCTL_RCC_XTAL_2MHZ

2 MHz

0x3 : SYSCTL_RCC_XTAL_2_45MHZ

2.4576 MHz

0x4 : SYSCTL_RCC_XTAL_3_57MHZ

3.579545 MHz

0x5 : SYSCTL_RCC_XTAL_3_68MHZ

3.6864 MHz

0x6 : SYSCTL_RCC_XTAL_4MHZ

4 MHz

0x7 : SYSCTL_RCC_XTAL_4_09MHZ

4.096 MHz

0x8 : SYSCTL_RCC_XTAL_4_91MHZ

4.9152 MHz

0x9 : SYSCTL_RCC_XTAL_5MHZ

5 MHz

0xa : SYSCTL_RCC_XTAL_5_12MHZ

5.12 MHz

0xb : SYSCTL_RCC_XTAL_6MHZ

6 MHz

0xc : SYSCTL_RCC_XTAL_6_14MHZ

6.144 MHz

0xd : SYSCTL_RCC_XTAL_7_37MHZ

7.3728 MHz

0xe : SYSCTL_RCC_XTAL_8MHZ

8 MHz

0xf : SYSCTL_RCC_XTAL_8_19MHZ

8.192 MHz

0x10 : SYSCTL_RCC_XTAL_10MHZ

10 MHz

0x11 : SYSCTL_RCC_XTAL_12MHZ

12 MHz

0x12 : SYSCTL_RCC_XTAL_12_2MHZ

12.288 MHz

0x13 : SYSCTL_RCC_XTAL_13_5MHZ

13.56 MHz

0x14 : SYSCTL_RCC_XTAL_14_3MHZ

14.31818 MHz

0x15 : SYSCTL_RCC_XTAL_16MHZ

16 MHz

0x16 : SYSCTL_RCC_XTAL_16_3MHZ

16.384 MHz

End of enumeration elements list.

SYSCTL_RCC_BYPASS : PLL Bypass
bits : 11 - 22 (12 bit)

SYSCTL_RCC_PWRDN : PLL Power Down
bits : 13 - 26 (14 bit)

SYSCTL_RCC_PWMDIV : PWM Unit Clock Divisor
bits : 17 - 36 (20 bit)

Enumeration:

0x0 : SYSCTL_RCC_PWMDIV_2

PWM clock /2

0x1 : SYSCTL_RCC_PWMDIV_4

PWM clock /4

0x2 : SYSCTL_RCC_PWMDIV_8

PWM clock /8

0x3 : SYSCTL_RCC_PWMDIV_16

PWM clock /16

0x4 : SYSCTL_RCC_PWMDIV_32

PWM clock /32

0x5 : SYSCTL_RCC_PWMDIV_64

PWM clock /64

End of enumeration elements list.

SYSCTL_RCC_USEPWMDIV : Enable PWM Clock Divisor
bits : 20 - 40 (21 bit)

SYSCTL_RCC_USESYSDIV : Enable System Clock Divider
bits : 22 - 44 (23 bit)

SYSCTL_RCC_SYSDIV : System Clock Divisor
bits : 23 - 49 (27 bit)

Enumeration:

0x1 : SYSCTL_RCC_SYSDIV_2

System clock /2

0x2 : SYSCTL_RCC_SYSDIV_3

System clock /3

0x3 : SYSCTL_RCC_SYSDIV_4

System clock /4

0x4 : SYSCTL_RCC_SYSDIV_5

System clock /5

0x5 : SYSCTL_RCC_SYSDIV_6

System clock /6

0x6 : SYSCTL_RCC_SYSDIV_7

System clock /7

0x7 : SYSCTL_RCC_SYSDIV_8

System clock /8

0x8 : SYSCTL_RCC_SYSDIV_9

System clock /9

0x9 : SYSCTL_RCC_SYSDIV_10

System clock /10

0xa : SYSCTL_RCC_SYSDIV_11

System clock /11

0xb : SYSCTL_RCC_SYSDIV_12

System clock /12

0xc : SYSCTL_RCC_SYSDIV_13

System clock /13

0xd : SYSCTL_RCC_SYSDIV_14

System clock /14

0xe : SYSCTL_RCC_SYSDIV_15

System clock /15

0xf : SYSCTL_RCC_SYSDIV_16

System clock /16

End of enumeration elements list.

SYSCTL_RCC_ACG : Auto Clock Gating
bits : 27 - 54 (28 bit)


SYSCTLPLLCFG

XTAL to PLL Translation
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLPLLCFG SYSCTLPLLCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_PLLCFG_R SYSCTL_PLLCFG_F

SYSCTL_PLLCFG_R : PLL R Value
bits : 0 - 4 (5 bit)

SYSCTL_PLLCFG_F : PLL F Value
bits : 5 - 18 (14 bit)


PLLCFG

XTAL to PLL Translation
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLCFG PLLCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_PLLCFG_R SYSCTL_PLLCFG_F

SYSCTL_PLLCFG_R : PLL R Value
bits : 0 - 4 (5 bit)

SYSCTL_PLLCFG_F : PLL F Value
bits : 5 - 18 (14 bit)


SYSCTLGPIOHBCTL

GPIO High-Performance Bus Control
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLGPIOHBCTL SYSCTLGPIOHBCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_GPIOHBCTL_PORTA SYSCTL_GPIOHBCTL_PORTB SYSCTL_GPIOHBCTL_PORTC SYSCTL_GPIOHBCTL_PORTD SYSCTL_GPIOHBCTL_PORTE

SYSCTL_GPIOHBCTL_PORTA : Port A Advanced High-Performance Bus
bits : 0 - 0 (1 bit)

SYSCTL_GPIOHBCTL_PORTB : Port B Advanced High-Performance Bus
bits : 1 - 2 (2 bit)

SYSCTL_GPIOHBCTL_PORTC : Port C Advanced High-Performance Bus
bits : 2 - 4 (3 bit)

SYSCTL_GPIOHBCTL_PORTD : Port D Advanced High-Performance Bus
bits : 3 - 6 (4 bit)

SYSCTL_GPIOHBCTL_PORTE : Port E Advanced High-Performance Bus
bits : 4 - 8 (5 bit)


GPIOHBCTL

GPIO High-Performance Bus Control
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOHBCTL GPIOHBCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_GPIOHBCTL_PORTA SYSCTL_GPIOHBCTL_PORTB SYSCTL_GPIOHBCTL_PORTC SYSCTL_GPIOHBCTL_PORTD SYSCTL_GPIOHBCTL_PORTE

SYSCTL_GPIOHBCTL_PORTA : Port A Advanced High-Performance Bus
bits : 0 - 0 (1 bit)

SYSCTL_GPIOHBCTL_PORTB : Port B Advanced High-Performance Bus
bits : 1 - 2 (2 bit)

SYSCTL_GPIOHBCTL_PORTC : Port C Advanced High-Performance Bus
bits : 2 - 4 (3 bit)

SYSCTL_GPIOHBCTL_PORTD : Port D Advanced High-Performance Bus
bits : 3 - 6 (4 bit)

SYSCTL_GPIOHBCTL_PORTE : Port E Advanced High-Performance Bus
bits : 4 - 8 (5 bit)


SYSCTLRCC2

Run-Mode Clock Configuration 2
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLRCC2 SYSCTLRCC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_RCC2_OSCSRC2 SYSCTL_RCC2_BYPASS2 SYSCTL_RCC2_PWRDN2 SYSCTL_RCC2_SYSDIV2 SYSCTL_RCC2_USERCC2

SYSCTL_RCC2_OSCSRC2 : Oscillator Source 2
bits : 4 - 10 (7 bit)

Enumeration:

0x0 : SYSCTL_RCC2_OSCSRC2_MO

MOSC

0x1 : SYSCTL_RCC2_OSCSRC2_IO

PIOSC

0x2 : SYSCTL_RCC2_OSCSRC2_IO4

PIOSC/4

0x3 : SYSCTL_RCC2_OSCSRC2_30

30 kHz

0x7 : SYSCTL_RCC2_OSCSRC2_32

32.768 kHz

End of enumeration elements list.

SYSCTL_RCC2_BYPASS2 : PLL Bypass 2
bits : 11 - 22 (12 bit)

SYSCTL_RCC2_PWRDN2 : Power-Down PLL 2
bits : 13 - 26 (14 bit)

SYSCTL_RCC2_SYSDIV2 : System Clock Divisor 2
bits : 23 - 51 (29 bit)

Enumeration:

0x1 : SYSCTL_RCC2_SYSDIV2_2

System clock /2

0x2 : SYSCTL_RCC2_SYSDIV2_3

System clock /3

0x3 : SYSCTL_RCC2_SYSDIV2_4

System clock /4

0x4 : SYSCTL_RCC2_SYSDIV2_5

System clock /5

0x5 : SYSCTL_RCC2_SYSDIV2_6

System clock /6

0x6 : SYSCTL_RCC2_SYSDIV2_7

System clock /7

0x7 : SYSCTL_RCC2_SYSDIV2_8

System clock /8

0x8 : SYSCTL_RCC2_SYSDIV2_9

System clock /9

0x9 : SYSCTL_RCC2_SYSDIV2_10

System clock /10

0xa : SYSCTL_RCC2_SYSDIV2_11

System clock /11

0xb : SYSCTL_RCC2_SYSDIV2_12

System clock /12

0xc : SYSCTL_RCC2_SYSDIV2_13

System clock /13

0xd : SYSCTL_RCC2_SYSDIV2_14

System clock /14

0xe : SYSCTL_RCC2_SYSDIV2_15

System clock /15

0xf : SYSCTL_RCC2_SYSDIV2_16

System clock /16

0x10 : SYSCTL_RCC2_SYSDIV2_17

System clock /17

0x11 : SYSCTL_RCC2_SYSDIV2_18

System clock /18

0x12 : SYSCTL_RCC2_SYSDIV2_19

System clock /19

0x13 : SYSCTL_RCC2_SYSDIV2_20

System clock /20

0x14 : SYSCTL_RCC2_SYSDIV2_21

System clock /21

0x15 : SYSCTL_RCC2_SYSDIV2_22

System clock /22

0x16 : SYSCTL_RCC2_SYSDIV2_23

System clock /23

0x17 : SYSCTL_RCC2_SYSDIV2_24

System clock /24

0x18 : SYSCTL_RCC2_SYSDIV2_25

System clock /25

0x19 : SYSCTL_RCC2_SYSDIV2_26

System clock /26

0x1a : SYSCTL_RCC2_SYSDIV2_27

System clock /27

0x1b : SYSCTL_RCC2_SYSDIV2_28

System clock /28

0x1c : SYSCTL_RCC2_SYSDIV2_29

System clock /29

0x1d : SYSCTL_RCC2_SYSDIV2_30

System clock /30

0x1e : SYSCTL_RCC2_SYSDIV2_31

System clock /31

0x1f : SYSCTL_RCC2_SYSDIV2_32

System clock /32

0x20 : SYSCTL_RCC2_SYSDIV2_33

System clock /33

0x21 : SYSCTL_RCC2_SYSDIV2_34

System clock /34

0x22 : SYSCTL_RCC2_SYSDIV2_35

System clock /35

0x23 : SYSCTL_RCC2_SYSDIV2_36

System clock /36

0x24 : SYSCTL_RCC2_SYSDIV2_37

System clock /37

0x25 : SYSCTL_RCC2_SYSDIV2_38

System clock /38

0x26 : SYSCTL_RCC2_SYSDIV2_39

System clock /39

0x27 : SYSCTL_RCC2_SYSDIV2_40

System clock /40

0x28 : SYSCTL_RCC2_SYSDIV2_41

System clock /41

0x29 : SYSCTL_RCC2_SYSDIV2_42

System clock /42

0x2a : SYSCTL_RCC2_SYSDIV2_43

System clock /43

0x2b : SYSCTL_RCC2_SYSDIV2_44

System clock /44

0x2c : SYSCTL_RCC2_SYSDIV2_45

System clock /45

0x2d : SYSCTL_RCC2_SYSDIV2_46

System clock /46

0x2e : SYSCTL_RCC2_SYSDIV2_47

System clock /47

0x2f : SYSCTL_RCC2_SYSDIV2_48

System clock /48

0x30 : SYSCTL_RCC2_SYSDIV2_49

System clock /49

0x31 : SYSCTL_RCC2_SYSDIV2_50

System clock /50

0x32 : SYSCTL_RCC2_SYSDIV2_51

System clock /51

0x33 : SYSCTL_RCC2_SYSDIV2_52

System clock /52

0x34 : SYSCTL_RCC2_SYSDIV2_53

System clock /53

0x35 : SYSCTL_RCC2_SYSDIV2_54

System clock /54

0x36 : SYSCTL_RCC2_SYSDIV2_55

System clock /55

0x37 : SYSCTL_RCC2_SYSDIV2_56

System clock /56

0x38 : SYSCTL_RCC2_SYSDIV2_57

System clock /57

0x39 : SYSCTL_RCC2_SYSDIV2_58

System clock /58

0x3a : SYSCTL_RCC2_SYSDIV2_59

System clock /59

0x3b : SYSCTL_RCC2_SYSDIV2_60

System clock /60

0x3c : SYSCTL_RCC2_SYSDIV2_61

System clock /61

0x3d : SYSCTL_RCC2_SYSDIV2_62

System clock /62

0x3e : SYSCTL_RCC2_SYSDIV2_63

System clock /63

0x3f : SYSCTL_RCC2_SYSDIV2_64

System clock /64

End of enumeration elements list.

SYSCTL_RCC2_USERCC2 : Use RCC2
bits : 31 - 62 (32 bit)


RCC2

Run-Mode Clock Configuration 2
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCC2 RCC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_RCC2_OSCSRC2 SYSCTL_RCC2_BYPASS2 SYSCTL_RCC2_PWRDN2 SYSCTL_RCC2_SYSDIV2 SYSCTL_RCC2_USERCC2

SYSCTL_RCC2_OSCSRC2 : Oscillator Source 2
bits : 4 - 10 (7 bit)

Enumeration:

0x0 : SYSCTL_RCC2_OSCSRC2_MO

MOSC

0x1 : SYSCTL_RCC2_OSCSRC2_IO

PIOSC

0x2 : SYSCTL_RCC2_OSCSRC2_IO4

PIOSC/4

0x3 : SYSCTL_RCC2_OSCSRC2_30

30 kHz

0x7 : SYSCTL_RCC2_OSCSRC2_32

32.768 kHz

End of enumeration elements list.

SYSCTL_RCC2_BYPASS2 : PLL Bypass 2
bits : 11 - 22 (12 bit)

SYSCTL_RCC2_PWRDN2 : Power-Down PLL 2
bits : 13 - 26 (14 bit)

SYSCTL_RCC2_SYSDIV2 : System Clock Divisor 2
bits : 23 - 51 (29 bit)

Enumeration:

0x1 : SYSCTL_RCC2_SYSDIV2_2

System clock /2

0x2 : SYSCTL_RCC2_SYSDIV2_3

System clock /3

0x3 : SYSCTL_RCC2_SYSDIV2_4

System clock /4

0x4 : SYSCTL_RCC2_SYSDIV2_5

System clock /5

0x5 : SYSCTL_RCC2_SYSDIV2_6

System clock /6

0x6 : SYSCTL_RCC2_SYSDIV2_7

System clock /7

0x7 : SYSCTL_RCC2_SYSDIV2_8

System clock /8

0x8 : SYSCTL_RCC2_SYSDIV2_9

System clock /9

0x9 : SYSCTL_RCC2_SYSDIV2_10

System clock /10

0xa : SYSCTL_RCC2_SYSDIV2_11

System clock /11

0xb : SYSCTL_RCC2_SYSDIV2_12

System clock /12

0xc : SYSCTL_RCC2_SYSDIV2_13

System clock /13

0xd : SYSCTL_RCC2_SYSDIV2_14

System clock /14

0xe : SYSCTL_RCC2_SYSDIV2_15

System clock /15

0xf : SYSCTL_RCC2_SYSDIV2_16

System clock /16

0x10 : SYSCTL_RCC2_SYSDIV2_17

System clock /17

0x11 : SYSCTL_RCC2_SYSDIV2_18

System clock /18

0x12 : SYSCTL_RCC2_SYSDIV2_19

System clock /19

0x13 : SYSCTL_RCC2_SYSDIV2_20

System clock /20

0x14 : SYSCTL_RCC2_SYSDIV2_21

System clock /21

0x15 : SYSCTL_RCC2_SYSDIV2_22

System clock /22

0x16 : SYSCTL_RCC2_SYSDIV2_23

System clock /23

0x17 : SYSCTL_RCC2_SYSDIV2_24

System clock /24

0x18 : SYSCTL_RCC2_SYSDIV2_25

System clock /25

0x19 : SYSCTL_RCC2_SYSDIV2_26

System clock /26

0x1a : SYSCTL_RCC2_SYSDIV2_27

System clock /27

0x1b : SYSCTL_RCC2_SYSDIV2_28

System clock /28

0x1c : SYSCTL_RCC2_SYSDIV2_29

System clock /29

0x1d : SYSCTL_RCC2_SYSDIV2_30

System clock /30

0x1e : SYSCTL_RCC2_SYSDIV2_31

System clock /31

0x1f : SYSCTL_RCC2_SYSDIV2_32

System clock /32

0x20 : SYSCTL_RCC2_SYSDIV2_33

System clock /33

0x21 : SYSCTL_RCC2_SYSDIV2_34

System clock /34

0x22 : SYSCTL_RCC2_SYSDIV2_35

System clock /35

0x23 : SYSCTL_RCC2_SYSDIV2_36

System clock /36

0x24 : SYSCTL_RCC2_SYSDIV2_37

System clock /37

0x25 : SYSCTL_RCC2_SYSDIV2_38

System clock /38

0x26 : SYSCTL_RCC2_SYSDIV2_39

System clock /39

0x27 : SYSCTL_RCC2_SYSDIV2_40

System clock /40

0x28 : SYSCTL_RCC2_SYSDIV2_41

System clock /41

0x29 : SYSCTL_RCC2_SYSDIV2_42

System clock /42

0x2a : SYSCTL_RCC2_SYSDIV2_43

System clock /43

0x2b : SYSCTL_RCC2_SYSDIV2_44

System clock /44

0x2c : SYSCTL_RCC2_SYSDIV2_45

System clock /45

0x2d : SYSCTL_RCC2_SYSDIV2_46

System clock /46

0x2e : SYSCTL_RCC2_SYSDIV2_47

System clock /47

0x2f : SYSCTL_RCC2_SYSDIV2_48

System clock /48

0x30 : SYSCTL_RCC2_SYSDIV2_49

System clock /49

0x31 : SYSCTL_RCC2_SYSDIV2_50

System clock /50

0x32 : SYSCTL_RCC2_SYSDIV2_51

System clock /51

0x33 : SYSCTL_RCC2_SYSDIV2_52

System clock /52

0x34 : SYSCTL_RCC2_SYSDIV2_53

System clock /53

0x35 : SYSCTL_RCC2_SYSDIV2_54

System clock /54

0x36 : SYSCTL_RCC2_SYSDIV2_55

System clock /55

0x37 : SYSCTL_RCC2_SYSDIV2_56

System clock /56

0x38 : SYSCTL_RCC2_SYSDIV2_57

System clock /57

0x39 : SYSCTL_RCC2_SYSDIV2_58

System clock /58

0x3a : SYSCTL_RCC2_SYSDIV2_59

System clock /59

0x3b : SYSCTL_RCC2_SYSDIV2_60

System clock /60

0x3c : SYSCTL_RCC2_SYSDIV2_61

System clock /61

0x3d : SYSCTL_RCC2_SYSDIV2_62

System clock /62

0x3e : SYSCTL_RCC2_SYSDIV2_63

System clock /63

0x3f : SYSCTL_RCC2_SYSDIV2_64

System clock /64

End of enumeration elements list.

SYSCTL_RCC2_USERCC2 : Use RCC2
bits : 31 - 62 (32 bit)


SYSCTLMOSCCTL

Main Oscillator Control
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLMOSCCTL SYSCTLMOSCCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_MOSCCTL_CVAL

SYSCTL_MOSCCTL_CVAL : Clock Validation for MOSC
bits : 0 - 0 (1 bit)


MOSCCTL

Main Oscillator Control
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOSCCTL MOSCCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_MOSCCTL_CVAL

SYSCTL_MOSCCTL_CVAL : Clock Validation for MOSC
bits : 0 - 0 (1 bit)


SYSCTLDC0

Device Capabilities 0
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCTLDC0 SYSCTLDC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DC0_FLASHSZ SYSCTL_DC0_SRAMSZ

SYSCTL_DC0_FLASHSZ : Flash Size
bits : 0 - 15 (16 bit)

Enumeration:

0x1f : SYSCTL_DC0_FLASHSZ_64KB

64 KB of Flash

End of enumeration elements list.

SYSCTL_DC0_SRAMSZ : SRAM Size
bits : 16 - 47 (32 bit)

Enumeration:

0x7f : SYSCTL_DC0_SRAMSZ_32KB

32 KB of SRAM

End of enumeration elements list.


DC0

Device Capabilities 0
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DC0 DC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCTL_DC0_FLASHSZ SYSCTL_DC0_SRAMSZ

SYSCTL_DC0_FLASHSZ : Flash Size
bits : 0 - 15 (16 bit)

Enumeration:

0x1f : SYSCTL_DC0_FLASHSZ_64KB

64 KB of Flash

End of enumeration elements list.

SYSCTL_DC0_SRAMSZ : SRAM Size
bits : 16 - 47 (32 bit)

Enumeration:

0x7f : SYSCTL_DC0_SRAMSZ_32KB

32 KB of SRAM

End of enumeration elements list.



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