Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Device Identification 0
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DID0_MIN : Minor Revision
bits : 0 - 7 (8 bit)
Enumeration:
0x0 : SYSCTL_DID0_MIN_0
Initial device, or a major revision update
0x1 : SYSCTL_DID0_MIN_1
First metal layer change
0x2 : SYSCTL_DID0_MIN_2
Second metal layer change
End of enumeration elements list.
SYSCTL_DID0_MAJ : Major Revision
bits : 8 - 23 (16 bit)
Enumeration:
0x0 : SYSCTL_DID0_MAJ_REVA
Revision A (initial device)
0x1 : SYSCTL_DID0_MAJ_REVB
Revision B (first base layer revision)
0x2 : SYSCTL_DID0_MAJ_REVC
Revision C (second base layer revision)
End of enumeration elements list.
SYSCTL_DID0_VER : DID0 Version
bits : 28 - 58 (31 bit)
Enumeration:
0x0 : SYSCTL_DID0_VER_0
Initial DID0 register format definition for Stellaris(R) Sandstorm-class devices
End of enumeration elements list.
Device Identification 0
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DID0_MIN : Minor Revision
bits : 0 - 7 (8 bit)
Enumeration:
0x0 : SYSCTL_DID0_MIN_0
Initial device, or a major revision update
0x1 : SYSCTL_DID0_MIN_1
First metal layer change
0x2 : SYSCTL_DID0_MIN_2
Second metal layer change
End of enumeration elements list.
SYSCTL_DID0_MAJ : Major Revision
bits : 8 - 23 (16 bit)
Enumeration:
0x0 : SYSCTL_DID0_MAJ_REVA
Revision A (initial device)
0x1 : SYSCTL_DID0_MAJ_REVB
Revision B (first base layer revision)
0x2 : SYSCTL_DID0_MAJ_REVC
Revision C (second base layer revision)
End of enumeration elements list.
SYSCTL_DID0_VER : DID0 Version
bits : 28 - 58 (31 bit)
Enumeration:
0x0 : SYSCTL_DID0_VER_0
Initial DID0 register format definition for Stellaris(R) Sandstorm-class devices
End of enumeration elements list.
Device Capabilities 1
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC1_JTAG : JTAG Present
bits : 0 - 0 (1 bit)
SYSCTL_DC1_SWD : SWD Present
bits : 1 - 2 (2 bit)
SYSCTL_DC1_SWO : SWO Trace Port Present
bits : 2 - 4 (3 bit)
SYSCTL_DC1_WDT0 : Watchdog Timer 0 Present
bits : 3 - 6 (4 bit)
SYSCTL_DC1_PLL : PLL Present
bits : 4 - 8 (5 bit)
SYSCTL_DC1_MPU : MPU Present
bits : 7 - 14 (8 bit)
SYSCTL_DC1_MINSYSDIV : System Clock Divider
bits : 12 - 27 (16 bit)
Enumeration:
0x7 : SYSCTL_DC1_MINSYSDIV_25
Specifies a 25-MHz clock with a PLL divider of 8
End of enumeration elements list.
Device Capabilities 1
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC1_JTAG : JTAG Present
bits : 0 - 0 (1 bit)
SYSCTL_DC1_SWD : SWD Present
bits : 1 - 2 (2 bit)
SYSCTL_DC1_SWO : SWO Trace Port Present
bits : 2 - 4 (3 bit)
SYSCTL_DC1_WDT0 : Watchdog Timer 0 Present
bits : 3 - 6 (4 bit)
SYSCTL_DC1_PLL : PLL Present
bits : 4 - 8 (5 bit)
SYSCTL_DC1_MPU : MPU Present
bits : 7 - 14 (8 bit)
SYSCTL_DC1_MINSYSDIV : System Clock Divider
bits : 12 - 27 (16 bit)
Enumeration:
0x7 : SYSCTL_DC1_MINSYSDIV_25
Specifies a 25-MHz clock with a PLL divider of 8
End of enumeration elements list.
Run Mode Clock Gating Control Register 0
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Run Mode Clock Gating Control Register 0
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Run Mode Clock Gating Control Register 1
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGC1_UART0 : UART0 Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGC1_UART1 : UART1 Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_RCGC1_SSI0 : SSI0 Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_RCGC1_TIMER0 : Timer 0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_RCGC1_TIMER1 : Timer 1 Clock Gating Control
bits : 17 - 34 (18 bit)
SYSCTL_RCGC1_TIMER2 : Timer 2 Clock Gating Control
bits : 18 - 36 (19 bit)
SYSCTL_RCGC1_COMP0 : Analog Comparator 0 Clock Gating
bits : 24 - 48 (25 bit)
SYSCTL_RCGC1_COMP1 : Analog Comparator 1 Clock Gating
bits : 25 - 50 (26 bit)
SYSCTL_RCGC1_COMP2 : Analog Comparator 2 Clock Gating
bits : 26 - 52 (27 bit)
Run Mode Clock Gating Control Register 1
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGC1_UART0 : UART0 Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGC1_UART1 : UART1 Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_RCGC1_SSI0 : SSI0 Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_RCGC1_TIMER0 : Timer 0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_RCGC1_TIMER1 : Timer 1 Clock Gating Control
bits : 17 - 34 (18 bit)
SYSCTL_RCGC1_TIMER2 : Timer 2 Clock Gating Control
bits : 18 - 36 (19 bit)
SYSCTL_RCGC1_COMP0 : Analog Comparator 0 Clock Gating
bits : 24 - 48 (25 bit)
SYSCTL_RCGC1_COMP1 : Analog Comparator 1 Clock Gating
bits : 25 - 50 (26 bit)
SYSCTL_RCGC1_COMP2 : Analog Comparator 2 Clock Gating
bits : 26 - 52 (27 bit)
Run Mode Clock Gating Control Register 2
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGC2_GPIOA : Port A Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGC2_GPIOB : Port B Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_RCGC2_GPIOC : Port C Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_RCGC2_GPIOD : Port D Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_RCGC2_GPIOE : Port E Clock Gating Control
bits : 4 - 8 (5 bit)
Run Mode Clock Gating Control Register 2
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGC2_GPIOA : Port A Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGC2_GPIOB : Port B Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_RCGC2_GPIOC : Port C Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_RCGC2_GPIOD : Port D Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_RCGC2_GPIOE : Port E Clock Gating Control
bits : 4 - 8 (5 bit)
Sleep Mode Clock Gating Control Register 0
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Sleep Mode Clock Gating Control Register 0
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Sleep Mode Clock Gating Control Register 1
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGC1_UART0 : UART0 Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGC1_UART1 : UART1 Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_SCGC1_SSI0 : SSI0 Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_SCGC1_TIMER0 : Timer 0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_SCGC1_TIMER1 : Timer 1 Clock Gating Control
bits : 17 - 34 (18 bit)
SYSCTL_SCGC1_TIMER2 : Timer 2 Clock Gating Control
bits : 18 - 36 (19 bit)
SYSCTL_SCGC1_COMP0 : Analog Comparator 0 Clock Gating
bits : 24 - 48 (25 bit)
SYSCTL_SCGC1_COMP1 : Analog Comparator 1 Clock Gating
bits : 25 - 50 (26 bit)
SYSCTL_SCGC1_COMP2 : Analog Comparator 2 Clock Gating
bits : 26 - 52 (27 bit)
Sleep Mode Clock Gating Control Register 1
address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGC1_UART0 : UART0 Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGC1_UART1 : UART1 Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_SCGC1_SSI0 : SSI0 Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_SCGC1_TIMER0 : Timer 0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_SCGC1_TIMER1 : Timer 1 Clock Gating Control
bits : 17 - 34 (18 bit)
SYSCTL_SCGC1_TIMER2 : Timer 2 Clock Gating Control
bits : 18 - 36 (19 bit)
SYSCTL_SCGC1_COMP0 : Analog Comparator 0 Clock Gating
bits : 24 - 48 (25 bit)
SYSCTL_SCGC1_COMP1 : Analog Comparator 1 Clock Gating
bits : 25 - 50 (26 bit)
SYSCTL_SCGC1_COMP2 : Analog Comparator 2 Clock Gating
bits : 26 - 52 (27 bit)
Sleep Mode Clock Gating Control Register 2
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGC2_GPIOA : Port A Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGC2_GPIOB : Port B Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_SCGC2_GPIOC : Port C Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_SCGC2_GPIOD : Port D Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_SCGC2_GPIOE : Port E Clock Gating Control
bits : 4 - 8 (5 bit)
Sleep Mode Clock Gating Control Register 2
address_offset : 0x118 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGC2_GPIOA : Port A Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGC2_GPIOB : Port B Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_SCGC2_GPIOC : Port C Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_SCGC2_GPIOD : Port D Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_SCGC2_GPIOE : Port E Clock Gating Control
bits : 4 - 8 (5 bit)
Deep Sleep Mode Clock Gating Control Register 0
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Deep Sleep Mode Clock Gating Control Register 0
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Deep-Sleep Mode Clock Gating Control Register 1
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGC1_UART0 : UART0 Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGC1_UART1 : UART1 Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_DCGC1_SSI0 : SSI0 Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_DCGC1_TIMER0 : Timer 0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_DCGC1_TIMER1 : Timer 1 Clock Gating Control
bits : 17 - 34 (18 bit)
SYSCTL_DCGC1_TIMER2 : Timer 2 Clock Gating Control
bits : 18 - 36 (19 bit)
SYSCTL_DCGC1_COMP0 : Analog Comparator 0 Clock Gating
bits : 24 - 48 (25 bit)
SYSCTL_DCGC1_COMP1 : Analog Comparator 1 Clock Gating
bits : 25 - 50 (26 bit)
SYSCTL_DCGC1_COMP2 : Analog Comparator 2 Clock Gating
bits : 26 - 52 (27 bit)
Deep-Sleep Mode Clock Gating Control Register 1
address_offset : 0x124 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGC1_UART0 : UART0 Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGC1_UART1 : UART1 Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_DCGC1_SSI0 : SSI0 Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_DCGC1_TIMER0 : Timer 0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_DCGC1_TIMER1 : Timer 1 Clock Gating Control
bits : 17 - 34 (18 bit)
SYSCTL_DCGC1_TIMER2 : Timer 2 Clock Gating Control
bits : 18 - 36 (19 bit)
SYSCTL_DCGC1_COMP0 : Analog Comparator 0 Clock Gating
bits : 24 - 48 (25 bit)
SYSCTL_DCGC1_COMP1 : Analog Comparator 1 Clock Gating
bits : 25 - 50 (26 bit)
SYSCTL_DCGC1_COMP2 : Analog Comparator 2 Clock Gating
bits : 26 - 52 (27 bit)
Deep Sleep Mode Clock Gating Control Register 2
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGC2_GPIOA : Port A Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGC2_GPIOB : Port B Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_DCGC2_GPIOC : Port C Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_DCGC2_GPIOD : Port D Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_DCGC2_GPIOE : Port E Clock Gating Control
bits : 4 - 8 (5 bit)
Deep Sleep Mode Clock Gating Control Register 2
address_offset : 0x128 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGC2_GPIOA : Port A Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGC2_GPIOB : Port B Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_DCGC2_GPIOC : Port C Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_DCGC2_GPIOD : Port D Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_DCGC2_GPIOE : Port E Clock Gating Control
bits : 4 - 8 (5 bit)
Device Capabilities 2
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC2_UART0 : UART Module 0 Present
bits : 0 - 0 (1 bit)
SYSCTL_DC2_UART1 : UART Module 1 Present
bits : 1 - 2 (2 bit)
SYSCTL_DC2_SSI0 : SSI Module 0 Present
bits : 4 - 8 (5 bit)
SYSCTL_DC2_TIMER0 : Timer Module 0 Present
bits : 16 - 32 (17 bit)
SYSCTL_DC2_TIMER1 : Timer Module 1 Present
bits : 17 - 34 (18 bit)
SYSCTL_DC2_TIMER2 : Timer Module 2 Present
bits : 18 - 36 (19 bit)
SYSCTL_DC2_COMP0 : Analog Comparator 0 Present
bits : 24 - 48 (25 bit)
SYSCTL_DC2_COMP1 : Analog Comparator 1 Present
bits : 25 - 50 (26 bit)
SYSCTL_DC2_COMP2 : Analog Comparator 2 Present
bits : 26 - 52 (27 bit)
Device Capabilities 2
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC2_UART0 : UART Module 0 Present
bits : 0 - 0 (1 bit)
SYSCTL_DC2_UART1 : UART Module 1 Present
bits : 1 - 2 (2 bit)
SYSCTL_DC2_SSI0 : SSI Module 0 Present
bits : 4 - 8 (5 bit)
SYSCTL_DC2_TIMER0 : Timer Module 0 Present
bits : 16 - 32 (17 bit)
SYSCTL_DC2_TIMER1 : Timer Module 1 Present
bits : 17 - 34 (18 bit)
SYSCTL_DC2_TIMER2 : Timer Module 2 Present
bits : 18 - 36 (19 bit)
SYSCTL_DC2_COMP0 : Analog Comparator 0 Present
bits : 24 - 48 (25 bit)
SYSCTL_DC2_COMP1 : Analog Comparator 1 Present
bits : 25 - 50 (26 bit)
SYSCTL_DC2_COMP2 : Analog Comparator 2 Present
bits : 26 - 52 (27 bit)
Deep Sleep Clock Configuration
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DSLPCLKCFG_IOSC : IOSC Clock Source
bits : 0 - 0 (1 bit)
Deep Sleep Clock Configuration
address_offset : 0x144 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DSLPCLKCFG_IOSC : IOSC Clock Source
bits : 0 - 0 (1 bit)
Clock Verification Clear
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_CLKVCLR_VERCLR : Clock Verification Clear
bits : 0 - 0 (1 bit)
Clock Verification Clear
address_offset : 0x150 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_CLKVCLR_VERCLR : Clock Verification Clear
bits : 0 - 0 (1 bit)
Allow Unregulated LDO to Reset the Part
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_LDOARST_LDOARST : LDO Reset
bits : 0 - 0 (1 bit)
Allow Unregulated LDO to Reset the Part
address_offset : 0x160 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_LDOARST_LDOARST : LDO Reset
bits : 0 - 0 (1 bit)
Device Capabilities 3
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC3_PWM0 : PWM0 Pin Present
bits : 0 - 0 (1 bit)
SYSCTL_DC3_PWM1 : PWM1 Pin Present
bits : 1 - 2 (2 bit)
SYSCTL_DC3_PWM2 : PWM2 Pin Present
bits : 2 - 4 (3 bit)
SYSCTL_DC3_PWM3 : PWM3 Pin Present
bits : 3 - 6 (4 bit)
SYSCTL_DC3_PWM4 : PWM4 Pin Present
bits : 4 - 8 (5 bit)
SYSCTL_DC3_PWM5 : PWM5 Pin Present
bits : 5 - 10 (6 bit)
SYSCTL_DC3_C0MINUS : C0- Pin Present
bits : 6 - 12 (7 bit)
SYSCTL_DC3_C0PLUS : C0+ Pin Present
bits : 7 - 14 (8 bit)
SYSCTL_DC3_C0O : C0o Pin Present
bits : 8 - 16 (9 bit)
SYSCTL_DC3_C1MINUS : C1- Pin Present
bits : 9 - 18 (10 bit)
SYSCTL_DC3_C1PLUS : C1+ Pin Present
bits : 10 - 20 (11 bit)
SYSCTL_DC3_C1O : C1o Pin Present
bits : 11 - 22 (12 bit)
SYSCTL_DC3_C2MINUS : C2- Pin Present
bits : 12 - 24 (13 bit)
SYSCTL_DC3_C2PLUS : C2+ Pin Present
bits : 13 - 26 (14 bit)
SYSCTL_DC3_C2O : C2o Pin Present
bits : 14 - 28 (15 bit)
SYSCTL_DC3_CCP0 : CCP0 Pin Present
bits : 24 - 48 (25 bit)
SYSCTL_DC3_CCP1 : CCP1 Pin Present
bits : 25 - 50 (26 bit)
SYSCTL_DC3_CCP2 : CCP2 Pin Present
bits : 26 - 52 (27 bit)
SYSCTL_DC3_CCP3 : CCP3 Pin Present
bits : 27 - 54 (28 bit)
SYSCTL_DC3_CCP4 : CCP4 Pin Present
bits : 28 - 56 (29 bit)
SYSCTL_DC3_CCP5 : CCP5 Pin Present
bits : 29 - 58 (30 bit)
SYSCTL_DC3_32KHZ : 32KHz Input Clock Available
bits : 31 - 62 (32 bit)
Device Capabilities 3
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC3_PWM0 : PWM0 Pin Present
bits : 0 - 0 (1 bit)
SYSCTL_DC3_PWM1 : PWM1 Pin Present
bits : 1 - 2 (2 bit)
SYSCTL_DC3_PWM2 : PWM2 Pin Present
bits : 2 - 4 (3 bit)
SYSCTL_DC3_PWM3 : PWM3 Pin Present
bits : 3 - 6 (4 bit)
SYSCTL_DC3_PWM4 : PWM4 Pin Present
bits : 4 - 8 (5 bit)
SYSCTL_DC3_PWM5 : PWM5 Pin Present
bits : 5 - 10 (6 bit)
SYSCTL_DC3_C0MINUS : C0- Pin Present
bits : 6 - 12 (7 bit)
SYSCTL_DC3_C0PLUS : C0+ Pin Present
bits : 7 - 14 (8 bit)
SYSCTL_DC3_C0O : C0o Pin Present
bits : 8 - 16 (9 bit)
SYSCTL_DC3_C1MINUS : C1- Pin Present
bits : 9 - 18 (10 bit)
SYSCTL_DC3_C1PLUS : C1+ Pin Present
bits : 10 - 20 (11 bit)
SYSCTL_DC3_C1O : C1o Pin Present
bits : 11 - 22 (12 bit)
SYSCTL_DC3_C2MINUS : C2- Pin Present
bits : 12 - 24 (13 bit)
SYSCTL_DC3_C2PLUS : C2+ Pin Present
bits : 13 - 26 (14 bit)
SYSCTL_DC3_C2O : C2o Pin Present
bits : 14 - 28 (15 bit)
SYSCTL_DC3_CCP0 : CCP0 Pin Present
bits : 24 - 48 (25 bit)
SYSCTL_DC3_CCP1 : CCP1 Pin Present
bits : 25 - 50 (26 bit)
SYSCTL_DC3_CCP2 : CCP2 Pin Present
bits : 26 - 52 (27 bit)
SYSCTL_DC3_CCP3 : CCP3 Pin Present
bits : 27 - 54 (28 bit)
SYSCTL_DC3_CCP4 : CCP4 Pin Present
bits : 28 - 56 (29 bit)
SYSCTL_DC3_CCP5 : CCP5 Pin Present
bits : 29 - 58 (30 bit)
SYSCTL_DC3_32KHZ : 32KHz Input Clock Available
bits : 31 - 62 (32 bit)
Device Capabilities 4
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC4_GPIOA : GPIO Port A Present
bits : 0 - 0 (1 bit)
SYSCTL_DC4_GPIOB : GPIO Port B Present
bits : 1 - 2 (2 bit)
SYSCTL_DC4_GPIOC : GPIO Port C Present
bits : 2 - 4 (3 bit)
SYSCTL_DC4_GPIOD : GPIO Port D Present
bits : 3 - 6 (4 bit)
SYSCTL_DC4_GPIOE : GPIO Port E Present
bits : 4 - 8 (5 bit)
Device Capabilities 4
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC4_GPIOA : GPIO Port A Present
bits : 0 - 0 (1 bit)
SYSCTL_DC4_GPIOB : GPIO Port B Present
bits : 1 - 2 (2 bit)
SYSCTL_DC4_GPIOC : GPIO Port C Present
bits : 2 - 4 (3 bit)
SYSCTL_DC4_GPIOD : GPIO Port D Present
bits : 3 - 6 (4 bit)
SYSCTL_DC4_GPIOE : GPIO Port E Present
bits : 4 - 8 (5 bit)
Brown-Out Reset Control
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PBORCTL_BORWT : BOR Wait and Check for Noise
bits : 0 - 0 (1 bit)
SYSCTL_PBORCTL_BORIOR : BOR Interrupt or Reset
bits : 1 - 2 (2 bit)
SYSCTL_PBORCTL_BORTIM : BOR Time Delay
bits : 2 - 17 (16 bit)
Brown-Out Reset Control
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PBORCTL_BORWT : BOR Wait and Check for Noise
bits : 0 - 0 (1 bit)
SYSCTL_PBORCTL_BORIOR : BOR Interrupt or Reset
bits : 1 - 2 (2 bit)
SYSCTL_PBORCTL_BORTIM : BOR Time Delay
bits : 2 - 17 (16 bit)
LDO Power Control
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_LDOPCTL : LDO Output Voltage
bits : 0 - 5 (6 bit)
Enumeration:
0x0 : SYSCTL_LDOPCTL_2_50V
2.50
0x1 : SYSCTL_LDOPCTL_2_45V
2.45
0x2 : SYSCTL_LDOPCTL_2_40V
2.40
0x3 : SYSCTL_LDOPCTL_2_35V
2.35
0x4 : SYSCTL_LDOPCTL_2_30V
2.30
0x5 : SYSCTL_LDOPCTL_2_25V
2.25
0x1b : SYSCTL_LDOPCTL_2_75V
2.75
0x1c : SYSCTL_LDOPCTL_2_70V
2.70
0x1d : SYSCTL_LDOPCTL_2_65V
2.65
0x1e : SYSCTL_LDOPCTL_2_60V
2.60
0x1f : SYSCTL_LDOPCTL_2_55V
2.55
End of enumeration elements list.
LDO Power Control
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_LDOPCTL : LDO Output Voltage
bits : 0 - 5 (6 bit)
Enumeration:
0x0 : SYSCTL_LDOPCTL_2_50V
2.50
0x1 : SYSCTL_LDOPCTL_2_45V
2.45
0x2 : SYSCTL_LDOPCTL_2_40V
2.40
0x3 : SYSCTL_LDOPCTL_2_35V
2.35
0x4 : SYSCTL_LDOPCTL_2_30V
2.30
0x5 : SYSCTL_LDOPCTL_2_25V
2.25
0x1b : SYSCTL_LDOPCTL_2_75V
2.75
0x1c : SYSCTL_LDOPCTL_2_70V
2.70
0x1d : SYSCTL_LDOPCTL_2_65V
2.65
0x1e : SYSCTL_LDOPCTL_2_60V
2.60
0x1f : SYSCTL_LDOPCTL_2_55V
2.55
End of enumeration elements list.
Device Identification 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DID1_QUAL : Qualification Status
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : SYSCTL_DID1_QUAL_ES
Engineering Sample (unqualified)
0x1 : SYSCTL_DID1_QUAL_PP
Pilot Production (unqualified)
0x2 : SYSCTL_DID1_QUAL_FQ
Fully Qualified
End of enumeration elements list.
SYSCTL_DID1_ROHS : RoHS-Compliance
bits : 2 - 4 (3 bit)
SYSCTL_DID1_PKG : Package Type
bits : 3 - 7 (5 bit)
Enumeration:
0x0 : SYSCTL_DID1_PKG_SOIC
SOIC package
0x1 : SYSCTL_DID1_PKG_QFP
LQFP package
0x3 : SYSCTL_DID1_PKG_QFN
QFN package
End of enumeration elements list.
SYSCTL_DID1_TEMP : Temperature Range
bits : 5 - 12 (8 bit)
Enumeration:
0x0 : SYSCTL_DID1_TEMP_C
Commercial temperature range (0C to 70C)
0x1 : SYSCTL_DID1_TEMP_I
Industrial temperature range (-40C to 85C)
0x2 : SYSCTL_DID1_TEMP_E
Extended temperature range (-40C to 105C)
End of enumeration elements list.
SYSCTL_DID1_PRTNO : Part Number
bits : 16 - 39 (24 bit)
Enumeration:
0x12 : SYSCTL_DID1_PRTNO_310
LM3S310
End of enumeration elements list.
SYSCTL_DID1_FAM : Family
bits : 24 - 51 (28 bit)
Enumeration:
0x0 : SYSCTL_DID1_FAM_STELLARIS
Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S
End of enumeration elements list.
SYSCTL_DID1_VER : DID1 Version
bits : 28 - 59 (32 bit)
Enumeration:
0x0 : SYSCTL_DID1_VER_0
Initial DID1 register format definition, indicating a Stellaris LM3Snnn device
End of enumeration elements list.
Device Identification 1
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DID1_QUAL : Qualification Status
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : SYSCTL_DID1_QUAL_ES
Engineering Sample (unqualified)
0x1 : SYSCTL_DID1_QUAL_PP
Pilot Production (unqualified)
0x2 : SYSCTL_DID1_QUAL_FQ
Fully Qualified
End of enumeration elements list.
SYSCTL_DID1_ROHS : RoHS-Compliance
bits : 2 - 4 (3 bit)
SYSCTL_DID1_PKG : Package Type
bits : 3 - 7 (5 bit)
Enumeration:
0x0 : SYSCTL_DID1_PKG_SOIC
SOIC package
0x1 : SYSCTL_DID1_PKG_QFP
LQFP package
0x3 : SYSCTL_DID1_PKG_QFN
QFN package
End of enumeration elements list.
SYSCTL_DID1_TEMP : Temperature Range
bits : 5 - 12 (8 bit)
Enumeration:
0x0 : SYSCTL_DID1_TEMP_C
Commercial temperature range (0C to 70C)
0x1 : SYSCTL_DID1_TEMP_I
Industrial temperature range (-40C to 85C)
0x2 : SYSCTL_DID1_TEMP_E
Extended temperature range (-40C to 105C)
End of enumeration elements list.
SYSCTL_DID1_PRTNO : Part Number
bits : 16 - 39 (24 bit)
Enumeration:
0x12 : SYSCTL_DID1_PRTNO_310
LM3S310
End of enumeration elements list.
SYSCTL_DID1_FAM : Family
bits : 24 - 51 (28 bit)
Enumeration:
0x0 : SYSCTL_DID1_FAM_STELLARIS
Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S
End of enumeration elements list.
SYSCTL_DID1_VER : DID1 Version
bits : 28 - 59 (32 bit)
Enumeration:
0x0 : SYSCTL_DID1_VER_0
Initial DID1 register format definition, indicating a Stellaris LM3Snnn device
End of enumeration elements list.
Software Reset Control 0
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Software Reset Control 0
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Software Reset Control 1
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRCR1_UART0 : UART0 Reset Control
bits : 0 - 0 (1 bit)
SYSCTL_SRCR1_UART1 : UART1 Reset Control
bits : 1 - 2 (2 bit)
SYSCTL_SRCR1_SSI0 : SSI0 Reset Control
bits : 4 - 8 (5 bit)
SYSCTL_SRCR1_TIMER0 : Timer 0 Reset Control
bits : 16 - 32 (17 bit)
SYSCTL_SRCR1_TIMER1 : Timer 1 Reset Control
bits : 17 - 34 (18 bit)
SYSCTL_SRCR1_TIMER2 : Timer 2 Reset Control
bits : 18 - 36 (19 bit)
SYSCTL_SRCR1_COMP0 : Analog Comp 0 Reset Control
bits : 24 - 48 (25 bit)
SYSCTL_SRCR1_COMP1 : Analog Comp 1 Reset Control
bits : 25 - 50 (26 bit)
SYSCTL_SRCR1_COMP2 : Analog Comp 2 Reset Control
bits : 26 - 52 (27 bit)
Software Reset Control 1
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRCR1_UART0 : UART0 Reset Control
bits : 0 - 0 (1 bit)
SYSCTL_SRCR1_UART1 : UART1 Reset Control
bits : 1 - 2 (2 bit)
SYSCTL_SRCR1_SSI0 : SSI0 Reset Control
bits : 4 - 8 (5 bit)
SYSCTL_SRCR1_TIMER0 : Timer 0 Reset Control
bits : 16 - 32 (17 bit)
SYSCTL_SRCR1_TIMER1 : Timer 1 Reset Control
bits : 17 - 34 (18 bit)
SYSCTL_SRCR1_TIMER2 : Timer 2 Reset Control
bits : 18 - 36 (19 bit)
SYSCTL_SRCR1_COMP0 : Analog Comp 0 Reset Control
bits : 24 - 48 (25 bit)
SYSCTL_SRCR1_COMP1 : Analog Comp 1 Reset Control
bits : 25 - 50 (26 bit)
SYSCTL_SRCR1_COMP2 : Analog Comp 2 Reset Control
bits : 26 - 52 (27 bit)
Software Reset Control 2
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRCR2_GPIOA : Port A Reset Control
bits : 0 - 0 (1 bit)
SYSCTL_SRCR2_GPIOB : Port B Reset Control
bits : 1 - 2 (2 bit)
SYSCTL_SRCR2_GPIOC : Port C Reset Control
bits : 2 - 4 (3 bit)
SYSCTL_SRCR2_GPIOD : Port D Reset Control
bits : 3 - 6 (4 bit)
SYSCTL_SRCR2_GPIOE : Port E Reset Control
bits : 4 - 8 (5 bit)
Software Reset Control 2
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRCR2_GPIOA : Port A Reset Control
bits : 0 - 0 (1 bit)
SYSCTL_SRCR2_GPIOB : Port B Reset Control
bits : 1 - 2 (2 bit)
SYSCTL_SRCR2_GPIOC : Port C Reset Control
bits : 2 - 4 (3 bit)
SYSCTL_SRCR2_GPIOD : Port D Reset Control
bits : 3 - 6 (4 bit)
SYSCTL_SRCR2_GPIOE : Port E Reset Control
bits : 4 - 8 (5 bit)
Raw Interrupt Status
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RIS_PLLFRIS : PLL Fault Raw Interrupt Status
bits : 0 - 0 (1 bit)
SYSCTL_RIS_BORRIS : Brown-Out Reset Raw Interrupt Status
bits : 1 - 2 (2 bit)
SYSCTL_RIS_LDORIS : LDO Power Unregulated Raw Interrupt Status
bits : 2 - 4 (3 bit)
SYSCTL_RIS_MOFRIS : Main Oscillator Fault Raw Interrupt Status
bits : 3 - 6 (4 bit)
SYSCTL_RIS_IOFRIS : Internal Oscillator Fault Raw Interrupt Status
bits : 4 - 8 (5 bit)
SYSCTL_RIS_CLRIS : Current Limit Raw Interrupt Status
bits : 5 - 10 (6 bit)
SYSCTL_RIS_PLLLRIS : PLL Lock Raw Interrupt Status
bits : 6 - 12 (7 bit)
Raw Interrupt Status
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RIS_PLLFRIS : PLL Fault Raw Interrupt Status
bits : 0 - 0 (1 bit)
SYSCTL_RIS_BORRIS : Brown-Out Reset Raw Interrupt Status
bits : 1 - 2 (2 bit)
SYSCTL_RIS_LDORIS : LDO Power Unregulated Raw Interrupt Status
bits : 2 - 4 (3 bit)
SYSCTL_RIS_MOFRIS : Main Oscillator Fault Raw Interrupt Status
bits : 3 - 6 (4 bit)
SYSCTL_RIS_IOFRIS : Internal Oscillator Fault Raw Interrupt Status
bits : 4 - 8 (5 bit)
SYSCTL_RIS_CLRIS : Current Limit Raw Interrupt Status
bits : 5 - 10 (6 bit)
SYSCTL_RIS_PLLLRIS : PLL Lock Raw Interrupt Status
bits : 6 - 12 (7 bit)
Interrupt Mask Control
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_IMC_PLLFIM : PLL Fault Interrupt Mask
bits : 0 - 0 (1 bit)
SYSCTL_IMC_BORIM : Brown-Out Reset Interrupt Mask
bits : 1 - 2 (2 bit)
SYSCTL_IMC_LDOIM : LDO Power Unregulated Interrupt Mask
bits : 2 - 4 (3 bit)
SYSCTL_IMC_MOFIM : Main Oscillator Fault Interrupt Mask
bits : 3 - 6 (4 bit)
SYSCTL_IMC_IOFIM : Internal Oscillator Fault Interrupt Mask
bits : 4 - 8 (5 bit)
SYSCTL_IMC_CLIM : Current Limit Interrupt Mask
bits : 5 - 10 (6 bit)
SYSCTL_IMC_PLLLIM : PLL Lock Interrupt Mask
bits : 6 - 12 (7 bit)
Interrupt Mask Control
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_IMC_PLLFIM : PLL Fault Interrupt Mask
bits : 0 - 0 (1 bit)
SYSCTL_IMC_BORIM : Brown-Out Reset Interrupt Mask
bits : 1 - 2 (2 bit)
SYSCTL_IMC_LDOIM : LDO Power Unregulated Interrupt Mask
bits : 2 - 4 (3 bit)
SYSCTL_IMC_MOFIM : Main Oscillator Fault Interrupt Mask
bits : 3 - 6 (4 bit)
SYSCTL_IMC_IOFIM : Internal Oscillator Fault Interrupt Mask
bits : 4 - 8 (5 bit)
SYSCTL_IMC_CLIM : Current Limit Interrupt Mask
bits : 5 - 10 (6 bit)
SYSCTL_IMC_PLLLIM : PLL Lock Interrupt Mask
bits : 6 - 12 (7 bit)
Masked Interrupt Status and Clear
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_MISC_BORMIS : BOR Masked Interrupt Status
bits : 1 - 2 (2 bit)
SYSCTL_MISC_LDOMIS : LDO Power Unregulated Masked Interrupt Status
bits : 2 - 4 (3 bit)
SYSCTL_MISC_MOFMIS : Main Oscillator Fault Masked Interrupt Status
bits : 3 - 6 (4 bit)
SYSCTL_MISC_IOFMIS : Internal Oscillator Fault Masked Interrupt Status
bits : 4 - 8 (5 bit)
SYSCTL_MISC_CLMIS : Current Limit Masked Interrupt Status
bits : 5 - 10 (6 bit)
SYSCTL_MISC_PLLLMIS : PLL Lock Masked Interrupt Status
bits : 6 - 12 (7 bit)
Masked Interrupt Status and Clear
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_MISC_BORMIS : BOR Masked Interrupt Status
bits : 1 - 2 (2 bit)
SYSCTL_MISC_LDOMIS : LDO Power Unregulated Masked Interrupt Status
bits : 2 - 4 (3 bit)
SYSCTL_MISC_MOFMIS : Main Oscillator Fault Masked Interrupt Status
bits : 3 - 6 (4 bit)
SYSCTL_MISC_IOFMIS : Internal Oscillator Fault Masked Interrupt Status
bits : 4 - 8 (5 bit)
SYSCTL_MISC_CLMIS : Current Limit Masked Interrupt Status
bits : 5 - 10 (6 bit)
SYSCTL_MISC_PLLLMIS : PLL Lock Masked Interrupt Status
bits : 6 - 12 (7 bit)
Reset Cause
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RESC_EXT : External Reset
bits : 0 - 0 (1 bit)
SYSCTL_RESC_POR : Power-On Reset
bits : 1 - 2 (2 bit)
SYSCTL_RESC_BOR : Brown-Out Reset
bits : 2 - 4 (3 bit)
SYSCTL_RESC_SW : Software Reset
bits : 4 - 8 (5 bit)
SYSCTL_RESC_LDO : LDO Reset
bits : 5 - 10 (6 bit)
Reset Cause
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RESC_EXT : External Reset
bits : 0 - 0 (1 bit)
SYSCTL_RESC_POR : Power-On Reset
bits : 1 - 2 (2 bit)
SYSCTL_RESC_BOR : Brown-Out Reset
bits : 2 - 4 (3 bit)
SYSCTL_RESC_SW : Software Reset
bits : 4 - 8 (5 bit)
SYSCTL_RESC_LDO : LDO Reset
bits : 5 - 10 (6 bit)
Run-Mode Clock Configuration
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCC_MOSCDIS : Main Oscillator Disable
bits : 0 - 0 (1 bit)
SYSCTL_RCC_IOSCDIS : Internal Oscillator Disable
bits : 1 - 2 (2 bit)
SYSCTL_RCC_MOSCVER : Main Oscillator Verification Timer
bits : 2 - 4 (3 bit)
SYSCTL_RCC_IOSCVER : Internal Oscillator Verification Timer
bits : 3 - 6 (4 bit)
SYSCTL_RCC_OSCSRC : Oscillator Source
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : SYSCTL_RCC_OSCSRC_MAIN
MOSC
0x1 : SYSCTL_RCC_OSCSRC_INT
IOSC
0x2 : SYSCTL_RCC_OSCSRC_INT4
IOSC/4
End of enumeration elements list.
SYSCTL_RCC_XTAL : Crystal Value
bits : 6 - 15 (10 bit)
Enumeration:
0x0 : SYSCTL_RCC_XTAL_1MHZ
1 MHz
0x1 : SYSCTL_RCC_XTAL_1_84MHZ
1.8432 MHz
0x2 : SYSCTL_RCC_XTAL_2MHZ
2 MHz
0x3 : SYSCTL_RCC_XTAL_2_45MHZ
2.4576 MHz
0x4 : SYSCTL_RCC_XTAL_3_57MHZ
3.579545 MHz
0x5 : SYSCTL_RCC_XTAL_3_68MHZ
3.6864 MHz
0x6 : SYSCTL_RCC_XTAL_4MHZ
4 MHz
0x7 : SYSCTL_RCC_XTAL_4_09MHZ
4.096 MHz
0x8 : SYSCTL_RCC_XTAL_4_91MHZ
4.9152 MHz
0x9 : SYSCTL_RCC_XTAL_5MHZ
5 MHz
0xa : SYSCTL_RCC_XTAL_5_12MHZ
5.12 MHz
0xb : SYSCTL_RCC_XTAL_6MHZ
6 MHz
0xc : SYSCTL_RCC_XTAL_6_14MHZ
6.144 MHz
0xd : SYSCTL_RCC_XTAL_7_37MHZ
7.3728 MHz
0xe : SYSCTL_RCC_XTAL_8MHZ
8 MHz
0xf : SYSCTL_RCC_XTAL_8_19MHZ
8.192 MHz
End of enumeration elements list.
SYSCTL_RCC_PLLVER : PLL Verification
bits : 10 - 20 (11 bit)
SYSCTL_RCC_BYPASS : PLL Bypass
bits : 11 - 22 (12 bit)
SYSCTL_RCC_OEN : PLL Output Enable
bits : 12 - 24 (13 bit)
SYSCTL_RCC_PWRDN : PLL Power Down
bits : 13 - 26 (14 bit)
SYSCTL_RCC_PWMDIV : PWM Unit Clock Divisor
bits : 17 - 36 (20 bit)
Enumeration:
0x0 : SYSCTL_RCC_PWMDIV_2
PWM clock /2
0x1 : SYSCTL_RCC_PWMDIV_4
PWM clock /4
0x2 : SYSCTL_RCC_PWMDIV_8
PWM clock /8
0x3 : SYSCTL_RCC_PWMDIV_16
PWM clock /16
0x4 : SYSCTL_RCC_PWMDIV_32
PWM clock /32
0x5 : SYSCTL_RCC_PWMDIV_64
PWM clock /64
End of enumeration elements list.
SYSCTL_RCC_USEPWMDIV : Enable PWM Clock Divisor
bits : 20 - 40 (21 bit)
SYSCTL_RCC_USESYSDIV : Enable System Clock Divider
bits : 22 - 44 (23 bit)
SYSCTL_RCC_SYSDIV : System Clock Divisor
bits : 23 - 49 (27 bit)
Enumeration:
0x1 : SYSCTL_RCC_SYSDIV_2
System clock /2
0x2 : SYSCTL_RCC_SYSDIV_3
System clock /3
0x3 : SYSCTL_RCC_SYSDIV_4
System clock /4
0x4 : SYSCTL_RCC_SYSDIV_5
System clock /5
0x5 : SYSCTL_RCC_SYSDIV_6
System clock /6
0x6 : SYSCTL_RCC_SYSDIV_7
System clock /7
0x7 : SYSCTL_RCC_SYSDIV_8
System clock /8
0x8 : SYSCTL_RCC_SYSDIV_9
System clock /9
0x9 : SYSCTL_RCC_SYSDIV_10
System clock /10
0xa : SYSCTL_RCC_SYSDIV_11
System clock /11
0xb : SYSCTL_RCC_SYSDIV_12
System clock /12
0xc : SYSCTL_RCC_SYSDIV_13
System clock /13
0xd : SYSCTL_RCC_SYSDIV_14
System clock /14
0xe : SYSCTL_RCC_SYSDIV_15
System clock /15
0xf : SYSCTL_RCC_SYSDIV_16
System clock /16
End of enumeration elements list.
SYSCTL_RCC_ACG : Auto Clock Gating
bits : 27 - 54 (28 bit)
Run-Mode Clock Configuration
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCC_MOSCDIS : Main Oscillator Disable
bits : 0 - 0 (1 bit)
SYSCTL_RCC_IOSCDIS : Internal Oscillator Disable
bits : 1 - 2 (2 bit)
SYSCTL_RCC_MOSCVER : Main Oscillator Verification Timer
bits : 2 - 4 (3 bit)
SYSCTL_RCC_IOSCVER : Internal Oscillator Verification Timer
bits : 3 - 6 (4 bit)
SYSCTL_RCC_OSCSRC : Oscillator Source
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : SYSCTL_RCC_OSCSRC_MAIN
MOSC
0x1 : SYSCTL_RCC_OSCSRC_INT
IOSC
0x2 : SYSCTL_RCC_OSCSRC_INT4
IOSC/4
End of enumeration elements list.
SYSCTL_RCC_XTAL : Crystal Value
bits : 6 - 15 (10 bit)
Enumeration:
0x0 : SYSCTL_RCC_XTAL_1MHZ
1 MHz
0x1 : SYSCTL_RCC_XTAL_1_84MHZ
1.8432 MHz
0x2 : SYSCTL_RCC_XTAL_2MHZ
2 MHz
0x3 : SYSCTL_RCC_XTAL_2_45MHZ
2.4576 MHz
0x4 : SYSCTL_RCC_XTAL_3_57MHZ
3.579545 MHz
0x5 : SYSCTL_RCC_XTAL_3_68MHZ
3.6864 MHz
0x6 : SYSCTL_RCC_XTAL_4MHZ
4 MHz
0x7 : SYSCTL_RCC_XTAL_4_09MHZ
4.096 MHz
0x8 : SYSCTL_RCC_XTAL_4_91MHZ
4.9152 MHz
0x9 : SYSCTL_RCC_XTAL_5MHZ
5 MHz
0xa : SYSCTL_RCC_XTAL_5_12MHZ
5.12 MHz
0xb : SYSCTL_RCC_XTAL_6MHZ
6 MHz
0xc : SYSCTL_RCC_XTAL_6_14MHZ
6.144 MHz
0xd : SYSCTL_RCC_XTAL_7_37MHZ
7.3728 MHz
0xe : SYSCTL_RCC_XTAL_8MHZ
8 MHz
0xf : SYSCTL_RCC_XTAL_8_19MHZ
8.192 MHz
End of enumeration elements list.
SYSCTL_RCC_PLLVER : PLL Verification
bits : 10 - 20 (11 bit)
SYSCTL_RCC_BYPASS : PLL Bypass
bits : 11 - 22 (12 bit)
SYSCTL_RCC_OEN : PLL Output Enable
bits : 12 - 24 (13 bit)
SYSCTL_RCC_PWRDN : PLL Power Down
bits : 13 - 26 (14 bit)
SYSCTL_RCC_PWMDIV : PWM Unit Clock Divisor
bits : 17 - 36 (20 bit)
Enumeration:
0x0 : SYSCTL_RCC_PWMDIV_2
PWM clock /2
0x1 : SYSCTL_RCC_PWMDIV_4
PWM clock /4
0x2 : SYSCTL_RCC_PWMDIV_8
PWM clock /8
0x3 : SYSCTL_RCC_PWMDIV_16
PWM clock /16
0x4 : SYSCTL_RCC_PWMDIV_32
PWM clock /32
0x5 : SYSCTL_RCC_PWMDIV_64
PWM clock /64
End of enumeration elements list.
SYSCTL_RCC_USEPWMDIV : Enable PWM Clock Divisor
bits : 20 - 40 (21 bit)
SYSCTL_RCC_USESYSDIV : Enable System Clock Divider
bits : 22 - 44 (23 bit)
SYSCTL_RCC_SYSDIV : System Clock Divisor
bits : 23 - 49 (27 bit)
Enumeration:
0x1 : SYSCTL_RCC_SYSDIV_2
System clock /2
0x2 : SYSCTL_RCC_SYSDIV_3
System clock /3
0x3 : SYSCTL_RCC_SYSDIV_4
System clock /4
0x4 : SYSCTL_RCC_SYSDIV_5
System clock /5
0x5 : SYSCTL_RCC_SYSDIV_6
System clock /6
0x6 : SYSCTL_RCC_SYSDIV_7
System clock /7
0x7 : SYSCTL_RCC_SYSDIV_8
System clock /8
0x8 : SYSCTL_RCC_SYSDIV_9
System clock /9
0x9 : SYSCTL_RCC_SYSDIV_10
System clock /10
0xa : SYSCTL_RCC_SYSDIV_11
System clock /11
0xb : SYSCTL_RCC_SYSDIV_12
System clock /12
0xc : SYSCTL_RCC_SYSDIV_13
System clock /13
0xd : SYSCTL_RCC_SYSDIV_14
System clock /14
0xe : SYSCTL_RCC_SYSDIV_15
System clock /15
0xf : SYSCTL_RCC_SYSDIV_16
System clock /16
End of enumeration elements list.
SYSCTL_RCC_ACG : Auto Clock Gating
bits : 27 - 54 (28 bit)
XTAL to PLL Translation
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PLLCFG_R : PLL R Value
bits : 0 - 4 (5 bit)
SYSCTL_PLLCFG_F : PLL F Value
bits : 5 - 18 (14 bit)
SYSCTL_PLLCFG_OD : PLL OD Value
bits : 14 - 29 (16 bit)
Enumeration:
0x0 : SYSCTL_PLLCFG_OD_1
Divide by 1
0x1 : SYSCTL_PLLCFG_OD_2
Divide by 2
0x2 : SYSCTL_PLLCFG_OD_4
Divide by 4
End of enumeration elements list.
XTAL to PLL Translation
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PLLCFG_R : PLL R Value
bits : 0 - 4 (5 bit)
SYSCTL_PLLCFG_F : PLL F Value
bits : 5 - 18 (14 bit)
SYSCTL_PLLCFG_OD : PLL OD Value
bits : 14 - 29 (16 bit)
Enumeration:
0x0 : SYSCTL_PLLCFG_OD_1
Divide by 1
0x1 : SYSCTL_PLLCFG_OD_2
Divide by 2
0x2 : SYSCTL_PLLCFG_OD_4
Divide by 4
End of enumeration elements list.
Device Capabilities 0
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC0_FLASHSZ : Flash Size
bits : 0 - 15 (16 bit)
Enumeration:
0x7 : SYSCTL_DC0_FLASHSZ_16KB
16 KB of Flash
End of enumeration elements list.
SYSCTL_DC0_SRAMSZ : SRAM Size
bits : 16 - 47 (32 bit)
Enumeration:
0xf : SYSCTL_DC0_SRAMSZ_4KB
4 KB of SRAM
End of enumeration elements list.
Device Capabilities 0
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC0_FLASHSZ : Flash Size
bits : 0 - 15 (16 bit)
Enumeration:
0x7 : SYSCTL_DC0_FLASHSZ_16KB
16 KB of Flash
End of enumeration elements list.
SYSCTL_DC0_SRAMSZ : SRAM Size
bits : 16 - 47 (32 bit)
Enumeration:
0xf : SYSCTL_DC0_SRAMSZ_4KB
4 KB of SRAM
End of enumeration elements list.
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