Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
SysTick Control and Status Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_ST_CTRL_ENABLE : Enable
bits : 0 - 0 (1 bit)
NVIC_ST_CTRL_INTEN : Interrupt Enable
bits : 1 - 2 (2 bit)
NVIC_ST_CTRL_CLK_SRC : Clock Source
bits : 2 - 4 (3 bit)
NVIC_ST_CTRL_COUNT : Count Flag
bits : 16 - 32 (17 bit)
SysTick Control and Status Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_ST_CTRL_ENABLE : Enable
bits : 0 - 0 (1 bit)
NVIC_ST_CTRL_INTEN : Interrupt Enable
bits : 1 - 2 (2 bit)
NVIC_ST_CTRL_CLK_SRC : Clock Source
bits : 2 - 4 (3 bit)
NVIC_ST_CTRL_COUNT : Count Flag
bits : 16 - 32 (17 bit)
Interrupt 0-31 Set Enable
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_EN0_INT : Interrupt Enable
bits : 0 - 31 (32 bit)
Enumeration:
0x1 : NVIC_EN0_INT0
Interrupt 0 enable
0x2 : NVIC_EN0_INT1
Interrupt 1 enable
0x4 : NVIC_EN0_INT2
Interrupt 2 enable
0x8 : NVIC_EN0_INT3
Interrupt 3 enable
0x10 : NVIC_EN0_INT4
Interrupt 4 enable
0x20 : NVIC_EN0_INT5
Interrupt 5 enable
0x40 : NVIC_EN0_INT6
Interrupt 6 enable
0x80 : NVIC_EN0_INT7
Interrupt 7 enable
0x100 : NVIC_EN0_INT8
Interrupt 8 enable
0x200 : NVIC_EN0_INT9
Interrupt 9 enable
0x400 : NVIC_EN0_INT10
Interrupt 10 enable
0x800 : NVIC_EN0_INT11
Interrupt 11 enable
0x1000 : NVIC_EN0_INT12
Interrupt 12 enable
0x2000 : NVIC_EN0_INT13
Interrupt 13 enable
0x4000 : NVIC_EN0_INT14
Interrupt 14 enable
0x8000 : NVIC_EN0_INT15
Interrupt 15 enable
0x10000 : NVIC_EN0_INT16
Interrupt 16 enable
0x20000 : NVIC_EN0_INT17
Interrupt 17 enable
0x40000 : NVIC_EN0_INT18
Interrupt 18 enable
0x80000 : NVIC_EN0_INT19
Interrupt 19 enable
0x100000 : NVIC_EN0_INT20
Interrupt 20 enable
0x200000 : NVIC_EN0_INT21
Interrupt 21 enable
0x400000 : NVIC_EN0_INT22
Interrupt 22 enable
0x800000 : NVIC_EN0_INT23
Interrupt 23 enable
0x1000000 : NVIC_EN0_INT24
Interrupt 24 enable
0x2000000 : NVIC_EN0_INT25
Interrupt 25 enable
0x4000000 : NVIC_EN0_INT26
Interrupt 26 enable
0x8000000 : NVIC_EN0_INT27
Interrupt 27 enable
0x10000000 : NVIC_EN0_INT28
Interrupt 28 enable
0x20000000 : NVIC_EN0_INT29
Interrupt 29 enable
0x40000000 : NVIC_EN0_INT30
Interrupt 30 enable
0x80000000 : NVIC_EN0_INT31
Interrupt 31 enable
End of enumeration elements list.
Interrupt 0-31 Set Enable
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_EN0_INT : Interrupt Enable
bits : 0 - 31 (32 bit)
Enumeration:
0x1 : NVIC_EN0_INT0
Interrupt 0 enable
0x2 : NVIC_EN0_INT1
Interrupt 1 enable
0x4 : NVIC_EN0_INT2
Interrupt 2 enable
0x8 : NVIC_EN0_INT3
Interrupt 3 enable
0x10 : NVIC_EN0_INT4
Interrupt 4 enable
0x20 : NVIC_EN0_INT5
Interrupt 5 enable
0x40 : NVIC_EN0_INT6
Interrupt 6 enable
0x80 : NVIC_EN0_INT7
Interrupt 7 enable
0x100 : NVIC_EN0_INT8
Interrupt 8 enable
0x200 : NVIC_EN0_INT9
Interrupt 9 enable
0x400 : NVIC_EN0_INT10
Interrupt 10 enable
0x800 : NVIC_EN0_INT11
Interrupt 11 enable
0x1000 : NVIC_EN0_INT12
Interrupt 12 enable
0x2000 : NVIC_EN0_INT13
Interrupt 13 enable
0x4000 : NVIC_EN0_INT14
Interrupt 14 enable
0x8000 : NVIC_EN0_INT15
Interrupt 15 enable
0x10000 : NVIC_EN0_INT16
Interrupt 16 enable
0x20000 : NVIC_EN0_INT17
Interrupt 17 enable
0x40000 : NVIC_EN0_INT18
Interrupt 18 enable
0x80000 : NVIC_EN0_INT19
Interrupt 19 enable
0x100000 : NVIC_EN0_INT20
Interrupt 20 enable
0x200000 : NVIC_EN0_INT21
Interrupt 21 enable
0x400000 : NVIC_EN0_INT22
Interrupt 22 enable
0x800000 : NVIC_EN0_INT23
Interrupt 23 enable
0x1000000 : NVIC_EN0_INT24
Interrupt 24 enable
0x2000000 : NVIC_EN0_INT25
Interrupt 25 enable
0x4000000 : NVIC_EN0_INT26
Interrupt 26 enable
0x8000000 : NVIC_EN0_INT27
Interrupt 27 enable
0x10000000 : NVIC_EN0_INT28
Interrupt 28 enable
0x20000000 : NVIC_EN0_INT29
Interrupt 29 enable
0x40000000 : NVIC_EN0_INT30
Interrupt 30 enable
0x80000000 : NVIC_EN0_INT31
Interrupt 31 enable
End of enumeration elements list.
Interrupt 32-54 Set Enable
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_EN1_INT : Interrupt Enable
bits : 0 - 15 (16 bit)
Enumeration:
0x1 : NVIC_EN1_INT32
Interrupt 32 enable
0x2 : NVIC_EN1_INT33
Interrupt 33 enable
0x4 : NVIC_EN1_INT34
Interrupt 34 enable
0x8 : NVIC_EN1_INT35
Interrupt 35 enable
0x10 : NVIC_EN1_INT36
Interrupt 36 enable
0x20 : NVIC_EN1_INT37
Interrupt 37 enable
0x40 : NVIC_EN1_INT38
Interrupt 38 enable
0x80 : NVIC_EN1_INT39
Interrupt 39 enable
0x100 : NVIC_EN1_INT40
Interrupt 40 enable
0x200 : NVIC_EN1_INT41
Interrupt 41 enable
0x400 : NVIC_EN1_INT42
Interrupt 42 enable
0x800 : NVIC_EN1_INT43
Interrupt 43 enable
0x1000 : NVIC_EN1_INT44
Interrupt 44 enable
0x2000 : NVIC_EN1_INT45
Interrupt 45 enable
0x4000 : NVIC_EN1_INT46
Interrupt 46 enable
0x8000 : NVIC_EN1_INT47
Interrupt 47 enable
End of enumeration elements list.
Interrupt 32-54 Set Enable
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_EN1_INT : Interrupt Enable
bits : 0 - 15 (16 bit)
Enumeration:
0x1 : NVIC_EN1_INT32
Interrupt 32 enable
0x2 : NVIC_EN1_INT33
Interrupt 33 enable
0x4 : NVIC_EN1_INT34
Interrupt 34 enable
0x8 : NVIC_EN1_INT35
Interrupt 35 enable
0x10 : NVIC_EN1_INT36
Interrupt 36 enable
0x20 : NVIC_EN1_INT37
Interrupt 37 enable
0x40 : NVIC_EN1_INT38
Interrupt 38 enable
0x80 : NVIC_EN1_INT39
Interrupt 39 enable
0x100 : NVIC_EN1_INT40
Interrupt 40 enable
0x200 : NVIC_EN1_INT41
Interrupt 41 enable
0x400 : NVIC_EN1_INT42
Interrupt 42 enable
0x800 : NVIC_EN1_INT43
Interrupt 43 enable
0x1000 : NVIC_EN1_INT44
Interrupt 44 enable
0x2000 : NVIC_EN1_INT45
Interrupt 45 enable
0x4000 : NVIC_EN1_INT46
Interrupt 46 enable
0x8000 : NVIC_EN1_INT47
Interrupt 47 enable
End of enumeration elements list.
SysTick Reload Value Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_ST_RELOAD : Reload Value
bits : 0 - 23 (24 bit)
SysTick Reload Value Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_ST_RELOAD : Reload Value
bits : 0 - 23 (24 bit)
SysTick Current Value Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_ST_CURRENT : Current Value
bits : 0 - 23 (24 bit)
SysTick Current Value Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_ST_CURRENT : Current Value
bits : 0 - 23 (24 bit)
Interrupt 0-31 Clear Enable
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_DIS0_INT : Interrupt Disable
bits : 0 - 31 (32 bit)
Enumeration:
0x1 : NVIC_DIS0_INT0
Interrupt 0 disable
0x2 : NVIC_DIS0_INT1
Interrupt 1 disable
0x4 : NVIC_DIS0_INT2
Interrupt 2 disable
0x8 : NVIC_DIS0_INT3
Interrupt 3 disable
0x10 : NVIC_DIS0_INT4
Interrupt 4 disable
0x20 : NVIC_DIS0_INT5
Interrupt 5 disable
0x40 : NVIC_DIS0_INT6
Interrupt 6 disable
0x80 : NVIC_DIS0_INT7
Interrupt 7 disable
0x100 : NVIC_DIS0_INT8
Interrupt 8 disable
0x200 : NVIC_DIS0_INT9
Interrupt 9 disable
0x400 : NVIC_DIS0_INT10
Interrupt 10 disable
0x800 : NVIC_DIS0_INT11
Interrupt 11 disable
0x1000 : NVIC_DIS0_INT12
Interrupt 12 disable
0x2000 : NVIC_DIS0_INT13
Interrupt 13 disable
0x4000 : NVIC_DIS0_INT14
Interrupt 14 disable
0x8000 : NVIC_DIS0_INT15
Interrupt 15 disable
0x10000 : NVIC_DIS0_INT16
Interrupt 16 disable
0x20000 : NVIC_DIS0_INT17
Interrupt 17 disable
0x40000 : NVIC_DIS0_INT18
Interrupt 18 disable
0x80000 : NVIC_DIS0_INT19
Interrupt 19 disable
0x100000 : NVIC_DIS0_INT20
Interrupt 20 disable
0x200000 : NVIC_DIS0_INT21
Interrupt 21 disable
0x400000 : NVIC_DIS0_INT22
Interrupt 22 disable
0x800000 : NVIC_DIS0_INT23
Interrupt 23 disable
0x1000000 : NVIC_DIS0_INT24
Interrupt 24 disable
0x2000000 : NVIC_DIS0_INT25
Interrupt 25 disable
0x4000000 : NVIC_DIS0_INT26
Interrupt 26 disable
0x8000000 : NVIC_DIS0_INT27
Interrupt 27 disable
0x10000000 : NVIC_DIS0_INT28
Interrupt 28 disable
0x20000000 : NVIC_DIS0_INT29
Interrupt 29 disable
0x40000000 : NVIC_DIS0_INT30
Interrupt 30 disable
0x80000000 : NVIC_DIS0_INT31
Interrupt 31 disable
End of enumeration elements list.
Interrupt 0-31 Clear Enable
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_DIS0_INT : Interrupt Disable
bits : 0 - 31 (32 bit)
Enumeration:
0x1 : NVIC_DIS0_INT0
Interrupt 0 disable
0x2 : NVIC_DIS0_INT1
Interrupt 1 disable
0x4 : NVIC_DIS0_INT2
Interrupt 2 disable
0x8 : NVIC_DIS0_INT3
Interrupt 3 disable
0x10 : NVIC_DIS0_INT4
Interrupt 4 disable
0x20 : NVIC_DIS0_INT5
Interrupt 5 disable
0x40 : NVIC_DIS0_INT6
Interrupt 6 disable
0x80 : NVIC_DIS0_INT7
Interrupt 7 disable
0x100 : NVIC_DIS0_INT8
Interrupt 8 disable
0x200 : NVIC_DIS0_INT9
Interrupt 9 disable
0x400 : NVIC_DIS0_INT10
Interrupt 10 disable
0x800 : NVIC_DIS0_INT11
Interrupt 11 disable
0x1000 : NVIC_DIS0_INT12
Interrupt 12 disable
0x2000 : NVIC_DIS0_INT13
Interrupt 13 disable
0x4000 : NVIC_DIS0_INT14
Interrupt 14 disable
0x8000 : NVIC_DIS0_INT15
Interrupt 15 disable
0x10000 : NVIC_DIS0_INT16
Interrupt 16 disable
0x20000 : NVIC_DIS0_INT17
Interrupt 17 disable
0x40000 : NVIC_DIS0_INT18
Interrupt 18 disable
0x80000 : NVIC_DIS0_INT19
Interrupt 19 disable
0x100000 : NVIC_DIS0_INT20
Interrupt 20 disable
0x200000 : NVIC_DIS0_INT21
Interrupt 21 disable
0x400000 : NVIC_DIS0_INT22
Interrupt 22 disable
0x800000 : NVIC_DIS0_INT23
Interrupt 23 disable
0x1000000 : NVIC_DIS0_INT24
Interrupt 24 disable
0x2000000 : NVIC_DIS0_INT25
Interrupt 25 disable
0x4000000 : NVIC_DIS0_INT26
Interrupt 26 disable
0x8000000 : NVIC_DIS0_INT27
Interrupt 27 disable
0x10000000 : NVIC_DIS0_INT28
Interrupt 28 disable
0x20000000 : NVIC_DIS0_INT29
Interrupt 29 disable
0x40000000 : NVIC_DIS0_INT30
Interrupt 30 disable
0x80000000 : NVIC_DIS0_INT31
Interrupt 31 disable
End of enumeration elements list.
Interrupt 32-54 Clear Enable
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_DIS1_INT : Interrupt Disable
bits : 0 - 15 (16 bit)
Enumeration:
0x1 : NVIC_DIS1_INT32
Interrupt 32 disable
0x2 : NVIC_DIS1_INT33
Interrupt 33 disable
0x4 : NVIC_DIS1_INT34
Interrupt 34 disable
0x8 : NVIC_DIS1_INT35
Interrupt 35 disable
0x10 : NVIC_DIS1_INT36
Interrupt 36 disable
0x20 : NVIC_DIS1_INT37
Interrupt 37 disable
0x40 : NVIC_DIS1_INT38
Interrupt 38 disable
0x80 : NVIC_DIS1_INT39
Interrupt 39 disable
0x100 : NVIC_DIS1_INT40
Interrupt 40 disable
0x200 : NVIC_DIS1_INT41
Interrupt 41 disable
0x400 : NVIC_DIS1_INT42
Interrupt 42 disable
0x800 : NVIC_DIS1_INT43
Interrupt 43 disable
0x1000 : NVIC_DIS1_INT44
Interrupt 44 disable
0x2000 : NVIC_DIS1_INT45
Interrupt 45 disable
0x4000 : NVIC_DIS1_INT46
Interrupt 46 disable
0x8000 : NVIC_DIS1_INT47
Interrupt 47 disable
End of enumeration elements list.
Interrupt 32-54 Clear Enable
address_offset : 0x184 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_DIS1_INT : Interrupt Disable
bits : 0 - 15 (16 bit)
Enumeration:
0x1 : NVIC_DIS1_INT32
Interrupt 32 disable
0x2 : NVIC_DIS1_INT33
Interrupt 33 disable
0x4 : NVIC_DIS1_INT34
Interrupt 34 disable
0x8 : NVIC_DIS1_INT35
Interrupt 35 disable
0x10 : NVIC_DIS1_INT36
Interrupt 36 disable
0x20 : NVIC_DIS1_INT37
Interrupt 37 disable
0x40 : NVIC_DIS1_INT38
Interrupt 38 disable
0x80 : NVIC_DIS1_INT39
Interrupt 39 disable
0x100 : NVIC_DIS1_INT40
Interrupt 40 disable
0x200 : NVIC_DIS1_INT41
Interrupt 41 disable
0x400 : NVIC_DIS1_INT42
Interrupt 42 disable
0x800 : NVIC_DIS1_INT43
Interrupt 43 disable
0x1000 : NVIC_DIS1_INT44
Interrupt 44 disable
0x2000 : NVIC_DIS1_INT45
Interrupt 45 disable
0x4000 : NVIC_DIS1_INT46
Interrupt 46 disable
0x8000 : NVIC_DIS1_INT47
Interrupt 47 disable
End of enumeration elements list.
SysTick Calibration Value Reg
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_ST_CAL_ONEMS : 1ms reference value
bits : 0 - 23 (24 bit)
NVIC_ST_CAL_SKEW : Clock skew
bits : 30 - 60 (31 bit)
NVIC_ST_CAL_NOREF : No reference clock
bits : 31 - 62 (32 bit)
SysTick Calibration Value Reg
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_ST_CAL_ONEMS : 1ms reference value
bits : 0 - 23 (24 bit)
NVIC_ST_CAL_SKEW : Clock skew
bits : 30 - 60 (31 bit)
NVIC_ST_CAL_NOREF : No reference clock
bits : 31 - 62 (32 bit)
Interrupt 0-31 Set Pending
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PEND0_INT : Interrupt Set Pending
bits : 0 - 31 (32 bit)
Enumeration:
0x1 : NVIC_PEND0_INT0
Interrupt 0 pend
0x2 : NVIC_PEND0_INT1
Interrupt 1 pend
0x4 : NVIC_PEND0_INT2
Interrupt 2 pend
0x8 : NVIC_PEND0_INT3
Interrupt 3 pend
0x10 : NVIC_PEND0_INT4
Interrupt 4 pend
0x20 : NVIC_PEND0_INT5
Interrupt 5 pend
0x40 : NVIC_PEND0_INT6
Interrupt 6 pend
0x80 : NVIC_PEND0_INT7
Interrupt 7 pend
0x100 : NVIC_PEND0_INT8
Interrupt 8 pend
0x200 : NVIC_PEND0_INT9
Interrupt 9 pend
0x400 : NVIC_PEND0_INT10
Interrupt 10 pend
0x800 : NVIC_PEND0_INT11
Interrupt 11 pend
0x1000 : NVIC_PEND0_INT12
Interrupt 12 pend
0x2000 : NVIC_PEND0_INT13
Interrupt 13 pend
0x4000 : NVIC_PEND0_INT14
Interrupt 14 pend
0x8000 : NVIC_PEND0_INT15
Interrupt 15 pend
0x10000 : NVIC_PEND0_INT16
Interrupt 16 pend
0x20000 : NVIC_PEND0_INT17
Interrupt 17 pend
0x40000 : NVIC_PEND0_INT18
Interrupt 18 pend
0x80000 : NVIC_PEND0_INT19
Interrupt 19 pend
0x100000 : NVIC_PEND0_INT20
Interrupt 20 pend
0x200000 : NVIC_PEND0_INT21
Interrupt 21 pend
0x400000 : NVIC_PEND0_INT22
Interrupt 22 pend
0x800000 : NVIC_PEND0_INT23
Interrupt 23 pend
0x1000000 : NVIC_PEND0_INT24
Interrupt 24 pend
0x2000000 : NVIC_PEND0_INT25
Interrupt 25 pend
0x4000000 : NVIC_PEND0_INT26
Interrupt 26 pend
0x8000000 : NVIC_PEND0_INT27
Interrupt 27 pend
0x10000000 : NVIC_PEND0_INT28
Interrupt 28 pend
0x20000000 : NVIC_PEND0_INT29
Interrupt 29 pend
0x40000000 : NVIC_PEND0_INT30
Interrupt 30 pend
0x80000000 : NVIC_PEND0_INT31
Interrupt 31 pend
End of enumeration elements list.
Interrupt 0-31 Set Pending
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PEND0_INT : Interrupt Set Pending
bits : 0 - 31 (32 bit)
Enumeration:
0x1 : NVIC_PEND0_INT0
Interrupt 0 pend
0x2 : NVIC_PEND0_INT1
Interrupt 1 pend
0x4 : NVIC_PEND0_INT2
Interrupt 2 pend
0x8 : NVIC_PEND0_INT3
Interrupt 3 pend
0x10 : NVIC_PEND0_INT4
Interrupt 4 pend
0x20 : NVIC_PEND0_INT5
Interrupt 5 pend
0x40 : NVIC_PEND0_INT6
Interrupt 6 pend
0x80 : NVIC_PEND0_INT7
Interrupt 7 pend
0x100 : NVIC_PEND0_INT8
Interrupt 8 pend
0x200 : NVIC_PEND0_INT9
Interrupt 9 pend
0x400 : NVIC_PEND0_INT10
Interrupt 10 pend
0x800 : NVIC_PEND0_INT11
Interrupt 11 pend
0x1000 : NVIC_PEND0_INT12
Interrupt 12 pend
0x2000 : NVIC_PEND0_INT13
Interrupt 13 pend
0x4000 : NVIC_PEND0_INT14
Interrupt 14 pend
0x8000 : NVIC_PEND0_INT15
Interrupt 15 pend
0x10000 : NVIC_PEND0_INT16
Interrupt 16 pend
0x20000 : NVIC_PEND0_INT17
Interrupt 17 pend
0x40000 : NVIC_PEND0_INT18
Interrupt 18 pend
0x80000 : NVIC_PEND0_INT19
Interrupt 19 pend
0x100000 : NVIC_PEND0_INT20
Interrupt 20 pend
0x200000 : NVIC_PEND0_INT21
Interrupt 21 pend
0x400000 : NVIC_PEND0_INT22
Interrupt 22 pend
0x800000 : NVIC_PEND0_INT23
Interrupt 23 pend
0x1000000 : NVIC_PEND0_INT24
Interrupt 24 pend
0x2000000 : NVIC_PEND0_INT25
Interrupt 25 pend
0x4000000 : NVIC_PEND0_INT26
Interrupt 26 pend
0x8000000 : NVIC_PEND0_INT27
Interrupt 27 pend
0x10000000 : NVIC_PEND0_INT28
Interrupt 28 pend
0x20000000 : NVIC_PEND0_INT29
Interrupt 29 pend
0x40000000 : NVIC_PEND0_INT30
Interrupt 30 pend
0x80000000 : NVIC_PEND0_INT31
Interrupt 31 pend
End of enumeration elements list.
Interrupt 32-54 Set Pending
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PEND1_INT : Interrupt Set Pending
bits : 0 - 15 (16 bit)
Enumeration:
0x1 : NVIC_PEND1_INT32
Interrupt 32 pend
0x2 : NVIC_PEND1_INT33
Interrupt 33 pend
0x4 : NVIC_PEND1_INT34
Interrupt 34 pend
0x8 : NVIC_PEND1_INT35
Interrupt 35 pend
0x10 : NVIC_PEND1_INT36
Interrupt 36 pend
0x20 : NVIC_PEND1_INT37
Interrupt 37 pend
0x40 : NVIC_PEND1_INT38
Interrupt 38 pend
0x80 : NVIC_PEND1_INT39
Interrupt 39 pend
0x100 : NVIC_PEND1_INT40
Interrupt 40 pend
0x200 : NVIC_PEND1_INT41
Interrupt 41 pend
0x400 : NVIC_PEND1_INT42
Interrupt 42 pend
0x800 : NVIC_PEND1_INT43
Interrupt 43 pend
0x1000 : NVIC_PEND1_INT44
Interrupt 44 pend
0x2000 : NVIC_PEND1_INT45
Interrupt 45 pend
0x4000 : NVIC_PEND1_INT46
Interrupt 46 pend
0x8000 : NVIC_PEND1_INT47
Interrupt 47 pend
End of enumeration elements list.
Interrupt 32-54 Set Pending
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PEND1_INT : Interrupt Set Pending
bits : 0 - 15 (16 bit)
Enumeration:
0x1 : NVIC_PEND1_INT32
Interrupt 32 pend
0x2 : NVIC_PEND1_INT33
Interrupt 33 pend
0x4 : NVIC_PEND1_INT34
Interrupt 34 pend
0x8 : NVIC_PEND1_INT35
Interrupt 35 pend
0x10 : NVIC_PEND1_INT36
Interrupt 36 pend
0x20 : NVIC_PEND1_INT37
Interrupt 37 pend
0x40 : NVIC_PEND1_INT38
Interrupt 38 pend
0x80 : NVIC_PEND1_INT39
Interrupt 39 pend
0x100 : NVIC_PEND1_INT40
Interrupt 40 pend
0x200 : NVIC_PEND1_INT41
Interrupt 41 pend
0x400 : NVIC_PEND1_INT42
Interrupt 42 pend
0x800 : NVIC_PEND1_INT43
Interrupt 43 pend
0x1000 : NVIC_PEND1_INT44
Interrupt 44 pend
0x2000 : NVIC_PEND1_INT45
Interrupt 45 pend
0x4000 : NVIC_PEND1_INT46
Interrupt 46 pend
0x8000 : NVIC_PEND1_INT47
Interrupt 47 pend
End of enumeration elements list.
Interrupt 0-31 Clear Pending
address_offset : 0x280 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_UNPEND0_INT : Interrupt Clear Pending
bits : 0 - 31 (32 bit)
Enumeration:
0x1 : NVIC_UNPEND0_INT0
Interrupt 0 unpend
0x2 : NVIC_UNPEND0_INT1
Interrupt 1 unpend
0x4 : NVIC_UNPEND0_INT2
Interrupt 2 unpend
0x8 : NVIC_UNPEND0_INT3
Interrupt 3 unpend
0x10 : NVIC_UNPEND0_INT4
Interrupt 4 unpend
0x20 : NVIC_UNPEND0_INT5
Interrupt 5 unpend
0x40 : NVIC_UNPEND0_INT6
Interrupt 6 unpend
0x80 : NVIC_UNPEND0_INT7
Interrupt 7 unpend
0x100 : NVIC_UNPEND0_INT8
Interrupt 8 unpend
0x200 : NVIC_UNPEND0_INT9
Interrupt 9 unpend
0x400 : NVIC_UNPEND0_INT10
Interrupt 10 unpend
0x800 : NVIC_UNPEND0_INT11
Interrupt 11 unpend
0x1000 : NVIC_UNPEND0_INT12
Interrupt 12 unpend
0x2000 : NVIC_UNPEND0_INT13
Interrupt 13 unpend
0x4000 : NVIC_UNPEND0_INT14
Interrupt 14 unpend
0x8000 : NVIC_UNPEND0_INT15
Interrupt 15 unpend
0x10000 : NVIC_UNPEND0_INT16
Interrupt 16 unpend
0x20000 : NVIC_UNPEND0_INT17
Interrupt 17 unpend
0x40000 : NVIC_UNPEND0_INT18
Interrupt 18 unpend
0x80000 : NVIC_UNPEND0_INT19
Interrupt 19 unpend
0x100000 : NVIC_UNPEND0_INT20
Interrupt 20 unpend
0x200000 : NVIC_UNPEND0_INT21
Interrupt 21 unpend
0x400000 : NVIC_UNPEND0_INT22
Interrupt 22 unpend
0x800000 : NVIC_UNPEND0_INT23
Interrupt 23 unpend
0x1000000 : NVIC_UNPEND0_INT24
Interrupt 24 unpend
0x2000000 : NVIC_UNPEND0_INT25
Interrupt 25 unpend
0x4000000 : NVIC_UNPEND0_INT26
Interrupt 26 unpend
0x8000000 : NVIC_UNPEND0_INT27
Interrupt 27 unpend
0x10000000 : NVIC_UNPEND0_INT28
Interrupt 28 unpend
0x20000000 : NVIC_UNPEND0_INT29
Interrupt 29 unpend
0x40000000 : NVIC_UNPEND0_INT30
Interrupt 30 unpend
0x80000000 : NVIC_UNPEND0_INT31
Interrupt 31 unpend
End of enumeration elements list.
Interrupt 0-31 Clear Pending
address_offset : 0x280 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_UNPEND0_INT : Interrupt Clear Pending
bits : 0 - 31 (32 bit)
Enumeration:
0x1 : NVIC_UNPEND0_INT0
Interrupt 0 unpend
0x2 : NVIC_UNPEND0_INT1
Interrupt 1 unpend
0x4 : NVIC_UNPEND0_INT2
Interrupt 2 unpend
0x8 : NVIC_UNPEND0_INT3
Interrupt 3 unpend
0x10 : NVIC_UNPEND0_INT4
Interrupt 4 unpend
0x20 : NVIC_UNPEND0_INT5
Interrupt 5 unpend
0x40 : NVIC_UNPEND0_INT6
Interrupt 6 unpend
0x80 : NVIC_UNPEND0_INT7
Interrupt 7 unpend
0x100 : NVIC_UNPEND0_INT8
Interrupt 8 unpend
0x200 : NVIC_UNPEND0_INT9
Interrupt 9 unpend
0x400 : NVIC_UNPEND0_INT10
Interrupt 10 unpend
0x800 : NVIC_UNPEND0_INT11
Interrupt 11 unpend
0x1000 : NVIC_UNPEND0_INT12
Interrupt 12 unpend
0x2000 : NVIC_UNPEND0_INT13
Interrupt 13 unpend
0x4000 : NVIC_UNPEND0_INT14
Interrupt 14 unpend
0x8000 : NVIC_UNPEND0_INT15
Interrupt 15 unpend
0x10000 : NVIC_UNPEND0_INT16
Interrupt 16 unpend
0x20000 : NVIC_UNPEND0_INT17
Interrupt 17 unpend
0x40000 : NVIC_UNPEND0_INT18
Interrupt 18 unpend
0x80000 : NVIC_UNPEND0_INT19
Interrupt 19 unpend
0x100000 : NVIC_UNPEND0_INT20
Interrupt 20 unpend
0x200000 : NVIC_UNPEND0_INT21
Interrupt 21 unpend
0x400000 : NVIC_UNPEND0_INT22
Interrupt 22 unpend
0x800000 : NVIC_UNPEND0_INT23
Interrupt 23 unpend
0x1000000 : NVIC_UNPEND0_INT24
Interrupt 24 unpend
0x2000000 : NVIC_UNPEND0_INT25
Interrupt 25 unpend
0x4000000 : NVIC_UNPEND0_INT26
Interrupt 26 unpend
0x8000000 : NVIC_UNPEND0_INT27
Interrupt 27 unpend
0x10000000 : NVIC_UNPEND0_INT28
Interrupt 28 unpend
0x20000000 : NVIC_UNPEND0_INT29
Interrupt 29 unpend
0x40000000 : NVIC_UNPEND0_INT30
Interrupt 30 unpend
0x80000000 : NVIC_UNPEND0_INT31
Interrupt 31 unpend
End of enumeration elements list.
Interrupt 32-54 Clear Pending
address_offset : 0x284 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_UNPEND1_INT : Interrupt Clear Pending
bits : 0 - 15 (16 bit)
Enumeration:
0x1 : NVIC_UNPEND1_INT32
Interrupt 32 unpend
0x2 : NVIC_UNPEND1_INT33
Interrupt 33 unpend
0x4 : NVIC_UNPEND1_INT34
Interrupt 34 unpend
0x8 : NVIC_UNPEND1_INT35
Interrupt 35 unpend
0x10 : NVIC_UNPEND1_INT36
Interrupt 36 unpend
0x20 : NVIC_UNPEND1_INT37
Interrupt 37 unpend
0x40 : NVIC_UNPEND1_INT38
Interrupt 38 unpend
0x80 : NVIC_UNPEND1_INT39
Interrupt 39 unpend
0x100 : NVIC_UNPEND1_INT40
Interrupt 40 unpend
0x200 : NVIC_UNPEND1_INT41
Interrupt 41 unpend
0x400 : NVIC_UNPEND1_INT42
Interrupt 42 unpend
0x800 : NVIC_UNPEND1_INT43
Interrupt 43 unpend
0x1000 : NVIC_UNPEND1_INT44
Interrupt 44 unpend
0x2000 : NVIC_UNPEND1_INT45
Interrupt 45 unpend
0x4000 : NVIC_UNPEND1_INT46
Interrupt 46 unpend
0x8000 : NVIC_UNPEND1_INT47
Interrupt 47 unpend
End of enumeration elements list.
Interrupt 32-54 Clear Pending
address_offset : 0x284 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_UNPEND1_INT : Interrupt Clear Pending
bits : 0 - 15 (16 bit)
Enumeration:
0x1 : NVIC_UNPEND1_INT32
Interrupt 32 unpend
0x2 : NVIC_UNPEND1_INT33
Interrupt 33 unpend
0x4 : NVIC_UNPEND1_INT34
Interrupt 34 unpend
0x8 : NVIC_UNPEND1_INT35
Interrupt 35 unpend
0x10 : NVIC_UNPEND1_INT36
Interrupt 36 unpend
0x20 : NVIC_UNPEND1_INT37
Interrupt 37 unpend
0x40 : NVIC_UNPEND1_INT38
Interrupt 38 unpend
0x80 : NVIC_UNPEND1_INT39
Interrupt 39 unpend
0x100 : NVIC_UNPEND1_INT40
Interrupt 40 unpend
0x200 : NVIC_UNPEND1_INT41
Interrupt 41 unpend
0x400 : NVIC_UNPEND1_INT42
Interrupt 42 unpend
0x800 : NVIC_UNPEND1_INT43
Interrupt 43 unpend
0x1000 : NVIC_UNPEND1_INT44
Interrupt 44 unpend
0x2000 : NVIC_UNPEND1_INT45
Interrupt 45 unpend
0x4000 : NVIC_UNPEND1_INT46
Interrupt 46 unpend
0x8000 : NVIC_UNPEND1_INT47
Interrupt 47 unpend
End of enumeration elements list.
Interrupt 0-31 Active Bit
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_ACTIVE0_INT : Interrupt Active
bits : 0 - 31 (32 bit)
Enumeration:
0x1 : NVIC_ACTIVE0_INT0
Interrupt 0 active
0x2 : NVIC_ACTIVE0_INT1
Interrupt 1 active
0x4 : NVIC_ACTIVE0_INT2
Interrupt 2 active
0x8 : NVIC_ACTIVE0_INT3
Interrupt 3 active
0x10 : NVIC_ACTIVE0_INT4
Interrupt 4 active
0x20 : NVIC_ACTIVE0_INT5
Interrupt 5 active
0x40 : NVIC_ACTIVE0_INT6
Interrupt 6 active
0x80 : NVIC_ACTIVE0_INT7
Interrupt 7 active
0x100 : NVIC_ACTIVE0_INT8
Interrupt 8 active
0x200 : NVIC_ACTIVE0_INT9
Interrupt 9 active
0x400 : NVIC_ACTIVE0_INT10
Interrupt 10 active
0x800 : NVIC_ACTIVE0_INT11
Interrupt 11 active
0x1000 : NVIC_ACTIVE0_INT12
Interrupt 12 active
0x2000 : NVIC_ACTIVE0_INT13
Interrupt 13 active
0x4000 : NVIC_ACTIVE0_INT14
Interrupt 14 active
0x8000 : NVIC_ACTIVE0_INT15
Interrupt 15 active
0x10000 : NVIC_ACTIVE0_INT16
Interrupt 16 active
0x20000 : NVIC_ACTIVE0_INT17
Interrupt 17 active
0x40000 : NVIC_ACTIVE0_INT18
Interrupt 18 active
0x80000 : NVIC_ACTIVE0_INT19
Interrupt 19 active
0x100000 : NVIC_ACTIVE0_INT20
Interrupt 20 active
0x200000 : NVIC_ACTIVE0_INT21
Interrupt 21 active
0x400000 : NVIC_ACTIVE0_INT22
Interrupt 22 active
0x800000 : NVIC_ACTIVE0_INT23
Interrupt 23 active
0x1000000 : NVIC_ACTIVE0_INT24
Interrupt 24 active
0x2000000 : NVIC_ACTIVE0_INT25
Interrupt 25 active
0x4000000 : NVIC_ACTIVE0_INT26
Interrupt 26 active
0x8000000 : NVIC_ACTIVE0_INT27
Interrupt 27 active
0x10000000 : NVIC_ACTIVE0_INT28
Interrupt 28 active
0x20000000 : NVIC_ACTIVE0_INT29
Interrupt 29 active
0x40000000 : NVIC_ACTIVE0_INT30
Interrupt 30 active
0x80000000 : NVIC_ACTIVE0_INT31
Interrupt 31 active
End of enumeration elements list.
Interrupt 0-31 Active Bit
address_offset : 0x300 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_ACTIVE0_INT : Interrupt Active
bits : 0 - 31 (32 bit)
Enumeration:
0x1 : NVIC_ACTIVE0_INT0
Interrupt 0 active
0x2 : NVIC_ACTIVE0_INT1
Interrupt 1 active
0x4 : NVIC_ACTIVE0_INT2
Interrupt 2 active
0x8 : NVIC_ACTIVE0_INT3
Interrupt 3 active
0x10 : NVIC_ACTIVE0_INT4
Interrupt 4 active
0x20 : NVIC_ACTIVE0_INT5
Interrupt 5 active
0x40 : NVIC_ACTIVE0_INT6
Interrupt 6 active
0x80 : NVIC_ACTIVE0_INT7
Interrupt 7 active
0x100 : NVIC_ACTIVE0_INT8
Interrupt 8 active
0x200 : NVIC_ACTIVE0_INT9
Interrupt 9 active
0x400 : NVIC_ACTIVE0_INT10
Interrupt 10 active
0x800 : NVIC_ACTIVE0_INT11
Interrupt 11 active
0x1000 : NVIC_ACTIVE0_INT12
Interrupt 12 active
0x2000 : NVIC_ACTIVE0_INT13
Interrupt 13 active
0x4000 : NVIC_ACTIVE0_INT14
Interrupt 14 active
0x8000 : NVIC_ACTIVE0_INT15
Interrupt 15 active
0x10000 : NVIC_ACTIVE0_INT16
Interrupt 16 active
0x20000 : NVIC_ACTIVE0_INT17
Interrupt 17 active
0x40000 : NVIC_ACTIVE0_INT18
Interrupt 18 active
0x80000 : NVIC_ACTIVE0_INT19
Interrupt 19 active
0x100000 : NVIC_ACTIVE0_INT20
Interrupt 20 active
0x200000 : NVIC_ACTIVE0_INT21
Interrupt 21 active
0x400000 : NVIC_ACTIVE0_INT22
Interrupt 22 active
0x800000 : NVIC_ACTIVE0_INT23
Interrupt 23 active
0x1000000 : NVIC_ACTIVE0_INT24
Interrupt 24 active
0x2000000 : NVIC_ACTIVE0_INT25
Interrupt 25 active
0x4000000 : NVIC_ACTIVE0_INT26
Interrupt 26 active
0x8000000 : NVIC_ACTIVE0_INT27
Interrupt 27 active
0x10000000 : NVIC_ACTIVE0_INT28
Interrupt 28 active
0x20000000 : NVIC_ACTIVE0_INT29
Interrupt 29 active
0x40000000 : NVIC_ACTIVE0_INT30
Interrupt 30 active
0x80000000 : NVIC_ACTIVE0_INT31
Interrupt 31 active
End of enumeration elements list.
Interrupt 32-54 Active Bit
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_ACTIVE1_INT : Interrupt Active
bits : 0 - 15 (16 bit)
Enumeration:
0x1 : NVIC_ACTIVE1_INT32
Interrupt 32 active
0x2 : NVIC_ACTIVE1_INT33
Interrupt 33 active
0x4 : NVIC_ACTIVE1_INT34
Interrupt 34 active
0x8 : NVIC_ACTIVE1_INT35
Interrupt 35 active
0x10 : NVIC_ACTIVE1_INT36
Interrupt 36 active
0x20 : NVIC_ACTIVE1_INT37
Interrupt 37 active
0x40 : NVIC_ACTIVE1_INT38
Interrupt 38 active
0x80 : NVIC_ACTIVE1_INT39
Interrupt 39 active
0x100 : NVIC_ACTIVE1_INT40
Interrupt 40 active
0x200 : NVIC_ACTIVE1_INT41
Interrupt 41 active
0x400 : NVIC_ACTIVE1_INT42
Interrupt 42 active
0x800 : NVIC_ACTIVE1_INT43
Interrupt 43 active
0x1000 : NVIC_ACTIVE1_INT44
Interrupt 44 active
0x2000 : NVIC_ACTIVE1_INT45
Interrupt 45 active
0x4000 : NVIC_ACTIVE1_INT46
Interrupt 46 active
0x8000 : NVIC_ACTIVE1_INT47
Interrupt 47 active
End of enumeration elements list.
Interrupt 32-54 Active Bit
address_offset : 0x304 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_ACTIVE1_INT : Interrupt Active
bits : 0 - 15 (16 bit)
Enumeration:
0x1 : NVIC_ACTIVE1_INT32
Interrupt 32 active
0x2 : NVIC_ACTIVE1_INT33
Interrupt 33 active
0x4 : NVIC_ACTIVE1_INT34
Interrupt 34 active
0x8 : NVIC_ACTIVE1_INT35
Interrupt 35 active
0x10 : NVIC_ACTIVE1_INT36
Interrupt 36 active
0x20 : NVIC_ACTIVE1_INT37
Interrupt 37 active
0x40 : NVIC_ACTIVE1_INT38
Interrupt 38 active
0x80 : NVIC_ACTIVE1_INT39
Interrupt 39 active
0x100 : NVIC_ACTIVE1_INT40
Interrupt 40 active
0x200 : NVIC_ACTIVE1_INT41
Interrupt 41 active
0x400 : NVIC_ACTIVE1_INT42
Interrupt 42 active
0x800 : NVIC_ACTIVE1_INT43
Interrupt 43 active
0x1000 : NVIC_ACTIVE1_INT44
Interrupt 44 active
0x2000 : NVIC_ACTIVE1_INT45
Interrupt 45 active
0x4000 : NVIC_ACTIVE1_INT46
Interrupt 46 active
0x8000 : NVIC_ACTIVE1_INT47
Interrupt 47 active
End of enumeration elements list.
Interrupt Controller Type Reg
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_INT_TYPE_LINES : Number of interrupt lines (x32)
bits : 0 - 4 (5 bit)
Interrupt Controller Type Reg
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_INT_TYPE_LINES : Number of interrupt lines (x32)
bits : 0 - 4 (5 bit)
Interrupt 0-3 Priority
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI0_INT0 : Interrupt 0 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI0_INT1 : Interrupt 1 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI0_INT2 : Interrupt 2 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI0_INT3 : Interrupt 3 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 0-3 Priority
address_offset : 0x400 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI0_INT0 : Interrupt 0 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI0_INT1 : Interrupt 1 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI0_INT2 : Interrupt 2 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI0_INT3 : Interrupt 3 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 4-7 Priority
address_offset : 0x404 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI1_INT4 : Interrupt 4 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI1_INT5 : Interrupt 5 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI1_INT6 : Interrupt 6 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI1_INT7 : Interrupt 7 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 4-7 Priority
address_offset : 0x404 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI1_INT4 : Interrupt 4 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI1_INT5 : Interrupt 5 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI1_INT6 : Interrupt 6 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI1_INT7 : Interrupt 7 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 8-11 Priority
address_offset : 0x408 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI2_INT8 : Interrupt 8 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI2_INT9 : Interrupt 9 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI2_INT10 : Interrupt 10 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI2_INT11 : Interrupt 11 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 8-11 Priority
address_offset : 0x408 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI2_INT8 : Interrupt 8 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI2_INT9 : Interrupt 9 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI2_INT10 : Interrupt 10 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI2_INT11 : Interrupt 11 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 12-15 Priority
address_offset : 0x40C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI3_INT12 : Interrupt 12 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI3_INT13 : Interrupt 13 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI3_INT14 : Interrupt 14 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI3_INT15 : Interrupt 15 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 12-15 Priority
address_offset : 0x40C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI3_INT12 : Interrupt 12 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI3_INT13 : Interrupt 13 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI3_INT14 : Interrupt 14 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI3_INT15 : Interrupt 15 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 16-19 Priority
address_offset : 0x410 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI4_INT16 : Interrupt 16 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI4_INT17 : Interrupt 17 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI4_INT18 : Interrupt 18 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI4_INT19 : Interrupt 19 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 16-19 Priority
address_offset : 0x410 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI4_INT16 : Interrupt 16 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI4_INT17 : Interrupt 17 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI4_INT18 : Interrupt 18 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI4_INT19 : Interrupt 19 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 20-23 Priority
address_offset : 0x414 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI5_INT20 : Interrupt 20 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI5_INT21 : Interrupt 21 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI5_INT22 : Interrupt 22 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI5_INT23 : Interrupt 23 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 20-23 Priority
address_offset : 0x414 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI5_INT20 : Interrupt 20 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI5_INT21 : Interrupt 21 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI5_INT22 : Interrupt 22 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI5_INT23 : Interrupt 23 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 24-27 Priority
address_offset : 0x418 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI6_INT24 : Interrupt 24 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI6_INT25 : Interrupt 25 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI6_INT26 : Interrupt 26 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI6_INT27 : Interrupt 27 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 24-27 Priority
address_offset : 0x418 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI6_INT24 : Interrupt 24 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI6_INT25 : Interrupt 25 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI6_INT26 : Interrupt 26 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI6_INT27 : Interrupt 27 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 28-31 Priority
address_offset : 0x41C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI7_INT28 : Interrupt 28 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI7_INT29 : Interrupt 29 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI7_INT30 : Interrupt 30 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI7_INT31 : Interrupt 31 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 28-31 Priority
address_offset : 0x41C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI7_INT28 : Interrupt 28 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI7_INT29 : Interrupt 29 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI7_INT30 : Interrupt 30 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI7_INT31 : Interrupt 31 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 32-35 Priority
address_offset : 0x420 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI8_INT32 : Interrupt 32 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI8_INT33 : Interrupt 33 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI8_INT34 : Interrupt 34 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI8_INT35 : Interrupt 35 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 32-35 Priority
address_offset : 0x420 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI8_INT32 : Interrupt 32 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI8_INT33 : Interrupt 33 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI8_INT34 : Interrupt 34 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI8_INT35 : Interrupt 35 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 36-39 Priority
address_offset : 0x424 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI9_INT36 : Interrupt 36 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI9_INT37 : Interrupt 37 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI9_INT38 : Interrupt 38 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI9_INT39 : Interrupt 39 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 36-39 Priority
address_offset : 0x424 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI9_INT36 : Interrupt 36 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI9_INT37 : Interrupt 37 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI9_INT38 : Interrupt 38 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI9_INT39 : Interrupt 39 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 40-43 Priority
address_offset : 0x428 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI10_INT40 : Interrupt 40 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI10_INT41 : Interrupt 41 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI10_INT42 : Interrupt 42 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI10_INT43 : Interrupt 43 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 40-43 Priority
address_offset : 0x428 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI10_INT40 : Interrupt 40 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI10_INT41 : Interrupt 41 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI10_INT42 : Interrupt 42 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI10_INT43 : Interrupt 43 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 44-47 Priority
address_offset : 0x42C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI11_INT44 : Interrupt 44 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI11_INT45 : Interrupt 45 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI11_INT46 : Interrupt 46 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI11_INT47 : Interrupt 47 Priority Mask
bits : 29 - 60 (32 bit)
Interrupt 44-47 Priority
address_offset : 0x42C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_PRI11_INT44 : Interrupt 44 Priority Mask
bits : 5 - 12 (8 bit)
NVIC_PRI11_INT45 : Interrupt 45 Priority Mask
bits : 13 - 28 (16 bit)
NVIC_PRI11_INT46 : Interrupt 46 Priority Mask
bits : 21 - 44 (24 bit)
NVIC_PRI11_INT47 : Interrupt 47 Priority Mask
bits : 29 - 60 (32 bit)
CPU ID Base
address_offset : 0xD00 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_CPUID_REV : Revision Number
bits : 0 - 3 (4 bit)
NVIC_CPUID_PARTNO : Part Number
bits : 4 - 19 (16 bit)
Enumeration:
0xc23 : NVIC_CPUID_PARTNO_CM3
Cortex-M3 processor
End of enumeration elements list.
NVIC_CPUID_CON : Constant
bits : 16 - 35 (20 bit)
NVIC_CPUID_VAR : Variant Number
bits : 20 - 43 (24 bit)
NVIC_CPUID_IMP : Implementer Code
bits : 24 - 55 (32 bit)
Enumeration:
0x41 : NVIC_CPUID_IMP_ARM
ARM
End of enumeration elements list.
CPU ID Base
address_offset : 0xD00 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_CPUID_REV : Revision Number
bits : 0 - 3 (4 bit)
NVIC_CPUID_PARTNO : Part Number
bits : 4 - 19 (16 bit)
Enumeration:
0xc23 : NVIC_CPUID_PARTNO_CM3
Cortex-M3 processor
End of enumeration elements list.
NVIC_CPUID_CON : Constant
bits : 16 - 35 (20 bit)
NVIC_CPUID_VAR : Variant Number
bits : 20 - 43 (24 bit)
NVIC_CPUID_IMP : Implementer Code
bits : 24 - 55 (32 bit)
Enumeration:
0x41 : NVIC_CPUID_IMP_ARM
ARM
End of enumeration elements list.
Interrupt Control and State
address_offset : 0xD04 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_INT_CTRL_VEC_ACT : Interrupt Pending Vector Number
bits : 0 - 6 (7 bit)
NVIC_INT_CTRL_RET_BASE : Return to Base
bits : 11 - 22 (12 bit)
NVIC_INT_CTRL_VEC_PEN : Interrupt Pending Vector Number
bits : 12 - 30 (19 bit)
Enumeration:
0x2 : NVIC_INT_CTRL_VEC_PEN_NMI
NMI
0x3 : NVIC_INT_CTRL_VEC_PEN_HARD
Hard fault
0x4 : NVIC_INT_CTRL_VEC_PEN_MEM
Memory management fault
0x5 : NVIC_INT_CTRL_VEC_PEN_BUS
Bus fault
0x6 : NVIC_INT_CTRL_VEC_PEN_USG
Usage fault
0xb : NVIC_INT_CTRL_VEC_PEN_SVC
SVCall
0xe : NVIC_INT_CTRL_VEC_PEN_PNDSV
PendSV
0xf : NVIC_INT_CTRL_VEC_PEN_TICK
SysTick
End of enumeration elements list.
NVIC_INT_CTRL_ISR_PEND : Interrupt Pending
bits : 22 - 44 (23 bit)
NVIC_INT_CTRL_ISR_PRE : Debug Interrupt Handling
bits : 23 - 46 (24 bit)
NVIC_INT_CTRL_PENDSTCLR : SysTick Clear Pending
bits : 25 - 50 (26 bit)
NVIC_INT_CTRL_PENDSTSET : SysTick Set Pending
bits : 26 - 52 (27 bit)
NVIC_INT_CTRL_UNPEND_SV : PendSV Clear Pending
bits : 27 - 54 (28 bit)
NVIC_INT_CTRL_PEND_SV : PendSV Set Pending
bits : 28 - 56 (29 bit)
NVIC_INT_CTRL_NMI_SET : NMI Set Pending
bits : 31 - 62 (32 bit)
Interrupt Control and State
address_offset : 0xD04 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_INT_CTRL_VEC_ACT : Interrupt Pending Vector Number
bits : 0 - 6 (7 bit)
NVIC_INT_CTRL_RET_BASE : Return to Base
bits : 11 - 22 (12 bit)
NVIC_INT_CTRL_VEC_PEN : Interrupt Pending Vector Number
bits : 12 - 30 (19 bit)
Enumeration:
0x2 : NVIC_INT_CTRL_VEC_PEN_NMI
NMI
0x3 : NVIC_INT_CTRL_VEC_PEN_HARD
Hard fault
0x4 : NVIC_INT_CTRL_VEC_PEN_MEM
Memory management fault
0x5 : NVIC_INT_CTRL_VEC_PEN_BUS
Bus fault
0x6 : NVIC_INT_CTRL_VEC_PEN_USG
Usage fault
0xb : NVIC_INT_CTRL_VEC_PEN_SVC
SVCall
0xe : NVIC_INT_CTRL_VEC_PEN_PNDSV
PendSV
0xf : NVIC_INT_CTRL_VEC_PEN_TICK
SysTick
End of enumeration elements list.
NVIC_INT_CTRL_ISR_PEND : Interrupt Pending
bits : 22 - 44 (23 bit)
NVIC_INT_CTRL_ISR_PRE : Debug Interrupt Handling
bits : 23 - 46 (24 bit)
NVIC_INT_CTRL_PENDSTCLR : SysTick Clear Pending
bits : 25 - 50 (26 bit)
NVIC_INT_CTRL_PENDSTSET : SysTick Set Pending
bits : 26 - 52 (27 bit)
NVIC_INT_CTRL_UNPEND_SV : PendSV Clear Pending
bits : 27 - 54 (28 bit)
NVIC_INT_CTRL_PEND_SV : PendSV Set Pending
bits : 28 - 56 (29 bit)
NVIC_INT_CTRL_NMI_SET : NMI Set Pending
bits : 31 - 62 (32 bit)
Vector Table Offset
address_offset : 0xD08 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_VTABLE_OFFSET : Vector Table Offset
bits : 8 - 36 (29 bit)
NVIC_VTABLE_BASE : Vector Table Base
bits : 29 - 58 (30 bit)
Vector Table Offset
address_offset : 0xD08 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_VTABLE_OFFSET : Vector Table Offset
bits : 8 - 36 (29 bit)
NVIC_VTABLE_BASE : Vector Table Base
bits : 29 - 58 (30 bit)
Application Interrupt and Reset Control
address_offset : 0xD0C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_APINT_VECT_RESET : System Reset
bits : 0 - 0 (1 bit)
NVIC_APINT_VECT_CLR_ACT : Clear Active NMI / Fault
bits : 1 - 2 (2 bit)
NVIC_APINT_SYSRESETREQ : System Reset Request
bits : 2 - 4 (3 bit)
NVIC_APINT_PRIGROUP : Interrupt Priority Grouping
bits : 8 - 18 (11 bit)
Enumeration:
0x0 : NVIC_APINT_PRIGROUP_7_1
Priority group 7.1 split
0x1 : NVIC_APINT_PRIGROUP_6_2
Priority group 6.2 split
0x2 : NVIC_APINT_PRIGROUP_5_3
Priority group 5.3 split
0x3 : NVIC_APINT_PRIGROUP_4_4
Priority group 4.4 split
0x4 : NVIC_APINT_PRIGROUP_3_5
Priority group 3.5 split
0x5 : NVIC_APINT_PRIGROUP_2_6
Priority group 2.6 split
0x6 : NVIC_APINT_PRIGROUP_1_7
Priority group 1.7 split
0x7 : NVIC_APINT_PRIGROUP_0_8
Priority group 0.8 split
End of enumeration elements list.
NVIC_APINT_ENDIANESS : Data Endianess
bits : 15 - 30 (16 bit)
NVIC_APINT_VECTKEY : Register Key
bits : 16 - 47 (32 bit)
Enumeration:
0x5fa : NVIC_APINT_VECTKEY
Vector key
End of enumeration elements list.
Application Interrupt and Reset Control
address_offset : 0xD0C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_APINT_VECT_RESET : System Reset
bits : 0 - 0 (1 bit)
NVIC_APINT_VECT_CLR_ACT : Clear Active NMI / Fault
bits : 1 - 2 (2 bit)
NVIC_APINT_SYSRESETREQ : System Reset Request
bits : 2 - 4 (3 bit)
NVIC_APINT_PRIGROUP : Interrupt Priority Grouping
bits : 8 - 18 (11 bit)
Enumeration:
0x0 : NVIC_APINT_PRIGROUP_7_1
Priority group 7.1 split
0x1 : NVIC_APINT_PRIGROUP_6_2
Priority group 6.2 split
0x2 : NVIC_APINT_PRIGROUP_5_3
Priority group 5.3 split
0x3 : NVIC_APINT_PRIGROUP_4_4
Priority group 4.4 split
0x4 : NVIC_APINT_PRIGROUP_3_5
Priority group 3.5 split
0x5 : NVIC_APINT_PRIGROUP_2_6
Priority group 2.6 split
0x6 : NVIC_APINT_PRIGROUP_1_7
Priority group 1.7 split
0x7 : NVIC_APINT_PRIGROUP_0_8
Priority group 0.8 split
End of enumeration elements list.
NVIC_APINT_ENDIANESS : Data Endianess
bits : 15 - 30 (16 bit)
NVIC_APINT_VECTKEY : Register Key
bits : 16 - 47 (32 bit)
Enumeration:
0x5fa : NVIC_APINT_VECTKEY
Vector key
End of enumeration elements list.
System Control
address_offset : 0xD10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_SYS_CTRL_SLEEPEXIT : Sleep on ISR Exit
bits : 1 - 2 (2 bit)
NVIC_SYS_CTRL_SLEEPDEEP : Deep Sleep Enable
bits : 2 - 4 (3 bit)
NVIC_SYS_CTRL_SEVONPEND : Wake Up on Pending
bits : 4 - 8 (5 bit)
System Control
address_offset : 0xD10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_SYS_CTRL_SLEEPEXIT : Sleep on ISR Exit
bits : 1 - 2 (2 bit)
NVIC_SYS_CTRL_SLEEPDEEP : Deep Sleep Enable
bits : 2 - 4 (3 bit)
NVIC_SYS_CTRL_SEVONPEND : Wake Up on Pending
bits : 4 - 8 (5 bit)
Configuration and Control
address_offset : 0xD14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_CFG_CTRL_BASE_THR : Thread State Control
bits : 0 - 0 (1 bit)
NVIC_CFG_CTRL_MAIN_PEND : Allow Main Interrupt Trigger
bits : 1 - 2 (2 bit)
NVIC_CFG_CTRL_UNALIGNED : Trap on Unaligned Access
bits : 3 - 6 (4 bit)
NVIC_CFG_CTRL_DIV0 : Trap on Divide by 0
bits : 4 - 8 (5 bit)
NVIC_CFG_CTRL_BFHFNMIGN : Ignore Bus Fault in NMI and Fault
bits : 8 - 16 (9 bit)
NVIC_CFG_CTRL_STKALIGN : Stack Alignment on Exception Entry
bits : 9 - 18 (10 bit)
Configuration and Control
address_offset : 0xD14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_CFG_CTRL_BASE_THR : Thread State Control
bits : 0 - 0 (1 bit)
NVIC_CFG_CTRL_MAIN_PEND : Allow Main Interrupt Trigger
bits : 1 - 2 (2 bit)
NVIC_CFG_CTRL_UNALIGNED : Trap on Unaligned Access
bits : 3 - 6 (4 bit)
NVIC_CFG_CTRL_DIV0 : Trap on Divide by 0
bits : 4 - 8 (5 bit)
NVIC_CFG_CTRL_BFHFNMIGN : Ignore Bus Fault in NMI and Fault
bits : 8 - 16 (9 bit)
NVIC_CFG_CTRL_STKALIGN : Stack Alignment on Exception Entry
bits : 9 - 18 (10 bit)
System Handler Priority 1
address_offset : 0xD18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_SYS_PRI1_MEM : Memory Management Fault Priority
bits : 5 - 12 (8 bit)
NVIC_SYS_PRI1_BUS : Bus Fault Priority
bits : 13 - 28 (16 bit)
NVIC_SYS_PRI1_USAGE : Usage Fault Priority
bits : 21 - 44 (24 bit)
System Handler Priority 1
address_offset : 0xD18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_SYS_PRI1_MEM : Memory Management Fault Priority
bits : 5 - 12 (8 bit)
NVIC_SYS_PRI1_BUS : Bus Fault Priority
bits : 13 - 28 (16 bit)
NVIC_SYS_PRI1_USAGE : Usage Fault Priority
bits : 21 - 44 (24 bit)
System Handler Priority 2
address_offset : 0xD1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_SYS_PRI2_SVC : SVCall Priority
bits : 29 - 60 (32 bit)
System Handler Priority 2
address_offset : 0xD1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_SYS_PRI2_SVC : SVCall Priority
bits : 29 - 60 (32 bit)
System Handler Priority 3
address_offset : 0xD20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_SYS_PRI3_DEBUG : Debug Priority
bits : 5 - 12 (8 bit)
NVIC_SYS_PRI3_PENDSV : PendSV Priority
bits : 21 - 44 (24 bit)
NVIC_SYS_PRI3_TICK : SysTick Exception Priority
bits : 29 - 60 (32 bit)
System Handler Priority 3
address_offset : 0xD20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_SYS_PRI3_DEBUG : Debug Priority
bits : 5 - 12 (8 bit)
NVIC_SYS_PRI3_PENDSV : PendSV Priority
bits : 21 - 44 (24 bit)
NVIC_SYS_PRI3_TICK : SysTick Exception Priority
bits : 29 - 60 (32 bit)
System Handler Control and State
address_offset : 0xD24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_SYS_HND_CTRL_MEMA : Memory Management Fault Active
bits : 0 - 0 (1 bit)
NVIC_SYS_HND_CTRL_BUSA : Bus Fault Active
bits : 1 - 2 (2 bit)
NVIC_SYS_HND_CTRL_USGA : Usage Fault Active
bits : 3 - 6 (4 bit)
NVIC_SYS_HND_CTRL_SVCA : SVC Call Active
bits : 7 - 14 (8 bit)
NVIC_SYS_HND_CTRL_MON : Debug Monitor Active
bits : 8 - 16 (9 bit)
NVIC_SYS_HND_CTRL_PNDSV : PendSV Exception Active
bits : 10 - 20 (11 bit)
NVIC_SYS_HND_CTRL_TICK : SysTick Exception Active
bits : 11 - 22 (12 bit)
NVIC_SYS_HND_CTRL_USAGEP : Usage Fault Pending
bits : 12 - 24 (13 bit)
NVIC_SYS_HND_CTRL_MEMP : Memory Management Fault Pending
bits : 13 - 26 (14 bit)
NVIC_SYS_HND_CTRL_BUSP : Bus Fault Pending
bits : 14 - 28 (15 bit)
NVIC_SYS_HND_CTRL_SVC : SVC Call Pending
bits : 15 - 30 (16 bit)
NVIC_SYS_HND_CTRL_MEM : Memory Management Fault Enable
bits : 16 - 32 (17 bit)
NVIC_SYS_HND_CTRL_BUS : Bus Fault Enable
bits : 17 - 34 (18 bit)
NVIC_SYS_HND_CTRL_USAGE : Usage Fault Enable
bits : 18 - 36 (19 bit)
System Handler Control and State
address_offset : 0xD24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_SYS_HND_CTRL_MEMA : Memory Management Fault Active
bits : 0 - 0 (1 bit)
NVIC_SYS_HND_CTRL_BUSA : Bus Fault Active
bits : 1 - 2 (2 bit)
NVIC_SYS_HND_CTRL_USGA : Usage Fault Active
bits : 3 - 6 (4 bit)
NVIC_SYS_HND_CTRL_SVCA : SVC Call Active
bits : 7 - 14 (8 bit)
NVIC_SYS_HND_CTRL_MON : Debug Monitor Active
bits : 8 - 16 (9 bit)
NVIC_SYS_HND_CTRL_PNDSV : PendSV Exception Active
bits : 10 - 20 (11 bit)
NVIC_SYS_HND_CTRL_TICK : SysTick Exception Active
bits : 11 - 22 (12 bit)
NVIC_SYS_HND_CTRL_USAGEP : Usage Fault Pending
bits : 12 - 24 (13 bit)
NVIC_SYS_HND_CTRL_MEMP : Memory Management Fault Pending
bits : 13 - 26 (14 bit)
NVIC_SYS_HND_CTRL_BUSP : Bus Fault Pending
bits : 14 - 28 (15 bit)
NVIC_SYS_HND_CTRL_SVC : SVC Call Pending
bits : 15 - 30 (16 bit)
NVIC_SYS_HND_CTRL_MEM : Memory Management Fault Enable
bits : 16 - 32 (17 bit)
NVIC_SYS_HND_CTRL_BUS : Bus Fault Enable
bits : 17 - 34 (18 bit)
NVIC_SYS_HND_CTRL_USAGE : Usage Fault Enable
bits : 18 - 36 (19 bit)
Configurable Fault Status
address_offset : 0xD28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_FAULT_STAT_IERR : Instruction Access Violation
bits : 0 - 0 (1 bit)
NVIC_FAULT_STAT_DERR : Data Access Violation
bits : 1 - 2 (2 bit)
NVIC_FAULT_STAT_MUSTKE : Unstack Access Violation
bits : 3 - 6 (4 bit)
NVIC_FAULT_STAT_MSTKE : Stack Access Violation
bits : 4 - 8 (5 bit)
NVIC_FAULT_STAT_MMARV : Memory Management Fault Address Register Valid
bits : 7 - 14 (8 bit)
NVIC_FAULT_STAT_IBUS : Instruction Bus Error
bits : 8 - 16 (9 bit)
NVIC_FAULT_STAT_PRECISE : Precise Data Bus Error
bits : 9 - 18 (10 bit)
NVIC_FAULT_STAT_IMPRE : Imprecise Data Bus Error
bits : 10 - 20 (11 bit)
NVIC_FAULT_STAT_BUSTKE : Unstack Bus Fault
bits : 11 - 22 (12 bit)
NVIC_FAULT_STAT_BSTKE : Stack Bus Fault
bits : 12 - 24 (13 bit)
NVIC_FAULT_STAT_BFARV : Bus Fault Address Register Valid
bits : 15 - 30 (16 bit)
NVIC_FAULT_STAT_UNDEF : Undefined Instruction Usage Fault
bits : 16 - 32 (17 bit)
NVIC_FAULT_STAT_INVSTAT : Invalid State Usage Fault
bits : 17 - 34 (18 bit)
NVIC_FAULT_STAT_INVPC : Invalid PC Load Usage Fault
bits : 18 - 36 (19 bit)
NVIC_FAULT_STAT_NOCP : No Coprocessor Usage Fault
bits : 19 - 38 (20 bit)
NVIC_FAULT_STAT_UNALIGN : Unaligned Access Usage Fault
bits : 24 - 48 (25 bit)
NVIC_FAULT_STAT_DIV0 : Divide-by-Zero Usage Fault
bits : 25 - 50 (26 bit)
Configurable Fault Status
address_offset : 0xD28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_FAULT_STAT_IERR : Instruction Access Violation
bits : 0 - 0 (1 bit)
NVIC_FAULT_STAT_DERR : Data Access Violation
bits : 1 - 2 (2 bit)
NVIC_FAULT_STAT_MUSTKE : Unstack Access Violation
bits : 3 - 6 (4 bit)
NVIC_FAULT_STAT_MSTKE : Stack Access Violation
bits : 4 - 8 (5 bit)
NVIC_FAULT_STAT_MMARV : Memory Management Fault Address Register Valid
bits : 7 - 14 (8 bit)
NVIC_FAULT_STAT_IBUS : Instruction Bus Error
bits : 8 - 16 (9 bit)
NVIC_FAULT_STAT_PRECISE : Precise Data Bus Error
bits : 9 - 18 (10 bit)
NVIC_FAULT_STAT_IMPRE : Imprecise Data Bus Error
bits : 10 - 20 (11 bit)
NVIC_FAULT_STAT_BUSTKE : Unstack Bus Fault
bits : 11 - 22 (12 bit)
NVIC_FAULT_STAT_BSTKE : Stack Bus Fault
bits : 12 - 24 (13 bit)
NVIC_FAULT_STAT_BFARV : Bus Fault Address Register Valid
bits : 15 - 30 (16 bit)
NVIC_FAULT_STAT_UNDEF : Undefined Instruction Usage Fault
bits : 16 - 32 (17 bit)
NVIC_FAULT_STAT_INVSTAT : Invalid State Usage Fault
bits : 17 - 34 (18 bit)
NVIC_FAULT_STAT_INVPC : Invalid PC Load Usage Fault
bits : 18 - 36 (19 bit)
NVIC_FAULT_STAT_NOCP : No Coprocessor Usage Fault
bits : 19 - 38 (20 bit)
NVIC_FAULT_STAT_UNALIGN : Unaligned Access Usage Fault
bits : 24 - 48 (25 bit)
NVIC_FAULT_STAT_DIV0 : Divide-by-Zero Usage Fault
bits : 25 - 50 (26 bit)
Hard Fault Status
address_offset : 0xD2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_HFAULT_STAT_VECT : Vector Table Read Fault
bits : 1 - 2 (2 bit)
NVIC_HFAULT_STAT_FORCED : Forced Hard Fault
bits : 30 - 60 (31 bit)
NVIC_HFAULT_STAT_DBG : Debug Event
bits : 31 - 62 (32 bit)
Hard Fault Status
address_offset : 0xD2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_HFAULT_STAT_VECT : Vector Table Read Fault
bits : 1 - 2 (2 bit)
NVIC_HFAULT_STAT_FORCED : Forced Hard Fault
bits : 30 - 60 (31 bit)
NVIC_HFAULT_STAT_DBG : Debug Event
bits : 31 - 62 (32 bit)
Debug Status Register
address_offset : 0xD30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_DEBUG_STAT_HALTED : Halt request
bits : 0 - 0 (1 bit)
NVIC_DEBUG_STAT_BKPT : Breakpoint instruction
bits : 1 - 2 (2 bit)
NVIC_DEBUG_STAT_DWTTRAP : DWT match
bits : 2 - 4 (3 bit)
NVIC_DEBUG_STAT_VCATCH : Vector catch
bits : 3 - 6 (4 bit)
NVIC_DEBUG_STAT_EXTRNL : EDBGRQ asserted
bits : 4 - 8 (5 bit)
Debug Status Register
address_offset : 0xD30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_DEBUG_STAT_HALTED : Halt request
bits : 0 - 0 (1 bit)
NVIC_DEBUG_STAT_BKPT : Breakpoint instruction
bits : 1 - 2 (2 bit)
NVIC_DEBUG_STAT_DWTTRAP : DWT match
bits : 2 - 4 (3 bit)
NVIC_DEBUG_STAT_VCATCH : Vector catch
bits : 3 - 6 (4 bit)
NVIC_DEBUG_STAT_EXTRNL : EDBGRQ asserted
bits : 4 - 8 (5 bit)
Memory Management Fault Address
address_offset : 0xD34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MM_ADDR : Fault Address
bits : 0 - 31 (32 bit)
Memory Management Fault Address
address_offset : 0xD34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MM_ADDR : Fault Address
bits : 0 - 31 (32 bit)
Bus Fault Address
address_offset : 0xD38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_FAULT_ADDR : Fault Address
bits : 0 - 31 (32 bit)
Bus Fault Address
address_offset : 0xD38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_FAULT_ADDR : Fault Address
bits : 0 - 31 (32 bit)
MPU Type
address_offset : 0xD90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_TYPE_SEPARATE : Separate or Unified MPU
bits : 0 - 0 (1 bit)
NVIC_MPU_TYPE_DREGION : Number of D Regions
bits : 8 - 23 (16 bit)
NVIC_MPU_TYPE_IREGION : Number of I Regions
bits : 16 - 39 (24 bit)
MPU Type
address_offset : 0xD90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_TYPE_SEPARATE : Separate or Unified MPU
bits : 0 - 0 (1 bit)
NVIC_MPU_TYPE_DREGION : Number of D Regions
bits : 8 - 23 (16 bit)
NVIC_MPU_TYPE_IREGION : Number of I Regions
bits : 16 - 39 (24 bit)
MPU Control
address_offset : 0xD94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_CTRL_ENABLE : MPU Enable
bits : 0 - 0 (1 bit)
NVIC_MPU_CTRL_HFNMIENA : MPU Enabled During Faults
bits : 1 - 2 (2 bit)
NVIC_MPU_CTRL_PRIVDEFEN : MPU Default Region
bits : 2 - 4 (3 bit)
MPU Control
address_offset : 0xD94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_CTRL_ENABLE : MPU Enable
bits : 0 - 0 (1 bit)
NVIC_MPU_CTRL_HFNMIENA : MPU Enabled During Faults
bits : 1 - 2 (2 bit)
NVIC_MPU_CTRL_PRIVDEFEN : MPU Default Region
bits : 2 - 4 (3 bit)
MPU Region Number
address_offset : 0xD98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_NUMBER : MPU Region to Access
bits : 0 - 2 (3 bit)
MPU Region Number
address_offset : 0xD98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_NUMBER : MPU Region to Access
bits : 0 - 2 (3 bit)
MPU Region Base Address
address_offset : 0xD9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_BASE_REGION : Region Number
bits : 0 - 2 (3 bit)
NVIC_MPU_BASE_VALID : Region Number Valid
bits : 4 - 8 (5 bit)
NVIC_MPU_BASE_ADDR : Base Address Mask
bits : 5 - 36 (32 bit)
MPU Region Base Address
address_offset : 0xD9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_BASE_REGION : Region Number
bits : 0 - 2 (3 bit)
NVIC_MPU_BASE_VALID : Region Number Valid
bits : 4 - 8 (5 bit)
NVIC_MPU_BASE_ADDR : Base Address Mask
bits : 5 - 36 (32 bit)
MPU Region Attribute and Size
address_offset : 0xDA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_ATTR_ENABLE : Region Enable
bits : 0 - 0 (1 bit)
NVIC_MPU_ATTR_SIZE : Region Size Mask
bits : 1 - 6 (6 bit)
Enumeration:
0x4 : NVIC_MPU_ATTR_SIZE_32B
Region size 32 bytes
0x5 : NVIC_MPU_ATTR_SIZE_64B
Region size 64 bytes
0x6 : NVIC_MPU_ATTR_SIZE_128B
Region size 128 bytes
0x7 : NVIC_MPU_ATTR_SIZE_256B
Region size 256 bytes
0x8 : NVIC_MPU_ATTR_SIZE_512B
Region size 512 bytes
0x9 : NVIC_MPU_ATTR_SIZE_1K
Region size 1 Kbytes
0xa : NVIC_MPU_ATTR_SIZE_2K
Region size 2 Kbytes
0xb : NVIC_MPU_ATTR_SIZE_4K
Region size 4 Kbytes
0xc : NVIC_MPU_ATTR_SIZE_8K
Region size 8 Kbytes
0xd : NVIC_MPU_ATTR_SIZE_16K
Region size 16 Kbytes
0xe : NVIC_MPU_ATTR_SIZE_32K
Region size 32 Kbytes
0xf : NVIC_MPU_ATTR_SIZE_64K
Region size 64 Kbytes
0x10 : NVIC_MPU_ATTR_SIZE_128K
Region size 128 Kbytes
0x11 : NVIC_MPU_ATTR_SIZE_256K
Region size 256 Kbytes
0x12 : NVIC_MPU_ATTR_SIZE_512K
Region size 512 Kbytes
0x13 : NVIC_MPU_ATTR_SIZE_1M
Region size 1 Mbytes
0x14 : NVIC_MPU_ATTR_SIZE_2M
Region size 2 Mbytes
0x15 : NVIC_MPU_ATTR_SIZE_4M
Region size 4 Mbytes
0x16 : NVIC_MPU_ATTR_SIZE_8M
Region size 8 Mbytes
0x17 : NVIC_MPU_ATTR_SIZE_16M
Region size 16 Mbytes
0x18 : NVIC_MPU_ATTR_SIZE_32M
Region size 32 Mbytes
0x19 : NVIC_MPU_ATTR_SIZE_64M
Region size 64 Mbytes
0x1a : NVIC_MPU_ATTR_SIZE_128M
Region size 128 Mbytes
0x1b : NVIC_MPU_ATTR_SIZE_256M
Region size 256 Mbytes
0x1c : NVIC_MPU_ATTR_SIZE_512M
Region size 512 Mbytes
0x1d : NVIC_MPU_ATTR_SIZE_1G
Region size 1 Gbytes
0x1e : NVIC_MPU_ATTR_SIZE_2G
Region size 2 Gbytes
0x1f : NVIC_MPU_ATTR_SIZE_4G
Region size 4 Gbytes
End of enumeration elements list.
NVIC_MPU_ATTR_SRD : Subregion Disable Bits
bits : 8 - 23 (16 bit)
Enumeration:
0x1 : NVIC_MPU_ATTR_SRD_0
Sub-region 0 disable
0x2 : NVIC_MPU_ATTR_SRD_1
Sub-region 1 disable
0x4 : NVIC_MPU_ATTR_SRD_2
Sub-region 2 disable
0x8 : NVIC_MPU_ATTR_SRD_3
Sub-region 3 disable
0x10 : NVIC_MPU_ATTR_SRD_4
Sub-region 4 disable
0x20 : NVIC_MPU_ATTR_SRD_5
Sub-region 5 disable
0x40 : NVIC_MPU_ATTR_SRD_6
Sub-region 6 disable
0x80 : NVIC_MPU_ATTR_SRD_7
Sub-region 7 disable
End of enumeration elements list.
NVIC_MPU_ATTR_BUFFRABLE : Bufferable
bits : 16 - 32 (17 bit)
NVIC_MPU_ATTR_CACHEABLE : Cacheable
bits : 17 - 34 (18 bit)
NVIC_MPU_ATTR_SHAREABLE : Shareable
bits : 18 - 36 (19 bit)
NVIC_MPU_ATTR_TEX : Type Extension Mask
bits : 19 - 40 (22 bit)
NVIC_MPU_ATTR_AP : Access Privilege
bits : 24 - 50 (27 bit)
Enumeration:
0x0 : NVIC_MPU_ATTR_AP_NO_NO
prv: no access, usr: no access
0x1 : NVIC_MPU_ATTR_AP_RW_NO
prv: rw, usr: none
0x2 : NVIC_MPU_ATTR_AP_RW_RO
prv: rw, usr: read-only
0x3 : NVIC_MPU_ATTR_AP_RW_RW
prv: rw, usr: rw
0x5 : NVIC_MPU_ATTR_AP_RO_NO
prv: ro, usr: none
0x6 : NVIC_MPU_ATTR_AP_RO_RO
prv: ro, usr: ro
End of enumeration elements list.
NVIC_MPU_ATTR_XN : Instruction Access Disable
bits : 28 - 56 (29 bit)
MPU Region Attribute and Size
address_offset : 0xDA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_ATTR_ENABLE : Region Enable
bits : 0 - 0 (1 bit)
NVIC_MPU_ATTR_SIZE : Region Size Mask
bits : 1 - 6 (6 bit)
Enumeration:
0x4 : NVIC_MPU_ATTR_SIZE_32B
Region size 32 bytes
0x5 : NVIC_MPU_ATTR_SIZE_64B
Region size 64 bytes
0x6 : NVIC_MPU_ATTR_SIZE_128B
Region size 128 bytes
0x7 : NVIC_MPU_ATTR_SIZE_256B
Region size 256 bytes
0x8 : NVIC_MPU_ATTR_SIZE_512B
Region size 512 bytes
0x9 : NVIC_MPU_ATTR_SIZE_1K
Region size 1 Kbytes
0xa : NVIC_MPU_ATTR_SIZE_2K
Region size 2 Kbytes
0xb : NVIC_MPU_ATTR_SIZE_4K
Region size 4 Kbytes
0xc : NVIC_MPU_ATTR_SIZE_8K
Region size 8 Kbytes
0xd : NVIC_MPU_ATTR_SIZE_16K
Region size 16 Kbytes
0xe : NVIC_MPU_ATTR_SIZE_32K
Region size 32 Kbytes
0xf : NVIC_MPU_ATTR_SIZE_64K
Region size 64 Kbytes
0x10 : NVIC_MPU_ATTR_SIZE_128K
Region size 128 Kbytes
0x11 : NVIC_MPU_ATTR_SIZE_256K
Region size 256 Kbytes
0x12 : NVIC_MPU_ATTR_SIZE_512K
Region size 512 Kbytes
0x13 : NVIC_MPU_ATTR_SIZE_1M
Region size 1 Mbytes
0x14 : NVIC_MPU_ATTR_SIZE_2M
Region size 2 Mbytes
0x15 : NVIC_MPU_ATTR_SIZE_4M
Region size 4 Mbytes
0x16 : NVIC_MPU_ATTR_SIZE_8M
Region size 8 Mbytes
0x17 : NVIC_MPU_ATTR_SIZE_16M
Region size 16 Mbytes
0x18 : NVIC_MPU_ATTR_SIZE_32M
Region size 32 Mbytes
0x19 : NVIC_MPU_ATTR_SIZE_64M
Region size 64 Mbytes
0x1a : NVIC_MPU_ATTR_SIZE_128M
Region size 128 Mbytes
0x1b : NVIC_MPU_ATTR_SIZE_256M
Region size 256 Mbytes
0x1c : NVIC_MPU_ATTR_SIZE_512M
Region size 512 Mbytes
0x1d : NVIC_MPU_ATTR_SIZE_1G
Region size 1 Gbytes
0x1e : NVIC_MPU_ATTR_SIZE_2G
Region size 2 Gbytes
0x1f : NVIC_MPU_ATTR_SIZE_4G
Region size 4 Gbytes
End of enumeration elements list.
NVIC_MPU_ATTR_SRD : Subregion Disable Bits
bits : 8 - 23 (16 bit)
Enumeration:
0x1 : NVIC_MPU_ATTR_SRD_0
Sub-region 0 disable
0x2 : NVIC_MPU_ATTR_SRD_1
Sub-region 1 disable
0x4 : NVIC_MPU_ATTR_SRD_2
Sub-region 2 disable
0x8 : NVIC_MPU_ATTR_SRD_3
Sub-region 3 disable
0x10 : NVIC_MPU_ATTR_SRD_4
Sub-region 4 disable
0x20 : NVIC_MPU_ATTR_SRD_5
Sub-region 5 disable
0x40 : NVIC_MPU_ATTR_SRD_6
Sub-region 6 disable
0x80 : NVIC_MPU_ATTR_SRD_7
Sub-region 7 disable
End of enumeration elements list.
NVIC_MPU_ATTR_BUFFRABLE : Bufferable
bits : 16 - 32 (17 bit)
NVIC_MPU_ATTR_CACHEABLE : Cacheable
bits : 17 - 34 (18 bit)
NVIC_MPU_ATTR_SHAREABLE : Shareable
bits : 18 - 36 (19 bit)
NVIC_MPU_ATTR_TEX : Type Extension Mask
bits : 19 - 40 (22 bit)
NVIC_MPU_ATTR_AP : Access Privilege
bits : 24 - 50 (27 bit)
Enumeration:
0x0 : NVIC_MPU_ATTR_AP_NO_NO
prv: no access, usr: no access
0x1 : NVIC_MPU_ATTR_AP_RW_NO
prv: rw, usr: none
0x2 : NVIC_MPU_ATTR_AP_RW_RO
prv: rw, usr: read-only
0x3 : NVIC_MPU_ATTR_AP_RW_RW
prv: rw, usr: rw
0x5 : NVIC_MPU_ATTR_AP_RO_NO
prv: ro, usr: none
0x6 : NVIC_MPU_ATTR_AP_RO_RO
prv: ro, usr: ro
End of enumeration elements list.
NVIC_MPU_ATTR_XN : Instruction Access Disable
bits : 28 - 56 (29 bit)
MPU Region Base Address Alias 1
address_offset : 0xDA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_BASE1_REGION : Region Number
bits : 0 - 2 (3 bit)
NVIC_MPU_BASE1_VALID : Region Number Valid
bits : 4 - 8 (5 bit)
NVIC_MPU_BASE1_ADDR : Base Address Mask
bits : 5 - 36 (32 bit)
MPU Region Base Address Alias 1
address_offset : 0xDA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_BASE1_REGION : Region Number
bits : 0 - 2 (3 bit)
NVIC_MPU_BASE1_VALID : Region Number Valid
bits : 4 - 8 (5 bit)
NVIC_MPU_BASE1_ADDR : Base Address Mask
bits : 5 - 36 (32 bit)
MPU Region Attribute and Size Alias 1
address_offset : 0xDA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_ATTR1_ENABLE : Region Enable
bits : 0 - 0 (1 bit)
NVIC_MPU_ATTR1_SIZE : Region Size Mask
bits : 1 - 6 (6 bit)
NVIC_MPU_ATTR1_SRD : Subregion Disable Bits
bits : 8 - 23 (16 bit)
NVIC_MPU_ATTR1_BUFFRABLE : Bufferable
bits : 16 - 32 (17 bit)
NVIC_MPU_ATTR1_CACHEABLE : Cacheable
bits : 17 - 34 (18 bit)
NVIC_MPU_ATTR1_SHAREABLE : Shareable
bits : 18 - 36 (19 bit)
NVIC_MPU_ATTR1_TEX : Type Extension Mask
bits : 19 - 40 (22 bit)
NVIC_MPU_ATTR1_AP : Access Privilege
bits : 24 - 50 (27 bit)
NVIC_MPU_ATTR1_XN : Instruction Access Disable
bits : 28 - 56 (29 bit)
MPU Region Attribute and Size Alias 1
address_offset : 0xDA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_ATTR1_ENABLE : Region Enable
bits : 0 - 0 (1 bit)
NVIC_MPU_ATTR1_SIZE : Region Size Mask
bits : 1 - 6 (6 bit)
NVIC_MPU_ATTR1_SRD : Subregion Disable Bits
bits : 8 - 23 (16 bit)
NVIC_MPU_ATTR1_BUFFRABLE : Bufferable
bits : 16 - 32 (17 bit)
NVIC_MPU_ATTR1_CACHEABLE : Cacheable
bits : 17 - 34 (18 bit)
NVIC_MPU_ATTR1_SHAREABLE : Shareable
bits : 18 - 36 (19 bit)
NVIC_MPU_ATTR1_TEX : Type Extension Mask
bits : 19 - 40 (22 bit)
NVIC_MPU_ATTR1_AP : Access Privilege
bits : 24 - 50 (27 bit)
NVIC_MPU_ATTR1_XN : Instruction Access Disable
bits : 28 - 56 (29 bit)
MPU Region Base Address Alias 2
address_offset : 0xDAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_BASE2_REGION : Region Number
bits : 0 - 2 (3 bit)
NVIC_MPU_BASE2_VALID : Region Number Valid
bits : 4 - 8 (5 bit)
NVIC_MPU_BASE2_ADDR : Base Address Mask
bits : 5 - 36 (32 bit)
MPU Region Base Address Alias 2
address_offset : 0xDAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_BASE2_REGION : Region Number
bits : 0 - 2 (3 bit)
NVIC_MPU_BASE2_VALID : Region Number Valid
bits : 4 - 8 (5 bit)
NVIC_MPU_BASE2_ADDR : Base Address Mask
bits : 5 - 36 (32 bit)
MPU Region Attribute and Size Alias 2
address_offset : 0xDB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_ATTR2_ENABLE : Region Enable
bits : 0 - 0 (1 bit)
NVIC_MPU_ATTR2_SIZE : Region Size Mask
bits : 1 - 6 (6 bit)
NVIC_MPU_ATTR2_SRD : Subregion Disable Bits
bits : 8 - 23 (16 bit)
NVIC_MPU_ATTR2_BUFFRABLE : Bufferable
bits : 16 - 32 (17 bit)
NVIC_MPU_ATTR2_CACHEABLE : Cacheable
bits : 17 - 34 (18 bit)
NVIC_MPU_ATTR2_SHAREABLE : Shareable
bits : 18 - 36 (19 bit)
NVIC_MPU_ATTR2_TEX : Type Extension Mask
bits : 19 - 40 (22 bit)
NVIC_MPU_ATTR2_AP : Access Privilege
bits : 24 - 50 (27 bit)
NVIC_MPU_ATTR2_XN : Instruction Access Disable
bits : 28 - 56 (29 bit)
MPU Region Attribute and Size Alias 2
address_offset : 0xDB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_ATTR2_ENABLE : Region Enable
bits : 0 - 0 (1 bit)
NVIC_MPU_ATTR2_SIZE : Region Size Mask
bits : 1 - 6 (6 bit)
NVIC_MPU_ATTR2_SRD : Subregion Disable Bits
bits : 8 - 23 (16 bit)
NVIC_MPU_ATTR2_BUFFRABLE : Bufferable
bits : 16 - 32 (17 bit)
NVIC_MPU_ATTR2_CACHEABLE : Cacheable
bits : 17 - 34 (18 bit)
NVIC_MPU_ATTR2_SHAREABLE : Shareable
bits : 18 - 36 (19 bit)
NVIC_MPU_ATTR2_TEX : Type Extension Mask
bits : 19 - 40 (22 bit)
NVIC_MPU_ATTR2_AP : Access Privilege
bits : 24 - 50 (27 bit)
NVIC_MPU_ATTR2_XN : Instruction Access Disable
bits : 28 - 56 (29 bit)
MPU Region Base Address Alias 3
address_offset : 0xDB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_BASE3_REGION : Region Number
bits : 0 - 2 (3 bit)
NVIC_MPU_BASE3_VALID : Region Number Valid
bits : 4 - 8 (5 bit)
NVIC_MPU_BASE3_ADDR : Base Address Mask
bits : 5 - 36 (32 bit)
MPU Region Base Address Alias 3
address_offset : 0xDB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_BASE3_REGION : Region Number
bits : 0 - 2 (3 bit)
NVIC_MPU_BASE3_VALID : Region Number Valid
bits : 4 - 8 (5 bit)
NVIC_MPU_BASE3_ADDR : Base Address Mask
bits : 5 - 36 (32 bit)
MPU Region Attribute and Size Alias 3
address_offset : 0xDB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_ATTR3_ENABLE : Region Enable
bits : 0 - 0 (1 bit)
NVIC_MPU_ATTR3_SIZE : Region Size Mask
bits : 1 - 6 (6 bit)
NVIC_MPU_ATTR3_SRD : Subregion Disable Bits
bits : 8 - 23 (16 bit)
NVIC_MPU_ATTR3_BUFFRABLE : Bufferable
bits : 16 - 32 (17 bit)
NVIC_MPU_ATTR3_CACHEABLE : Cacheable
bits : 17 - 34 (18 bit)
NVIC_MPU_ATTR3_SHAREABLE : Shareable
bits : 18 - 36 (19 bit)
NVIC_MPU_ATTR3_TEX : Type Extension Mask
bits : 19 - 40 (22 bit)
NVIC_MPU_ATTR3_AP : Access Privilege
bits : 24 - 50 (27 bit)
NVIC_MPU_ATTR3_XN : Instruction Access Disable
bits : 28 - 56 (29 bit)
MPU Region Attribute and Size Alias 3
address_offset : 0xDB8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_MPU_ATTR3_ENABLE : Region Enable
bits : 0 - 0 (1 bit)
NVIC_MPU_ATTR3_SIZE : Region Size Mask
bits : 1 - 6 (6 bit)
NVIC_MPU_ATTR3_SRD : Subregion Disable Bits
bits : 8 - 23 (16 bit)
NVIC_MPU_ATTR3_BUFFRABLE : Bufferable
bits : 16 - 32 (17 bit)
NVIC_MPU_ATTR3_CACHEABLE : Cacheable
bits : 17 - 34 (18 bit)
NVIC_MPU_ATTR3_SHAREABLE : Shareable
bits : 18 - 36 (19 bit)
NVIC_MPU_ATTR3_TEX : Type Extension Mask
bits : 19 - 40 (22 bit)
NVIC_MPU_ATTR3_AP : Access Privilege
bits : 24 - 50 (27 bit)
NVIC_MPU_ATTR3_XN : Instruction Access Disable
bits : 28 - 56 (29 bit)
Debug Control and Status Reg
address_offset : 0xDF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_DBG_CTRL_C_DEBUGEN : Enable debug
bits : 0 - 0 (1 bit)
NVIC_DBG_CTRL_C_HALT : Halt the core
bits : 1 - 2 (2 bit)
NVIC_DBG_CTRL_C_STEP : Step the core
bits : 2 - 4 (3 bit)
NVIC_DBG_CTRL_C_MASKINT : Mask interrupts when stepping
bits : 3 - 6 (4 bit)
NVIC_DBG_CTRL_C_SNAPSTALL : Breaks a stalled load/store
bits : 5 - 10 (6 bit)
NVIC_DBG_CTRL_S_REGRDY : Register read/write available
bits : 16 - 32 (17 bit)
NVIC_DBG_CTRL_S_HALT : Core status on halt
bits : 17 - 34 (18 bit)
NVIC_DBG_CTRL_S_SLEEP : Core is sleeping
bits : 18 - 36 (19 bit)
NVIC_DBG_CTRL_S_LOCKUP : Core is locked up
bits : 19 - 38 (20 bit)
NVIC_DBG_CTRL_S_RETIRE_ST : Core has executed insruction since last read
bits : 24 - 48 (25 bit)
NVIC_DBG_CTRL_S_RESET_ST : Core has reset since last read
bits : 25 - 50 (26 bit)
Debug Control and Status Reg
address_offset : 0xDF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_DBG_CTRL_C_DEBUGEN : Enable debug
bits : 0 - 0 (1 bit)
NVIC_DBG_CTRL_C_HALT : Halt the core
bits : 1 - 2 (2 bit)
NVIC_DBG_CTRL_C_STEP : Step the core
bits : 2 - 4 (3 bit)
NVIC_DBG_CTRL_C_MASKINT : Mask interrupts when stepping
bits : 3 - 6 (4 bit)
NVIC_DBG_CTRL_C_SNAPSTALL : Breaks a stalled load/store
bits : 5 - 10 (6 bit)
NVIC_DBG_CTRL_S_REGRDY : Register read/write available
bits : 16 - 32 (17 bit)
NVIC_DBG_CTRL_S_HALT : Core status on halt
bits : 17 - 34 (18 bit)
NVIC_DBG_CTRL_S_SLEEP : Core is sleeping
bits : 18 - 36 (19 bit)
NVIC_DBG_CTRL_S_LOCKUP : Core is locked up
bits : 19 - 38 (20 bit)
NVIC_DBG_CTRL_S_RETIRE_ST : Core has executed insruction since last read
bits : 24 - 48 (25 bit)
NVIC_DBG_CTRL_S_RESET_ST : Core has reset since last read
bits : 25 - 50 (26 bit)
Debug Core Reg. Transfer Select
address_offset : 0xDF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_DBG_XFER_REG_SEL : Register
bits : 0 - 4 (5 bit)
Enumeration:
0x0 : NVIC_DBG_XFER_REG_R0
Register R0
0x1 : NVIC_DBG_XFER_REG_R1
Register R1
0x2 : NVIC_DBG_XFER_REG_R2
Register R2
0x3 : NVIC_DBG_XFER_REG_R3
Register R3
0x4 : NVIC_DBG_XFER_REG_R4
Register R4
0x5 : NVIC_DBG_XFER_REG_R5
Register R5
0x6 : NVIC_DBG_XFER_REG_R6
Register R6
0x7 : NVIC_DBG_XFER_REG_R7
Register R7
0x8 : NVIC_DBG_XFER_REG_R8
Register R8
0x9 : NVIC_DBG_XFER_REG_R9
Register R9
0xa : NVIC_DBG_XFER_REG_R10
Register R10
0xb : NVIC_DBG_XFER_REG_R11
Register R11
0xc : NVIC_DBG_XFER_REG_R12
Register R12
0xd : NVIC_DBG_XFER_REG_R13
Register R13
0xe : NVIC_DBG_XFER_REG_R14
Register R14
0xf : NVIC_DBG_XFER_REG_R15
Register R15
0x10 : NVIC_DBG_XFER_REG_FLAGS
xPSR/Flags register
0x11 : NVIC_DBG_XFER_REG_MSP
Main SP
0x12 : NVIC_DBG_XFER_REG_PSP
Process SP
0x13 : NVIC_DBG_XFER_REG_DSP
Deep SP
0x14 : NVIC_DBG_XFER_REG_CFBP
Control/Fault/BasePri/PriMask
End of enumeration elements list.
NVIC_DBG_XFER_REG_WNR : Write or not read
bits : 16 - 32 (17 bit)
Debug Core Reg. Transfer Select
address_offset : 0xDF4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_DBG_XFER_REG_SEL : Register
bits : 0 - 4 (5 bit)
Enumeration:
0x0 : NVIC_DBG_XFER_REG_R0
Register R0
0x1 : NVIC_DBG_XFER_REG_R1
Register R1
0x2 : NVIC_DBG_XFER_REG_R2
Register R2
0x3 : NVIC_DBG_XFER_REG_R3
Register R3
0x4 : NVIC_DBG_XFER_REG_R4
Register R4
0x5 : NVIC_DBG_XFER_REG_R5
Register R5
0x6 : NVIC_DBG_XFER_REG_R6
Register R6
0x7 : NVIC_DBG_XFER_REG_R7
Register R7
0x8 : NVIC_DBG_XFER_REG_R8
Register R8
0x9 : NVIC_DBG_XFER_REG_R9
Register R9
0xa : NVIC_DBG_XFER_REG_R10
Register R10
0xb : NVIC_DBG_XFER_REG_R11
Register R11
0xc : NVIC_DBG_XFER_REG_R12
Register R12
0xd : NVIC_DBG_XFER_REG_R13
Register R13
0xe : NVIC_DBG_XFER_REG_R14
Register R14
0xf : NVIC_DBG_XFER_REG_R15
Register R15
0x10 : NVIC_DBG_XFER_REG_FLAGS
xPSR/Flags register
0x11 : NVIC_DBG_XFER_REG_MSP
Main SP
0x12 : NVIC_DBG_XFER_REG_PSP
Process SP
0x13 : NVIC_DBG_XFER_REG_DSP
Deep SP
0x14 : NVIC_DBG_XFER_REG_CFBP
Control/Fault/BasePri/PriMask
End of enumeration elements list.
NVIC_DBG_XFER_REG_WNR : Write or not read
bits : 16 - 32 (17 bit)
Debug Core Register Data
address_offset : 0xDF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_DBG_DATA : Data temporary cache
bits : 0 - 31 (32 bit)
Debug Core Register Data
address_offset : 0xDF8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_DBG_DATA : Data temporary cache
bits : 0 - 31 (32 bit)
Debug Reset Interrupt Control
address_offset : 0xDFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_DBG_INT_RSTVCATCH : Reset vector catch
bits : 0 - 0 (1 bit)
NVIC_DBG_INT_RSTPENDING : Core reset is pending
bits : 1 - 2 (2 bit)
NVIC_DBG_INT_RSTPENDCLR : Clear pending core reset
bits : 2 - 4 (3 bit)
NVIC_DBG_INT_RESET : Core reset status
bits : 3 - 6 (4 bit)
NVIC_DBG_INT_MMERR : Debug trap on mem manage fault
bits : 4 - 8 (5 bit)
NVIC_DBG_INT_NOCPERR : Debug trap on coprocessor error
bits : 5 - 10 (6 bit)
NVIC_DBG_INT_CHKERR : Debug trap on usage fault check
bits : 6 - 12 (7 bit)
NVIC_DBG_INT_STATERR : Debug trap on usage fault state
bits : 7 - 14 (8 bit)
NVIC_DBG_INT_BUSERR : Debug trap on bus error
bits : 8 - 16 (9 bit)
NVIC_DBG_INT_INTERR : Debug trap on interrupt errors
bits : 9 - 18 (10 bit)
NVIC_DBG_INT_HARDERR : Debug trap on hard fault
bits : 10 - 20 (11 bit)
Debug Reset Interrupt Control
address_offset : 0xDFC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVIC_DBG_INT_RSTVCATCH : Reset vector catch
bits : 0 - 0 (1 bit)
NVIC_DBG_INT_RSTPENDING : Core reset is pending
bits : 1 - 2 (2 bit)
NVIC_DBG_INT_RSTPENDCLR : Clear pending core reset
bits : 2 - 4 (3 bit)
NVIC_DBG_INT_RESET : Core reset status
bits : 3 - 6 (4 bit)
NVIC_DBG_INT_MMERR : Debug trap on mem manage fault
bits : 4 - 8 (5 bit)
NVIC_DBG_INT_NOCPERR : Debug trap on coprocessor error
bits : 5 - 10 (6 bit)
NVIC_DBG_INT_CHKERR : Debug trap on usage fault check
bits : 6 - 12 (7 bit)
NVIC_DBG_INT_STATERR : Debug trap on usage fault state
bits : 7 - 14 (8 bit)
NVIC_DBG_INT_BUSERR : Debug trap on bus error
bits : 8 - 16 (9 bit)
NVIC_DBG_INT_INTERR : Debug trap on interrupt errors
bits : 9 - 18 (10 bit)
NVIC_DBG_INT_HARDERR : Debug trap on hard fault
bits : 10 - 20 (11 bit)
Software Trigger Interrupt
address_offset : 0xF00 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
NVIC_SW_TRIG_INTID : Interrupt ID
bits : 0 - 5 (6 bit)
access : write-only
Software Trigger Interrupt
address_offset : 0xF00 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
NVIC_SW_TRIG_INTID : Interrupt ID
bits : 0 - 5 (6 bit)
access : write-only
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