\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
PWM Master Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_CTL_GLOBALSYNC0 : Update PWM Generator 0
bits : 0 - 0 (1 bit)
PWM_CTL_GLOBALSYNC1 : Update PWM Generator 1
bits : 1 - 2 (2 bit)
PWM_CTL_GLOBALSYNC2 : Update PWM Generator 2
bits : 2 - 4 (3 bit)
PWM Master Control
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_CTL_GLOBALSYNC0 : Update PWM Generator 0
bits : 0 - 0 (1 bit)
PWM_CTL_GLOBALSYNC1 : Update PWM Generator 1
bits : 1 - 2 (2 bit)
PWM_CTL_GLOBALSYNC2 : Update PWM Generator 2
bits : 2 - 4 (3 bit)
PWM Output Fault
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_FAULT_FAULT0 : PWM0 Fault
bits : 0 - 0 (1 bit)
PWM_FAULT_FAULT1 : PWM1 Fault
bits : 1 - 2 (2 bit)
PWM_FAULT_FAULT2 : PWM2 Fault
bits : 2 - 4 (3 bit)
PWM_FAULT_FAULT3 : PWM3 Fault
bits : 3 - 6 (4 bit)
PWM_FAULT_FAULT4 : PWM4 Fault
bits : 4 - 8 (5 bit)
PWM_FAULT_FAULT5 : PWM5 Fault
bits : 5 - 10 (6 bit)
PWM Output Fault
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_FAULT_FAULT0 : PWM0 Fault
bits : 0 - 0 (1 bit)
PWM_FAULT_FAULT1 : PWM1 Fault
bits : 1 - 2 (2 bit)
PWM_FAULT_FAULT2 : PWM2 Fault
bits : 2 - 4 (3 bit)
PWM_FAULT_FAULT3 : PWM3 Fault
bits : 3 - 6 (4 bit)
PWM_FAULT_FAULT4 : PWM4 Fault
bits : 4 - 8 (5 bit)
PWM_FAULT_FAULT5 : PWM5 Fault
bits : 5 - 10 (6 bit)
PWM Interrupt Enable
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_INTEN_INTPWM0 : PWM0 Interrupt Enable
bits : 0 - 0 (1 bit)
PWM_INTEN_INTPWM1 : PWM1 Interrupt Enable
bits : 1 - 2 (2 bit)
PWM_INTEN_INTPWM2 : PWM2 Interrupt Enable
bits : 2 - 4 (3 bit)
PWM_INTEN_INTFAULT : Fault Interrupt Enable
bits : 16 - 32 (17 bit)
PWM Interrupt Enable
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_INTEN_INTPWM0 : PWM0 Interrupt Enable
bits : 0 - 0 (1 bit)
PWM_INTEN_INTPWM1 : PWM1 Interrupt Enable
bits : 1 - 2 (2 bit)
PWM_INTEN_INTPWM2 : PWM2 Interrupt Enable
bits : 2 - 4 (3 bit)
PWM_INTEN_INTFAULT : Fault Interrupt Enable
bits : 16 - 32 (17 bit)
PWM Raw Interrupt Status
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_RIS_INTPWM0 : PWM0 Interrupt Asserted
bits : 0 - 0 (1 bit)
PWM_RIS_INTPWM1 : PWM1 Interrupt Asserted
bits : 1 - 2 (2 bit)
PWM_RIS_INTPWM2 : PWM2 Interrupt Asserted
bits : 2 - 4 (3 bit)
PWM_RIS_INTFAULT : Fault Interrupt Asserted
bits : 16 - 32 (17 bit)
PWM Raw Interrupt Status
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_RIS_INTPWM0 : PWM0 Interrupt Asserted
bits : 0 - 0 (1 bit)
PWM_RIS_INTPWM1 : PWM1 Interrupt Asserted
bits : 1 - 2 (2 bit)
PWM_RIS_INTPWM2 : PWM2 Interrupt Asserted
bits : 2 - 4 (3 bit)
PWM_RIS_INTFAULT : Fault Interrupt Asserted
bits : 16 - 32 (17 bit)
PWM Interrupt Status and Clear
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_ISC_INTPWM0 : PWM0 Interrupt Status
bits : 0 - 0 (1 bit)
PWM_ISC_INTPWM1 : PWM1 Interrupt Status
bits : 1 - 2 (2 bit)
PWM_ISC_INTPWM2 : PWM2 Interrupt Status
bits : 2 - 4 (3 bit)
PWM_ISC_INTFAULT : Fault Interrupt Asserted
bits : 16 - 32 (17 bit)
PWM Interrupt Status and Clear
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_ISC_INTPWM0 : PWM0 Interrupt Status
bits : 0 - 0 (1 bit)
PWM_ISC_INTPWM1 : PWM1 Interrupt Status
bits : 1 - 2 (2 bit)
PWM_ISC_INTPWM2 : PWM2 Interrupt Status
bits : 2 - 4 (3 bit)
PWM_ISC_INTFAULT : Fault Interrupt Asserted
bits : 16 - 32 (17 bit)
PWM Status
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Status
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Time Base Sync
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_SYNC_SYNC0 : Reset Generator 0 Counter
bits : 0 - 0 (1 bit)
PWM_SYNC_SYNC1 : Reset Generator 1 Counter
bits : 1 - 2 (2 bit)
PWM_SYNC_SYNC2 : Reset Generator 2 Counter
bits : 2 - 4 (3 bit)
PWM Time Base Sync
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_SYNC_SYNC0 : Reset Generator 0 Counter
bits : 0 - 0 (1 bit)
PWM_SYNC_SYNC1 : Reset Generator 1 Counter
bits : 1 - 2 (2 bit)
PWM_SYNC_SYNC2 : Reset Generator 2 Counter
bits : 2 - 4 (3 bit)
PWM0 Control
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_CTL_ENABLE : PWM Block Enable
bits : 0 - 0 (1 bit)
PWM_X_CTL_MODE : Counter Mode
bits : 1 - 2 (2 bit)
PWM_X_CTL_DEBUG : Debug Mode
bits : 2 - 4 (3 bit)
PWM_X_CTL_LOADUPD : Load Register Update Mode
bits : 3 - 6 (4 bit)
PWM_X_CTL_CMPAUPD : Comparator A Update Mode
bits : 4 - 8 (5 bit)
PWM_X_CTL_CMPBUPD : Comparator B Update Mode
bits : 5 - 10 (6 bit)
PWM0 Control
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_CTL_ENABLE : PWM Block Enable
bits : 0 - 0 (1 bit)
PWM_X_CTL_MODE : Counter Mode
bits : 1 - 2 (2 bit)
PWM_X_CTL_DEBUG : Debug Mode
bits : 2 - 4 (3 bit)
PWM_X_CTL_LOADUPD : Load Register Update Mode
bits : 3 - 6 (4 bit)
PWM_X_CTL_CMPAUPD : Comparator A Update Mode
bits : 4 - 8 (5 bit)
PWM_X_CTL_CMPBUPD : Comparator B Update Mode
bits : 5 - 10 (6 bit)
PWM0 Interrupt and Trigger Enable
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_INTEN_INTCNTZERO : Interrupt for Counter=0
bits : 0 - 0 (1 bit)
PWM_X_INTEN_INTCNTLOAD : Interrupt for Counter=PWMnLOAD
bits : 1 - 2 (2 bit)
PWM_X_INTEN_INTCMPAU : Interrupt for Counter=PWMnCMPA Up
bits : 2 - 4 (3 bit)
PWM_X_INTEN_INTCMPAD : Interrupt for Counter=PWMnCMPA Down
bits : 3 - 6 (4 bit)
PWM_X_INTEN_INTCMPBU : Interrupt for Counter=PWMnCMPB Up
bits : 4 - 8 (5 bit)
PWM_X_INTEN_INTCMPBD : Interrupt for Counter=PWMnCMPB Down
bits : 5 - 10 (6 bit)
PWM0 Interrupt and Trigger Enable
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_INTEN_INTCNTZERO : Interrupt for Counter=0
bits : 0 - 0 (1 bit)
PWM_X_INTEN_INTCNTLOAD : Interrupt for Counter=PWMnLOAD
bits : 1 - 2 (2 bit)
PWM_X_INTEN_INTCMPAU : Interrupt for Counter=PWMnCMPA Up
bits : 2 - 4 (3 bit)
PWM_X_INTEN_INTCMPAD : Interrupt for Counter=PWMnCMPA Down
bits : 3 - 6 (4 bit)
PWM_X_INTEN_INTCMPBU : Interrupt for Counter=PWMnCMPB Up
bits : 4 - 8 (5 bit)
PWM_X_INTEN_INTCMPBD : Interrupt for Counter=PWMnCMPB Down
bits : 5 - 10 (6 bit)
PWM0 Raw Interrupt Status
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_RIS_INTCNTZERO : Counter=0 Interrupt Status
bits : 0 - 0 (1 bit)
PWM_X_RIS_INTCNTLOAD : Counter=Load Interrupt Status
bits : 1 - 2 (2 bit)
PWM_X_RIS_INTCMPAU : Comparator A Up Interrupt Status
bits : 2 - 4 (3 bit)
PWM_X_RIS_INTCMPAD : Comparator A Down Interrupt Status
bits : 3 - 6 (4 bit)
PWM_X_RIS_INTCMPBU : Comparator B Up Interrupt Status
bits : 4 - 8 (5 bit)
PWM_X_RIS_INTCMPBD : Comparator B Down Interrupt Status
bits : 5 - 10 (6 bit)
PWM0 Raw Interrupt Status
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_RIS_INTCNTZERO : Counter=0 Interrupt Status
bits : 0 - 0 (1 bit)
PWM_X_RIS_INTCNTLOAD : Counter=Load Interrupt Status
bits : 1 - 2 (2 bit)
PWM_X_RIS_INTCMPAU : Comparator A Up Interrupt Status
bits : 2 - 4 (3 bit)
PWM_X_RIS_INTCMPAD : Comparator A Down Interrupt Status
bits : 3 - 6 (4 bit)
PWM_X_RIS_INTCMPBU : Comparator B Up Interrupt Status
bits : 4 - 8 (5 bit)
PWM_X_RIS_INTCMPBD : Comparator B Down Interrupt Status
bits : 5 - 10 (6 bit)
PWM0 Interrupt Status and Clear
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_ISC_INTCNTZERO : Counter=0 Interrupt
bits : 0 - 0 (1 bit)
PWM_X_ISC_INTCNTLOAD : Counter=Load Interrupt
bits : 1 - 2 (2 bit)
PWM_X_ISC_INTCMPAU : Comparator A Up Interrupt
bits : 2 - 4 (3 bit)
PWM_X_ISC_INTCMPAD : Comparator A Down Interrupt
bits : 3 - 6 (4 bit)
PWM_X_ISC_INTCMPBU : Comparator B Up Interrupt
bits : 4 - 8 (5 bit)
PWM_X_ISC_INTCMPBD : Comparator B Down Interrupt
bits : 5 - 10 (6 bit)
PWM0 Interrupt Status and Clear
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_ISC_INTCNTZERO : Counter=0 Interrupt
bits : 0 - 0 (1 bit)
PWM_X_ISC_INTCNTLOAD : Counter=Load Interrupt
bits : 1 - 2 (2 bit)
PWM_X_ISC_INTCMPAU : Comparator A Up Interrupt
bits : 2 - 4 (3 bit)
PWM_X_ISC_INTCMPAD : Comparator A Down Interrupt
bits : 3 - 6 (4 bit)
PWM_X_ISC_INTCMPBU : Comparator B Up Interrupt
bits : 4 - 8 (5 bit)
PWM_X_ISC_INTCMPBD : Comparator B Down Interrupt
bits : 5 - 10 (6 bit)
PWM0 Load
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_LOAD : Counter Load Value
bits : 0 - 15 (16 bit)
PWM0 Load
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_LOAD : Counter Load Value
bits : 0 - 15 (16 bit)
PWM0 Counter
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_COUNT : Counter Value
bits : 0 - 15 (16 bit)
PWM0 Counter
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_COUNT : Counter Value
bits : 0 - 15 (16 bit)
PWM0 Compare A
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_CMPA : Comparator A Value
bits : 0 - 15 (16 bit)
PWM0 Compare A
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_CMPA : Comparator A Value
bits : 0 - 15 (16 bit)
PWM0 Compare B
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_CMPB : Comparator B Value
bits : 0 - 15 (16 bit)
PWM0 Compare B
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_CMPB : Comparator B Value
bits : 0 - 15 (16 bit)
PWM0 Generator A Control
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_GENA_ACTZERO : Action for Counter=0
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTZERO_NONE
Do nothing
0x1 : PWM_X_GENA_ACTZERO_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTZERO_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTZERO_ONE
Drive pwmA High
End of enumeration elements list.
PWM_X_GENA_ACTLOAD : Action for Counter=LOAD
bits : 2 - 5 (4 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTLOAD_NONE
Do nothing
0x1 : PWM_X_GENA_ACTLOAD_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTLOAD_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTLOAD_ONE
Drive pwmA High
End of enumeration elements list.
PWM_X_GENA_ACTCMPAU : Action for Comparator A Up
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTCMPAU_NONE
Do nothing
0x1 : PWM_X_GENA_ACTCMPAU_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTCMPAU_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTCMPAU_ONE
Drive pwmA High
End of enumeration elements list.
PWM_X_GENA_ACTCMPAD : Action for Comparator A Down
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTCMPAD_NONE
Do nothing
0x1 : PWM_X_GENA_ACTCMPAD_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTCMPAD_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTCMPAD_ONE
Drive pwmA High
End of enumeration elements list.
PWM_X_GENA_ACTCMPBU : Action for Comparator B Up
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTCMPBU_NONE
Do nothing
0x1 : PWM_X_GENA_ACTCMPBU_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTCMPBU_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTCMPBU_ONE
Drive pwmA High
End of enumeration elements list.
PWM_X_GENA_ACTCMPBD : Action for Comparator B Down
bits : 10 - 21 (12 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTCMPBD_NONE
Do nothing
0x1 : PWM_X_GENA_ACTCMPBD_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTCMPBD_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTCMPBD_ONE
Drive pwmA High
End of enumeration elements list.
PWM0 Generator A Control
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_GENA_ACTZERO : Action for Counter=0
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTZERO_NONE
Do nothing
0x1 : PWM_X_GENA_ACTZERO_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTZERO_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTZERO_ONE
Drive pwmA High
End of enumeration elements list.
PWM_X_GENA_ACTLOAD : Action for Counter=LOAD
bits : 2 - 5 (4 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTLOAD_NONE
Do nothing
0x1 : PWM_X_GENA_ACTLOAD_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTLOAD_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTLOAD_ONE
Drive pwmA High
End of enumeration elements list.
PWM_X_GENA_ACTCMPAU : Action for Comparator A Up
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTCMPAU_NONE
Do nothing
0x1 : PWM_X_GENA_ACTCMPAU_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTCMPAU_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTCMPAU_ONE
Drive pwmA High
End of enumeration elements list.
PWM_X_GENA_ACTCMPAD : Action for Comparator A Down
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTCMPAD_NONE
Do nothing
0x1 : PWM_X_GENA_ACTCMPAD_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTCMPAD_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTCMPAD_ONE
Drive pwmA High
End of enumeration elements list.
PWM_X_GENA_ACTCMPBU : Action for Comparator B Up
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTCMPBU_NONE
Do nothing
0x1 : PWM_X_GENA_ACTCMPBU_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTCMPBU_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTCMPBU_ONE
Drive pwmA High
End of enumeration elements list.
PWM_X_GENA_ACTCMPBD : Action for Comparator B Down
bits : 10 - 21 (12 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTCMPBD_NONE
Do nothing
0x1 : PWM_X_GENA_ACTCMPBD_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTCMPBD_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTCMPBD_ONE
Drive pwmA High
End of enumeration elements list.
PWM0 Generator B Control
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_GENB_ACTZERO : Action for Counter=0
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTZERO_NONE
Do nothing
0x1 : PWM_X_GENB_ACTZERO_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTZERO_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTZERO_ONE
Drive pwmB High
End of enumeration elements list.
PWM_X_GENB_ACTLOAD : Action for Counter=LOAD
bits : 2 - 5 (4 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTLOAD_NONE
Do nothing
0x1 : PWM_X_GENB_ACTLOAD_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTLOAD_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTLOAD_ONE
Drive pwmB High
End of enumeration elements list.
PWM_X_GENB_ACTCMPAU : Action for Comparator A Up
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTCMPAU_NONE
Do nothing
0x1 : PWM_X_GENB_ACTCMPAU_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTCMPAU_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTCMPAU_ONE
Drive pwmB High
End of enumeration elements list.
PWM_X_GENB_ACTCMPAD : Action for Comparator A Down
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTCMPAD_NONE
Do nothing
0x1 : PWM_X_GENB_ACTCMPAD_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTCMPAD_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTCMPAD_ONE
Drive pwmB High
End of enumeration elements list.
PWM_X_GENB_ACTCMPBU : Action for Comparator B Up
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTCMPBU_NONE
Do nothing
0x1 : PWM_X_GENB_ACTCMPBU_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTCMPBU_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTCMPBU_ONE
Drive pwmB High
End of enumeration elements list.
PWM_X_GENB_ACTCMPBD : Action for Comparator B Down
bits : 10 - 21 (12 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTCMPBD_NONE
Do nothing
0x1 : PWM_X_GENB_ACTCMPBD_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTCMPBD_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTCMPBD_ONE
Drive pwmB High
End of enumeration elements list.
PWM0 Generator B Control
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_GENB_ACTZERO : Action for Counter=0
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTZERO_NONE
Do nothing
0x1 : PWM_X_GENB_ACTZERO_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTZERO_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTZERO_ONE
Drive pwmB High
End of enumeration elements list.
PWM_X_GENB_ACTLOAD : Action for Counter=LOAD
bits : 2 - 5 (4 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTLOAD_NONE
Do nothing
0x1 : PWM_X_GENB_ACTLOAD_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTLOAD_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTLOAD_ONE
Drive pwmB High
End of enumeration elements list.
PWM_X_GENB_ACTCMPAU : Action for Comparator A Up
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTCMPAU_NONE
Do nothing
0x1 : PWM_X_GENB_ACTCMPAU_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTCMPAU_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTCMPAU_ONE
Drive pwmB High
End of enumeration elements list.
PWM_X_GENB_ACTCMPAD : Action for Comparator A Down
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTCMPAD_NONE
Do nothing
0x1 : PWM_X_GENB_ACTCMPAD_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTCMPAD_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTCMPAD_ONE
Drive pwmB High
End of enumeration elements list.
PWM_X_GENB_ACTCMPBU : Action for Comparator B Up
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTCMPBU_NONE
Do nothing
0x1 : PWM_X_GENB_ACTCMPBU_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTCMPBU_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTCMPBU_ONE
Drive pwmB High
End of enumeration elements list.
PWM_X_GENB_ACTCMPBD : Action for Comparator B Down
bits : 10 - 21 (12 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTCMPBD_NONE
Do nothing
0x1 : PWM_X_GENB_ACTCMPBD_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTCMPBD_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTCMPBD_ONE
Drive pwmB High
End of enumeration elements list.
PWM0 Dead-Band Control
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_DBCTL_ENABLE : Dead-Band Generator Enable
bits : 0 - 0 (1 bit)
PWM0 Dead-Band Control
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_DBCTL_ENABLE : Dead-Band Generator Enable
bits : 0 - 0 (1 bit)
PWM0 Dead-Band Rising-Edge Delay
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_DBRISE_DELAY : Dead-Band Rise Delay
bits : 0 - 11 (12 bit)
PWM0 Dead-Band Rising-Edge Delay
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_DBRISE_DELAY : Dead-Band Rise Delay
bits : 0 - 11 (12 bit)
PWM0 Dead-Band Falling-Edge-Delay
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_DBFALL_DELAY : Dead-Band Fall Delay
bits : 0 - 11 (12 bit)
PWM0 Dead-Band Falling-Edge-Delay
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_DBFALL_DELAY : Dead-Band Fall Delay
bits : 0 - 11 (12 bit)
PWM Output Enable
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_ENABLE_PWM0EN : PWM0 Output Enable
bits : 0 - 0 (1 bit)
PWM_ENABLE_PWM1EN : PWM1 Output Enable
bits : 1 - 2 (2 bit)
PWM_ENABLE_PWM2EN : PWM2 Output Enable
bits : 2 - 4 (3 bit)
PWM_ENABLE_PWM3EN : PWM3 Output Enable
bits : 3 - 6 (4 bit)
PWM_ENABLE_PWM4EN : PWM4 Output Enable
bits : 4 - 8 (5 bit)
PWM_ENABLE_PWM5EN : PWM5 Output Enable
bits : 5 - 10 (6 bit)
PWM Output Enable
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_ENABLE_PWM0EN : PWM0 Output Enable
bits : 0 - 0 (1 bit)
PWM_ENABLE_PWM1EN : PWM1 Output Enable
bits : 1 - 2 (2 bit)
PWM_ENABLE_PWM2EN : PWM2 Output Enable
bits : 2 - 4 (3 bit)
PWM_ENABLE_PWM3EN : PWM3 Output Enable
bits : 3 - 6 (4 bit)
PWM_ENABLE_PWM4EN : PWM4 Output Enable
bits : 4 - 8 (5 bit)
PWM_ENABLE_PWM5EN : PWM5 Output Enable
bits : 5 - 10 (6 bit)
PWM1 Control
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Control
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Interrupt and Trigger Enable
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Interrupt and Trigger Enable
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Raw Interrupt Status
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Raw Interrupt Status
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Interrupt Status and Clear
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Interrupt Status and Clear
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Load
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Load
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Counter
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Counter
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Compare A
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Compare A
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Compare B
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Compare B
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Generator A Control
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Generator A Control
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Generator B Control
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Generator B Control
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Dead-Band Control
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Dead-Band Control
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Dead-Band Rising-Edge Delay
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Dead-Band Rising-Edge Delay
address_offset : 0xAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Dead-Band Falling-Edge-Delay
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Dead-Band Falling-Edge-Delay
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Output Inversion
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_INVERT_PWM0INV : Invert PWM0 Signal
bits : 0 - 0 (1 bit)
PWM_INVERT_PWM1INV : Invert PWM1 Signal
bits : 1 - 2 (2 bit)
PWM_INVERT_PWM2INV : Invert PWM2 Signal
bits : 2 - 4 (3 bit)
PWM_INVERT_PWM3INV : Invert PWM3 Signal
bits : 3 - 6 (4 bit)
PWM_INVERT_PWM4INV : Invert PWM4 Signal
bits : 4 - 8 (5 bit)
PWM_INVERT_PWM5INV : Invert PWM5 Signal
bits : 5 - 10 (6 bit)
PWM Output Inversion
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_INVERT_PWM0INV : Invert PWM0 Signal
bits : 0 - 0 (1 bit)
PWM_INVERT_PWM1INV : Invert PWM1 Signal
bits : 1 - 2 (2 bit)
PWM_INVERT_PWM2INV : Invert PWM2 Signal
bits : 2 - 4 (3 bit)
PWM_INVERT_PWM3INV : Invert PWM3 Signal
bits : 3 - 6 (4 bit)
PWM_INVERT_PWM4INV : Invert PWM4 Signal
bits : 4 - 8 (5 bit)
PWM_INVERT_PWM5INV : Invert PWM5 Signal
bits : 5 - 10 (6 bit)
PWM2 Control
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Control
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Interrupt and Trigger Enable
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Interrupt and Trigger Enable
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Raw Interrupt Status
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Raw Interrupt Status
address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Interrupt Status and Clear
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Interrupt Status and Clear
address_offset : 0xCC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Load
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Load
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Counter
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Counter
address_offset : 0xD4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Compare A
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Compare A
address_offset : 0xD8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Compare B
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Compare B
address_offset : 0xDC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Generator A Control
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Generator A Control
address_offset : 0xE0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Generator B Control
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Generator B Control
address_offset : 0xE4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Dead-Band Control
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Dead-Band Control
address_offset : 0xE8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Dead-Band Rising-Edge Delay
address_offset : 0xEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Dead-Band Rising-Edge Delay
address_offset : 0xEC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Dead-Band Falling-Edge-Delay
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Dead-Band Falling-Edge-Delay
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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