\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Ethernet MAC Raw Interrupt Status/Acknowledge
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_RIS_RXINT : Packet Received
bits : 0 - 0 (1 bit)
MAC_RIS_TXER : Transmit Error
bits : 1 - 2 (2 bit)
MAC_RIS_TXEMP : Transmit FIFO Empty
bits : 2 - 4 (3 bit)
MAC_RIS_FOV : FIFO Overrun
bits : 3 - 6 (4 bit)
MAC_RIS_RXER : Receive Error
bits : 4 - 8 (5 bit)
MAC_RIS_MDINT : MII Transaction Complete
bits : 5 - 10 (6 bit)
MAC_RIS_PHYINT : PHY Interrupt
bits : 6 - 12 (7 bit)
Ethernet MAC Raw Interrupt Status/Acknowledge
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : MAC_ALT
reset_Mask : 0x0
MAC_IACK_RXINT : Clear Packet Received
bits : 0 - 0 (1 bit)
MAC_IACK_TXER : Clear Transmit Error
bits : 1 - 2 (2 bit)
MAC_IACK_TXEMP : Clear Transmit FIFO Empty
bits : 2 - 4 (3 bit)
MAC_IACK_FOV : Clear FIFO Overrun
bits : 3 - 6 (4 bit)
MAC_IACK_RXER : Clear Receive Error
bits : 4 - 8 (5 bit)
MAC_IACK_MDINT : Clear MII Transaction Complete
bits : 5 - 10 (6 bit)
MAC_IACK_PHYINT : Clear PHY Interrupt
bits : 6 - 12 (7 bit)
Ethernet MAC Raw Interrupt Status/Acknowledge
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_RIS_RXINT : Packet Received
bits : 0 - 0 (1 bit)
MAC_RIS_TXER : Transmit Error
bits : 1 - 2 (2 bit)
MAC_RIS_TXEMP : Transmit FIFO Empty
bits : 2 - 4 (3 bit)
MAC_RIS_FOV : FIFO Overrun
bits : 3 - 6 (4 bit)
MAC_RIS_RXER : Receive Error
bits : 4 - 8 (5 bit)
MAC_RIS_MDINT : MII Transaction Complete
bits : 5 - 10 (6 bit)
MAC_RIS_PHYINT : PHY Interrupt
bits : 6 - 12 (7 bit)
Ethernet MAC Raw Interrupt Status/Acknowledge
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_IACK_RXINT : Clear Packet Received
bits : 0 - 0 (1 bit)
MAC_IACK_TXER : Clear Transmit Error
bits : 1 - 2 (2 bit)
MAC_IACK_TXEMP : Clear Transmit FIFO Empty
bits : 2 - 4 (3 bit)
MAC_IACK_FOV : Clear FIFO Overrun
bits : 3 - 6 (4 bit)
MAC_IACK_RXER : Clear Receive Error
bits : 4 - 8 (5 bit)
MAC_IACK_MDINT : Clear MII Transaction Complete
bits : 5 - 10 (6 bit)
MAC_IACK_PHYINT : Clear PHY Interrupt
bits : 6 - 12 (7 bit)
Ethernet MAC Data
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_DATA_RXDATA : Receive FIFO Data
bits : 0 - 31 (32 bit)
Ethernet MAC Data
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_DATA_RXDATA : Receive FIFO Data
bits : 0 - 31 (32 bit)
MAC_DATA_TXDATA : Transmit FIFO Data
bits : 0 - 31 (32 bit)
Ethernet MAC Individual Address 0
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_IA0_MACOCT1 : MAC Address Octet 1
bits : 0 - 7 (8 bit)
MAC_IA0_MACOCT2 : MAC Address Octet 2
bits : 8 - 23 (16 bit)
MAC_IA0_MACOCT3 : MAC Address Octet 3
bits : 16 - 39 (24 bit)
MAC_IA0_MACOCT4 : MAC Address Octet 4
bits : 24 - 55 (32 bit)
Ethernet MAC Individual Address 0
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_IA0_MACOCT1 : MAC Address Octet 1
bits : 0 - 7 (8 bit)
MAC_IA0_MACOCT2 : MAC Address Octet 2
bits : 8 - 23 (16 bit)
MAC_IA0_MACOCT3 : MAC Address Octet 3
bits : 16 - 39 (24 bit)
MAC_IA0_MACOCT4 : MAC Address Octet 4
bits : 24 - 55 (32 bit)
Ethernet MAC Individual Address 1
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_IA1_MACOCT5 : MAC Address Octet 5
bits : 0 - 7 (8 bit)
MAC_IA1_MACOCT6 : MAC Address Octet 6
bits : 8 - 23 (16 bit)
Ethernet MAC Individual Address 1
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_IA1_MACOCT5 : MAC Address Octet 5
bits : 0 - 7 (8 bit)
MAC_IA1_MACOCT6 : MAC Address Octet 6
bits : 8 - 23 (16 bit)
Ethernet MAC Threshold
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_THR_THRESH : Threshold Value
bits : 0 - 5 (6 bit)
Ethernet MAC Threshold
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_THR_THRESH : Threshold Value
bits : 0 - 5 (6 bit)
Ethernet MAC Management Control
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_MCTL_START : MII Register Transaction Enable
bits : 0 - 0 (1 bit)
MAC_MCTL_WRITE : MII Register Transaction Type
bits : 1 - 2 (2 bit)
MAC_MCTL_REGADR : MII Register Address
bits : 3 - 10 (8 bit)
Ethernet MAC Management Control
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_MCTL_START : MII Register Transaction Enable
bits : 0 - 0 (1 bit)
MAC_MCTL_WRITE : MII Register Transaction Type
bits : 1 - 2 (2 bit)
MAC_MCTL_REGADR : MII Register Address
bits : 3 - 10 (8 bit)
Ethernet MAC Management Divider
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_MDV_DIV : Clock Divider
bits : 0 - 7 (8 bit)
Ethernet MAC Management Divider
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_MDV_DIV : Clock Divider
bits : 0 - 7 (8 bit)
Ethernet MAC Management Transmit Data
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_MTXD_MDTX : MII Register Transmit Data
bits : 0 - 15 (16 bit)
Ethernet MAC Management Transmit Data
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_MTXD_MDTX : MII Register Transmit Data
bits : 0 - 15 (16 bit)
Ethernet MAC Management Receive Data
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_MRXD_MDRX : MII Register Receive Data
bits : 0 - 15 (16 bit)
Ethernet MAC Management Receive Data
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_MRXD_MDRX : MII Register Receive Data
bits : 0 - 15 (16 bit)
Ethernet MAC Number of Packets
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_NP_NPR : Number of Packets in Receive FIFO
bits : 0 - 5 (6 bit)
Ethernet MAC Number of Packets
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_NP_NPR : Number of Packets in Receive FIFO
bits : 0 - 5 (6 bit)
Ethernet MAC Transmission Request
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_TR_NEWTX : New Transmission
bits : 0 - 0 (1 bit)
Ethernet MAC Transmission Request
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_TR_NEWTX : New Transmission
bits : 0 - 0 (1 bit)
Ethernet MAC Interrupt Mask
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_IM_RXINTM : Mask Packet Received
bits : 0 - 0 (1 bit)
MAC_IM_TXERM : Mask Transmit Error
bits : 1 - 2 (2 bit)
MAC_IM_TXEMPM : Mask Transmit FIFO Empty
bits : 2 - 4 (3 bit)
MAC_IM_FOVM : Mask FIFO Overrun
bits : 3 - 6 (4 bit)
MAC_IM_RXERM : Mask Receive Error
bits : 4 - 8 (5 bit)
MAC_IM_MDINTM : Mask MII Transaction Complete
bits : 5 - 10 (6 bit)
MAC_IM_PHYINTM : Mask PHY Interrupt
bits : 6 - 12 (7 bit)
Ethernet MAC Interrupt Mask
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_IM_RXINTM : Mask Packet Received
bits : 0 - 0 (1 bit)
MAC_IM_TXERM : Mask Transmit Error
bits : 1 - 2 (2 bit)
MAC_IM_TXEMPM : Mask Transmit FIFO Empty
bits : 2 - 4 (3 bit)
MAC_IM_FOVM : Mask FIFO Overrun
bits : 3 - 6 (4 bit)
MAC_IM_RXERM : Mask Receive Error
bits : 4 - 8 (5 bit)
MAC_IM_MDINTM : Mask MII Transaction Complete
bits : 5 - 10 (6 bit)
MAC_IM_PHYINTM : Mask PHY Interrupt
bits : 6 - 12 (7 bit)
Ethernet MAC Receive Control
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_RCTL_RXEN : Enable Receiver
bits : 0 - 0 (1 bit)
MAC_RCTL_AMUL : Enable Multicast Frames
bits : 1 - 2 (2 bit)
MAC_RCTL_PRMS : Enable Promiscuous Mode
bits : 2 - 4 (3 bit)
MAC_RCTL_BADCRC : Enable Reject Bad CRC
bits : 3 - 6 (4 bit)
MAC_RCTL_RSTFIFO : Clear Receive FIFO
bits : 4 - 8 (5 bit)
Ethernet MAC Receive Control
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_RCTL_RXEN : Enable Receiver
bits : 0 - 0 (1 bit)
MAC_RCTL_AMUL : Enable Multicast Frames
bits : 1 - 2 (2 bit)
MAC_RCTL_PRMS : Enable Promiscuous Mode
bits : 2 - 4 (3 bit)
MAC_RCTL_BADCRC : Enable Reject Bad CRC
bits : 3 - 6 (4 bit)
MAC_RCTL_RSTFIFO : Clear Receive FIFO
bits : 4 - 8 (5 bit)
Ethernet MAC Transmit Control
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_TCTL_TXEN : Enable Transmitter
bits : 0 - 0 (1 bit)
MAC_TCTL_PADEN : Enable Packet Padding
bits : 1 - 2 (2 bit)
MAC_TCTL_CRC : Enable CRC Generation
bits : 2 - 4 (3 bit)
MAC_TCTL_DUPLEX : Enable Duplex Mode
bits : 4 - 8 (5 bit)
Ethernet MAC Transmit Control
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC_TCTL_TXEN : Enable Transmitter
bits : 0 - 0 (1 bit)
MAC_TCTL_PADEN : Enable Packet Padding
bits : 1 - 2 (2 bit)
MAC_TCTL_CRC : Enable CRC Generation
bits : 2 - 4 (3 bit)
MAC_TCTL_DUPLEX : Enable Duplex Mode
bits : 4 - 8 (5 bit)
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