Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Device Identification 0
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DID0_MIN : Minor Revision
bits : 0 - 7 (8 bit)
Enumeration:
0x0 : SYSCTL_DID0_MIN_0
Initial device, or a major revision update
0x1 : SYSCTL_DID0_MIN_1
First metal layer change
0x2 : SYSCTL_DID0_MIN_2
Second metal layer change
End of enumeration elements list.
SYSCTL_DID0_MAJ : Major Revision
bits : 8 - 23 (16 bit)
Enumeration:
0x0 : SYSCTL_DID0_MAJ_REVA
Revision A (initial device)
0x1 : SYSCTL_DID0_MAJ_REVB
Revision B (first base layer revision)
0x2 : SYSCTL_DID0_MAJ_REVC
Revision C (second base layer revision)
End of enumeration elements list.
SYSCTL_DID0_CLASS : Device Class
bits : 16 - 39 (24 bit)
Enumeration:
0x4 : SYSCTL_DID0_CLASS_TEMPEST
Stellaris(R) Tempest-class microcontrollers
End of enumeration elements list.
SYSCTL_DID0_VER : DID0 Version
bits : 28 - 58 (31 bit)
Enumeration:
0x1 : SYSCTL_DID0_VER_1
Second version of the DID0 register format
End of enumeration elements list.
Device Identification 0
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DID0_MIN : Minor Revision
bits : 0 - 7 (8 bit)
Enumeration:
0x0 : SYSCTL_DID0_MIN_0
Initial device, or a major revision update
0x1 : SYSCTL_DID0_MIN_1
First metal layer change
0x2 : SYSCTL_DID0_MIN_2
Second metal layer change
End of enumeration elements list.
SYSCTL_DID0_MAJ : Major Revision
bits : 8 - 23 (16 bit)
Enumeration:
0x0 : SYSCTL_DID0_MAJ_REVA
Revision A (initial device)
0x1 : SYSCTL_DID0_MAJ_REVB
Revision B (first base layer revision)
0x2 : SYSCTL_DID0_MAJ_REVC
Revision C (second base layer revision)
End of enumeration elements list.
SYSCTL_DID0_CLASS : Device Class
bits : 16 - 39 (24 bit)
Enumeration:
0x4 : SYSCTL_DID0_CLASS_TEMPEST
Stellaris(R) Tempest-class microcontrollers
End of enumeration elements list.
SYSCTL_DID0_VER : DID0 Version
bits : 28 - 58 (31 bit)
Enumeration:
0x1 : SYSCTL_DID0_VER_1
Second version of the DID0 register format
End of enumeration elements list.
Device Capabilities 1
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC1_JTAG : JTAG Present
bits : 0 - 0 (1 bit)
SYSCTL_DC1_SWD : SWD Present
bits : 1 - 2 (2 bit)
SYSCTL_DC1_SWO : SWO Trace Port Present
bits : 2 - 4 (3 bit)
SYSCTL_DC1_WDT0 : Watchdog Timer 0 Present
bits : 3 - 6 (4 bit)
SYSCTL_DC1_PLL : PLL Present
bits : 4 - 8 (5 bit)
SYSCTL_DC1_TEMP : Temp Sensor Present
bits : 5 - 10 (6 bit)
SYSCTL_DC1_MPU : MPU Present
bits : 7 - 14 (8 bit)
SYSCTL_DC1_ADC0SPD : Max ADC0 Speed
bits : 8 - 17 (10 bit)
Enumeration:
0x3 : SYSCTL_DC1_ADC0SPD_1M
1M samples/second
End of enumeration elements list.
SYSCTL_DC1_ADC1SPD : Max ADC1 Speed
bits : 10 - 21 (12 bit)
Enumeration:
0x3 : SYSCTL_DC1_ADC1SPD_1M
1M samples/second
End of enumeration elements list.
SYSCTL_DC1_MINSYSDIV : System Clock Divider
bits : 12 - 27 (16 bit)
Enumeration:
0x1 : SYSCTL_DC1_MINSYSDIV_100
Divide VCO (400MHZ) by 5 minimum
0x2 : SYSCTL_DC1_MINSYSDIV_66
Divide VCO (400MHZ) by 2*2 + 2 = 6 minimum
0x3 : SYSCTL_DC1_MINSYSDIV_50
Specifies a 50-MHz CPU clock with a PLL divider of 4
0x7 : SYSCTL_DC1_MINSYSDIV_25
Specifies a 25-MHz clock with a PLL divider of 8
0x9 : SYSCTL_DC1_MINSYSDIV_20
Specifies a 20-MHz clock with a PLL divider of 10
End of enumeration elements list.
SYSCTL_DC1_ADC0 : ADC Module 0 Present
bits : 16 - 32 (17 bit)
SYSCTL_DC1_ADC1 : ADC Module 1 Present
bits : 17 - 34 (18 bit)
SYSCTL_DC1_CAN0 : CAN Module 0 Present
bits : 24 - 48 (25 bit)
SYSCTL_DC1_CAN1 : CAN Module 1 Present
bits : 25 - 50 (26 bit)
SYSCTL_DC1_WDT1 : Watchdog Timer1 Present
bits : 28 - 56 (29 bit)
Device Capabilities 1
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC1_JTAG : JTAG Present
bits : 0 - 0 (1 bit)
SYSCTL_DC1_SWD : SWD Present
bits : 1 - 2 (2 bit)
SYSCTL_DC1_SWO : SWO Trace Port Present
bits : 2 - 4 (3 bit)
SYSCTL_DC1_WDT0 : Watchdog Timer 0 Present
bits : 3 - 6 (4 bit)
SYSCTL_DC1_PLL : PLL Present
bits : 4 - 8 (5 bit)
SYSCTL_DC1_TEMP : Temp Sensor Present
bits : 5 - 10 (6 bit)
SYSCTL_DC1_MPU : MPU Present
bits : 7 - 14 (8 bit)
SYSCTL_DC1_ADC0SPD : Max ADC0 Speed
bits : 8 - 17 (10 bit)
Enumeration:
0x3 : SYSCTL_DC1_ADC0SPD_1M
1M samples/second
End of enumeration elements list.
SYSCTL_DC1_ADC1SPD : Max ADC1 Speed
bits : 10 - 21 (12 bit)
Enumeration:
0x3 : SYSCTL_DC1_ADC1SPD_1M
1M samples/second
End of enumeration elements list.
SYSCTL_DC1_MINSYSDIV : System Clock Divider
bits : 12 - 27 (16 bit)
Enumeration:
0x1 : SYSCTL_DC1_MINSYSDIV_100
Divide VCO (400MHZ) by 5 minimum
0x2 : SYSCTL_DC1_MINSYSDIV_66
Divide VCO (400MHZ) by 2*2 + 2 = 6 minimum
0x3 : SYSCTL_DC1_MINSYSDIV_50
Specifies a 50-MHz CPU clock with a PLL divider of 4
0x7 : SYSCTL_DC1_MINSYSDIV_25
Specifies a 25-MHz clock with a PLL divider of 8
0x9 : SYSCTL_DC1_MINSYSDIV_20
Specifies a 20-MHz clock with a PLL divider of 10
End of enumeration elements list.
SYSCTL_DC1_ADC0 : ADC Module 0 Present
bits : 16 - 32 (17 bit)
SYSCTL_DC1_ADC1 : ADC Module 1 Present
bits : 17 - 34 (18 bit)
SYSCTL_DC1_CAN0 : CAN Module 0 Present
bits : 24 - 48 (25 bit)
SYSCTL_DC1_CAN1 : CAN Module 1 Present
bits : 25 - 50 (26 bit)
SYSCTL_DC1_WDT1 : Watchdog Timer1 Present
bits : 28 - 56 (29 bit)
Run Mode Clock Gating Control Register 0
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGC0_WDT0 : WDT0 Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_RCGC0_ADC0SPD : ADC0 Sample Speed
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : SYSCTL_RCGC0_ADC0SPD_125K
125K samples/second
0x1 : SYSCTL_RCGC0_ADC0SPD_250K
250K samples/second
0x2 : SYSCTL_RCGC0_ADC0SPD_500K
500K samples/second
0x3 : SYSCTL_RCGC0_ADC0SPD_1M
1M samples/second
End of enumeration elements list.
SYSCTL_RCGC0_ADC1SPD : ADC1 Sample Speed
bits : 10 - 21 (12 bit)
Enumeration:
0x0 : SYSCTL_RCGC0_ADC1SPD_125K
125K samples/second
0x1 : SYSCTL_RCGC0_ADC1SPD_250K
250K samples/second
0x2 : SYSCTL_RCGC0_ADC1SPD_500K
500K samples/second
0x3 : SYSCTL_RCGC0_ADC1SPD_1M
1M samples/second
End of enumeration elements list.
SYSCTL_RCGC0_ADC0 : ADC0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_RCGC0_ADC1 : ADC1 Clock Gating Control
bits : 17 - 34 (18 bit)
SYSCTL_RCGC0_CAN0 : CAN0 Clock Gating Control
bits : 24 - 48 (25 bit)
SYSCTL_RCGC0_CAN1 : CAN1 Clock Gating Control
bits : 25 - 50 (26 bit)
SYSCTL_RCGC0_WDT1 : WDT1 Clock Gating Control
bits : 28 - 56 (29 bit)
Run Mode Clock Gating Control Register 0
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGC0_WDT0 : WDT0 Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_RCGC0_ADC0SPD : ADC0 Sample Speed
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : SYSCTL_RCGC0_ADC0SPD_125K
125K samples/second
0x1 : SYSCTL_RCGC0_ADC0SPD_250K
250K samples/second
0x2 : SYSCTL_RCGC0_ADC0SPD_500K
500K samples/second
0x3 : SYSCTL_RCGC0_ADC0SPD_1M
1M samples/second
End of enumeration elements list.
SYSCTL_RCGC0_ADC1SPD : ADC1 Sample Speed
bits : 10 - 21 (12 bit)
Enumeration:
0x0 : SYSCTL_RCGC0_ADC1SPD_125K
125K samples/second
0x1 : SYSCTL_RCGC0_ADC1SPD_250K
250K samples/second
0x2 : SYSCTL_RCGC0_ADC1SPD_500K
500K samples/second
0x3 : SYSCTL_RCGC0_ADC1SPD_1M
1M samples/second
End of enumeration elements list.
SYSCTL_RCGC0_ADC0 : ADC0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_RCGC0_ADC1 : ADC1 Clock Gating Control
bits : 17 - 34 (18 bit)
SYSCTL_RCGC0_CAN0 : CAN0 Clock Gating Control
bits : 24 - 48 (25 bit)
SYSCTL_RCGC0_CAN1 : CAN1 Clock Gating Control
bits : 25 - 50 (26 bit)
SYSCTL_RCGC0_WDT1 : WDT1 Clock Gating Control
bits : 28 - 56 (29 bit)
Run Mode Clock Gating Control Register 1
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGC1_UART0 : UART0 Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGC1_UART1 : UART1 Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_RCGC1_UART2 : UART2 Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_RCGC1_SSI0 : SSI0 Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_RCGC1_SSI1 : SSI1 Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_RCGC1_QEI0 : QEI0 Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_RCGC1_QEI1 : QEI1 Clock Gating Control
bits : 9 - 18 (10 bit)
SYSCTL_RCGC1_I2C0 : I2C0 Clock Gating Control
bits : 12 - 24 (13 bit)
SYSCTL_RCGC1_I2C1 : I2C1 Clock Gating Control
bits : 14 - 28 (15 bit)
SYSCTL_RCGC1_TIMER0 : Timer 0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_RCGC1_TIMER1 : Timer 1 Clock Gating Control
bits : 17 - 34 (18 bit)
SYSCTL_RCGC1_TIMER2 : Timer 2 Clock Gating Control
bits : 18 - 36 (19 bit)
SYSCTL_RCGC1_TIMER3 : Timer 3 Clock Gating Control
bits : 19 - 38 (20 bit)
SYSCTL_RCGC1_COMP0 : Analog Comparator 0 Clock Gating
bits : 24 - 48 (25 bit)
SYSCTL_RCGC1_COMP1 : Analog Comparator 1 Clock Gating
bits : 25 - 50 (26 bit)
SYSCTL_RCGC1_COMP2 : Analog Comparator 2 Clock Gating
bits : 26 - 52 (27 bit)
SYSCTL_RCGC1_I2S0 : I2S0 Clock Gating
bits : 28 - 56 (29 bit)
SYSCTL_RCGC1_EPI0 : EPI0 Clock Gating
bits : 30 - 60 (31 bit)
Run Mode Clock Gating Control Register 1
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGC1_UART0 : UART0 Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGC1_UART1 : UART1 Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_RCGC1_UART2 : UART2 Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_RCGC1_SSI0 : SSI0 Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_RCGC1_SSI1 : SSI1 Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_RCGC1_QEI0 : QEI0 Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_RCGC1_QEI1 : QEI1 Clock Gating Control
bits : 9 - 18 (10 bit)
SYSCTL_RCGC1_I2C0 : I2C0 Clock Gating Control
bits : 12 - 24 (13 bit)
SYSCTL_RCGC1_I2C1 : I2C1 Clock Gating Control
bits : 14 - 28 (15 bit)
SYSCTL_RCGC1_TIMER0 : Timer 0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_RCGC1_TIMER1 : Timer 1 Clock Gating Control
bits : 17 - 34 (18 bit)
SYSCTL_RCGC1_TIMER2 : Timer 2 Clock Gating Control
bits : 18 - 36 (19 bit)
SYSCTL_RCGC1_TIMER3 : Timer 3 Clock Gating Control
bits : 19 - 38 (20 bit)
SYSCTL_RCGC1_COMP0 : Analog Comparator 0 Clock Gating
bits : 24 - 48 (25 bit)
SYSCTL_RCGC1_COMP1 : Analog Comparator 1 Clock Gating
bits : 25 - 50 (26 bit)
SYSCTL_RCGC1_COMP2 : Analog Comparator 2 Clock Gating
bits : 26 - 52 (27 bit)
SYSCTL_RCGC1_I2S0 : I2S0 Clock Gating
bits : 28 - 56 (29 bit)
SYSCTL_RCGC1_EPI0 : EPI0 Clock Gating
bits : 30 - 60 (31 bit)
Run Mode Clock Gating Control Register 2
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGC2_GPIOA : Port A Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGC2_GPIOB : Port B Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_RCGC2_GPIOC : Port C Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_RCGC2_GPIOD : Port D Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_RCGC2_GPIOE : Port E Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_RCGC2_GPIOF : Port F Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_RCGC2_GPIOG : Port G Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_RCGC2_GPIOH : Port H Clock Gating Control
bits : 7 - 14 (8 bit)
SYSCTL_RCGC2_GPIOJ : Port J Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_RCGC2_UDMA : Micro-DMA Clock Gating Control
bits : 13 - 26 (14 bit)
SYSCTL_RCGC2_USB0 : USB0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_RCGC2_EMAC0 : MAC0 Clock Gating Control
bits : 28 - 56 (29 bit)
SYSCTL_RCGC2_EPHY0 : PHY0 Clock Gating Control
bits : 30 - 60 (31 bit)
Run Mode Clock Gating Control Register 2
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGC2_GPIOA : Port A Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGC2_GPIOB : Port B Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_RCGC2_GPIOC : Port C Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_RCGC2_GPIOD : Port D Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_RCGC2_GPIOE : Port E Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_RCGC2_GPIOF : Port F Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_RCGC2_GPIOG : Port G Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_RCGC2_GPIOH : Port H Clock Gating Control
bits : 7 - 14 (8 bit)
SYSCTL_RCGC2_GPIOJ : Port J Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_RCGC2_UDMA : Micro-DMA Clock Gating Control
bits : 13 - 26 (14 bit)
SYSCTL_RCGC2_USB0 : USB0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_RCGC2_EMAC0 : MAC0 Clock Gating Control
bits : 28 - 56 (29 bit)
SYSCTL_RCGC2_EPHY0 : PHY0 Clock Gating Control
bits : 30 - 60 (31 bit)
Sleep Mode Clock Gating Control Register 0
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGC0_WDT0 : WDT0 Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_SCGC0_ADC0SPD : ADC0 Sample Speed
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : SYSCTL_SCGC0_ADC0SPD_125K
125K samples/second
0x1 : SYSCTL_SCGC0_ADC0SPD_250K
250K samples/second
0x2 : SYSCTL_SCGC0_ADC0SPD_500K
500K samples/second
0x3 : SYSCTL_SCGC0_ADC0SPD_1M
1M samples/second
End of enumeration elements list.
SYSCTL_SCGC0_ADC1SPD : ADC1 Sample Speed
bits : 10 - 21 (12 bit)
Enumeration:
0x0 : SYSCTL_SCGC0_ADC1SPD_125K
125K samples/second
0x1 : SYSCTL_SCGC0_ADC1SPD_250K
250K samples/second
0x2 : SYSCTL_SCGC0_ADC1SPD_500K
500K samples/second
0x3 : SYSCTL_SCGC0_ADC1SPD_1M
1M samples/second
End of enumeration elements list.
SYSCTL_SCGC0_ADC0 : ADC0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_SCGC0_ADC1 : ADC1 Clock Gating Control
bits : 17 - 34 (18 bit)
SYSCTL_SCGC0_CAN0 : CAN0 Clock Gating Control
bits : 24 - 48 (25 bit)
SYSCTL_SCGC0_CAN1 : CAN1 Clock Gating Control
bits : 25 - 50 (26 bit)
SYSCTL_SCGC0_WDT1 : WDT1 Clock Gating Control
bits : 28 - 56 (29 bit)
Sleep Mode Clock Gating Control Register 0
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGC0_WDT0 : WDT0 Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_SCGC0_ADC0SPD : ADC0 Sample Speed
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : SYSCTL_SCGC0_ADC0SPD_125K
125K samples/second
0x1 : SYSCTL_SCGC0_ADC0SPD_250K
250K samples/second
0x2 : SYSCTL_SCGC0_ADC0SPD_500K
500K samples/second
0x3 : SYSCTL_SCGC0_ADC0SPD_1M
1M samples/second
End of enumeration elements list.
SYSCTL_SCGC0_ADC1SPD : ADC1 Sample Speed
bits : 10 - 21 (12 bit)
Enumeration:
0x0 : SYSCTL_SCGC0_ADC1SPD_125K
125K samples/second
0x1 : SYSCTL_SCGC0_ADC1SPD_250K
250K samples/second
0x2 : SYSCTL_SCGC0_ADC1SPD_500K
500K samples/second
0x3 : SYSCTL_SCGC0_ADC1SPD_1M
1M samples/second
End of enumeration elements list.
SYSCTL_SCGC0_ADC0 : ADC0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_SCGC0_ADC1 : ADC1 Clock Gating Control
bits : 17 - 34 (18 bit)
SYSCTL_SCGC0_CAN0 : CAN0 Clock Gating Control
bits : 24 - 48 (25 bit)
SYSCTL_SCGC0_CAN1 : CAN1 Clock Gating Control
bits : 25 - 50 (26 bit)
SYSCTL_SCGC0_WDT1 : WDT1 Clock Gating Control
bits : 28 - 56 (29 bit)
Sleep Mode Clock Gating Control Register 1
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGC1_UART0 : UART0 Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGC1_UART1 : UART1 Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_SCGC1_UART2 : UART2 Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_SCGC1_SSI0 : SSI0 Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_SCGC1_SSI1 : SSI1 Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_SCGC1_QEI0 : QEI0 Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_SCGC1_QEI1 : QEI1 Clock Gating Control
bits : 9 - 18 (10 bit)
SYSCTL_SCGC1_I2C0 : I2C0 Clock Gating Control
bits : 12 - 24 (13 bit)
SYSCTL_SCGC1_I2C1 : I2C1 Clock Gating Control
bits : 14 - 28 (15 bit)
SYSCTL_SCGC1_TIMER0 : Timer 0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_SCGC1_TIMER1 : Timer 1 Clock Gating Control
bits : 17 - 34 (18 bit)
SYSCTL_SCGC1_TIMER2 : Timer 2 Clock Gating Control
bits : 18 - 36 (19 bit)
SYSCTL_SCGC1_TIMER3 : Timer 3 Clock Gating Control
bits : 19 - 38 (20 bit)
SYSCTL_SCGC1_COMP0 : Analog Comparator 0 Clock Gating
bits : 24 - 48 (25 bit)
SYSCTL_SCGC1_COMP1 : Analog Comparator 1 Clock Gating
bits : 25 - 50 (26 bit)
SYSCTL_SCGC1_COMP2 : Analog Comparator 2 Clock Gating
bits : 26 - 52 (27 bit)
SYSCTL_SCGC1_I2S0 : I2S0 Clock Gating
bits : 28 - 56 (29 bit)
SYSCTL_SCGC1_EPI0 : EPI0 Clock Gating
bits : 30 - 60 (31 bit)
Sleep Mode Clock Gating Control Register 1
address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGC1_UART0 : UART0 Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGC1_UART1 : UART1 Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_SCGC1_UART2 : UART2 Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_SCGC1_SSI0 : SSI0 Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_SCGC1_SSI1 : SSI1 Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_SCGC1_QEI0 : QEI0 Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_SCGC1_QEI1 : QEI1 Clock Gating Control
bits : 9 - 18 (10 bit)
SYSCTL_SCGC1_I2C0 : I2C0 Clock Gating Control
bits : 12 - 24 (13 bit)
SYSCTL_SCGC1_I2C1 : I2C1 Clock Gating Control
bits : 14 - 28 (15 bit)
SYSCTL_SCGC1_TIMER0 : Timer 0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_SCGC1_TIMER1 : Timer 1 Clock Gating Control
bits : 17 - 34 (18 bit)
SYSCTL_SCGC1_TIMER2 : Timer 2 Clock Gating Control
bits : 18 - 36 (19 bit)
SYSCTL_SCGC1_TIMER3 : Timer 3 Clock Gating Control
bits : 19 - 38 (20 bit)
SYSCTL_SCGC1_COMP0 : Analog Comparator 0 Clock Gating
bits : 24 - 48 (25 bit)
SYSCTL_SCGC1_COMP1 : Analog Comparator 1 Clock Gating
bits : 25 - 50 (26 bit)
SYSCTL_SCGC1_COMP2 : Analog Comparator 2 Clock Gating
bits : 26 - 52 (27 bit)
SYSCTL_SCGC1_I2S0 : I2S0 Clock Gating
bits : 28 - 56 (29 bit)
SYSCTL_SCGC1_EPI0 : EPI0 Clock Gating
bits : 30 - 60 (31 bit)
Sleep Mode Clock Gating Control Register 2
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGC2_GPIOA : Port A Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGC2_GPIOB : Port B Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_SCGC2_GPIOC : Port C Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_SCGC2_GPIOD : Port D Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_SCGC2_GPIOE : Port E Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_SCGC2_GPIOF : Port F Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_SCGC2_GPIOG : Port G Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_SCGC2_GPIOH : Port H Clock Gating Control
bits : 7 - 14 (8 bit)
SYSCTL_SCGC2_GPIOJ : Port J Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_SCGC2_UDMA : Micro-DMA Clock Gating Control
bits : 13 - 26 (14 bit)
SYSCTL_SCGC2_USB0 : USB0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_SCGC2_EMAC0 : MAC0 Clock Gating Control
bits : 28 - 56 (29 bit)
SYSCTL_SCGC2_EPHY0 : PHY0 Clock Gating Control
bits : 30 - 60 (31 bit)
Sleep Mode Clock Gating Control Register 2
address_offset : 0x118 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGC2_GPIOA : Port A Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGC2_GPIOB : Port B Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_SCGC2_GPIOC : Port C Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_SCGC2_GPIOD : Port D Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_SCGC2_GPIOE : Port E Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_SCGC2_GPIOF : Port F Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_SCGC2_GPIOG : Port G Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_SCGC2_GPIOH : Port H Clock Gating Control
bits : 7 - 14 (8 bit)
SYSCTL_SCGC2_GPIOJ : Port J Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_SCGC2_UDMA : Micro-DMA Clock Gating Control
bits : 13 - 26 (14 bit)
SYSCTL_SCGC2_USB0 : USB0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_SCGC2_EMAC0 : MAC0 Clock Gating Control
bits : 28 - 56 (29 bit)
SYSCTL_SCGC2_EPHY0 : PHY0 Clock Gating Control
bits : 30 - 60 (31 bit)
Deep Sleep Mode Clock Gating Control Register 0
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGC0_WDT0 : WDT0 Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_DCGC0_ADC0 : ADC0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_DCGC0_ADC1 : ADC1 Clock Gating Control
bits : 17 - 34 (18 bit)
SYSCTL_DCGC0_CAN0 : CAN0 Clock Gating Control
bits : 24 - 48 (25 bit)
SYSCTL_DCGC0_CAN1 : CAN1 Clock Gating Control
bits : 25 - 50 (26 bit)
SYSCTL_DCGC0_WDT1 : WDT1 Clock Gating Control
bits : 28 - 56 (29 bit)
Deep Sleep Mode Clock Gating Control Register 0
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGC0_WDT0 : WDT0 Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_DCGC0_ADC0 : ADC0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_DCGC0_ADC1 : ADC1 Clock Gating Control
bits : 17 - 34 (18 bit)
SYSCTL_DCGC0_CAN0 : CAN0 Clock Gating Control
bits : 24 - 48 (25 bit)
SYSCTL_DCGC0_CAN1 : CAN1 Clock Gating Control
bits : 25 - 50 (26 bit)
SYSCTL_DCGC0_WDT1 : WDT1 Clock Gating Control
bits : 28 - 56 (29 bit)
Deep-Sleep Mode Clock Gating Control Register 1
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGC1_UART0 : UART0 Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGC1_UART1 : UART1 Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_DCGC1_UART2 : UART2 Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_DCGC1_SSI0 : SSI0 Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_DCGC1_SSI1 : SSI1 Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_DCGC1_QEI0 : QEI0 Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_DCGC1_QEI1 : QEI1 Clock Gating Control
bits : 9 - 18 (10 bit)
SYSCTL_DCGC1_I2C0 : I2C0 Clock Gating Control
bits : 12 - 24 (13 bit)
SYSCTL_DCGC1_I2C1 : I2C1 Clock Gating Control
bits : 14 - 28 (15 bit)
SYSCTL_DCGC1_TIMER0 : Timer 0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_DCGC1_TIMER1 : Timer 1 Clock Gating Control
bits : 17 - 34 (18 bit)
SYSCTL_DCGC1_TIMER2 : Timer 2 Clock Gating Control
bits : 18 - 36 (19 bit)
SYSCTL_DCGC1_TIMER3 : Timer 3 Clock Gating Control
bits : 19 - 38 (20 bit)
SYSCTL_DCGC1_COMP0 : Analog Comparator 0 Clock Gating
bits : 24 - 48 (25 bit)
SYSCTL_DCGC1_COMP1 : Analog Comparator 1 Clock Gating
bits : 25 - 50 (26 bit)
SYSCTL_DCGC1_COMP2 : Analog Comparator 2 Clock Gating
bits : 26 - 52 (27 bit)
SYSCTL_DCGC1_I2S0 : I2S0 Clock Gating
bits : 28 - 56 (29 bit)
SYSCTL_DCGC1_EPI0 : EPI0 Clock Gating
bits : 30 - 60 (31 bit)
Deep-Sleep Mode Clock Gating Control Register 1
address_offset : 0x124 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGC1_UART0 : UART0 Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGC1_UART1 : UART1 Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_DCGC1_UART2 : UART2 Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_DCGC1_SSI0 : SSI0 Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_DCGC1_SSI1 : SSI1 Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_DCGC1_QEI0 : QEI0 Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_DCGC1_QEI1 : QEI1 Clock Gating Control
bits : 9 - 18 (10 bit)
SYSCTL_DCGC1_I2C0 : I2C0 Clock Gating Control
bits : 12 - 24 (13 bit)
SYSCTL_DCGC1_I2C1 : I2C1 Clock Gating Control
bits : 14 - 28 (15 bit)
SYSCTL_DCGC1_TIMER0 : Timer 0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_DCGC1_TIMER1 : Timer 1 Clock Gating Control
bits : 17 - 34 (18 bit)
SYSCTL_DCGC1_TIMER2 : Timer 2 Clock Gating Control
bits : 18 - 36 (19 bit)
SYSCTL_DCGC1_TIMER3 : Timer 3 Clock Gating Control
bits : 19 - 38 (20 bit)
SYSCTL_DCGC1_COMP0 : Analog Comparator 0 Clock Gating
bits : 24 - 48 (25 bit)
SYSCTL_DCGC1_COMP1 : Analog Comparator 1 Clock Gating
bits : 25 - 50 (26 bit)
SYSCTL_DCGC1_COMP2 : Analog Comparator 2 Clock Gating
bits : 26 - 52 (27 bit)
SYSCTL_DCGC1_I2S0 : I2S0 Clock Gating
bits : 28 - 56 (29 bit)
SYSCTL_DCGC1_EPI0 : EPI0 Clock Gating
bits : 30 - 60 (31 bit)
Deep Sleep Mode Clock Gating Control Register 2
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGC2_GPIOA : Port A Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGC2_GPIOB : Port B Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_DCGC2_GPIOC : Port C Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_DCGC2_GPIOD : Port D Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_DCGC2_GPIOE : Port E Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_DCGC2_GPIOF : Port F Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_DCGC2_GPIOG : Port G Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_DCGC2_GPIOH : Port H Clock Gating Control
bits : 7 - 14 (8 bit)
SYSCTL_DCGC2_GPIOJ : Port J Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_DCGC2_UDMA : Micro-DMA Clock Gating Control
bits : 13 - 26 (14 bit)
SYSCTL_DCGC2_USB0 : USB0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_DCGC2_EMAC0 : MAC0 Clock Gating Control
bits : 28 - 56 (29 bit)
SYSCTL_DCGC2_EPHY0 : PHY0 Clock Gating Control
bits : 30 - 60 (31 bit)
Deep Sleep Mode Clock Gating Control Register 2
address_offset : 0x128 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGC2_GPIOA : Port A Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGC2_GPIOB : Port B Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_DCGC2_GPIOC : Port C Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_DCGC2_GPIOD : Port D Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_DCGC2_GPIOE : Port E Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_DCGC2_GPIOF : Port F Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_DCGC2_GPIOG : Port G Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_DCGC2_GPIOH : Port H Clock Gating Control
bits : 7 - 14 (8 bit)
SYSCTL_DCGC2_GPIOJ : Port J Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_DCGC2_UDMA : Micro-DMA Clock Gating Control
bits : 13 - 26 (14 bit)
SYSCTL_DCGC2_USB0 : USB0 Clock Gating Control
bits : 16 - 32 (17 bit)
SYSCTL_DCGC2_EMAC0 : MAC0 Clock Gating Control
bits : 28 - 56 (29 bit)
SYSCTL_DCGC2_EPHY0 : PHY0 Clock Gating Control
bits : 30 - 60 (31 bit)
Device Capabilities 2
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC2_UART0 : UART Module 0 Present
bits : 0 - 0 (1 bit)
SYSCTL_DC2_UART1 : UART Module 1 Present
bits : 1 - 2 (2 bit)
SYSCTL_DC2_UART2 : UART Module 2 Present
bits : 2 - 4 (3 bit)
SYSCTL_DC2_SSI0 : SSI Module 0 Present
bits : 4 - 8 (5 bit)
SYSCTL_DC2_SSI1 : SSI Module 1 Present
bits : 5 - 10 (6 bit)
SYSCTL_DC2_QEI0 : QEI Module 0 Present
bits : 8 - 16 (9 bit)
SYSCTL_DC2_QEI1 : QEI Module 1 Present
bits : 9 - 18 (10 bit)
SYSCTL_DC2_I2C0 : I2C Module 0 Present
bits : 12 - 24 (13 bit)
SYSCTL_DC2_I2C1 : I2C Module 1 Present
bits : 14 - 28 (15 bit)
SYSCTL_DC2_TIMER0 : Timer Module 0 Present
bits : 16 - 32 (17 bit)
SYSCTL_DC2_TIMER1 : Timer Module 1 Present
bits : 17 - 34 (18 bit)
SYSCTL_DC2_TIMER2 : Timer Module 2 Present
bits : 18 - 36 (19 bit)
SYSCTL_DC2_TIMER3 : Timer Module 3 Present
bits : 19 - 38 (20 bit)
SYSCTL_DC2_COMP0 : Analog Comparator 0 Present
bits : 24 - 48 (25 bit)
SYSCTL_DC2_COMP1 : Analog Comparator 1 Present
bits : 25 - 50 (26 bit)
SYSCTL_DC2_COMP2 : Analog Comparator 2 Present
bits : 26 - 52 (27 bit)
SYSCTL_DC2_I2S0 : I2S Module 0 Present
bits : 28 - 56 (29 bit)
SYSCTL_DC2_EPI0 : EPI Module 0 Present
bits : 30 - 60 (31 bit)
Device Capabilities 2
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC2_UART0 : UART Module 0 Present
bits : 0 - 0 (1 bit)
SYSCTL_DC2_UART1 : UART Module 1 Present
bits : 1 - 2 (2 bit)
SYSCTL_DC2_UART2 : UART Module 2 Present
bits : 2 - 4 (3 bit)
SYSCTL_DC2_SSI0 : SSI Module 0 Present
bits : 4 - 8 (5 bit)
SYSCTL_DC2_SSI1 : SSI Module 1 Present
bits : 5 - 10 (6 bit)
SYSCTL_DC2_QEI0 : QEI Module 0 Present
bits : 8 - 16 (9 bit)
SYSCTL_DC2_QEI1 : QEI Module 1 Present
bits : 9 - 18 (10 bit)
SYSCTL_DC2_I2C0 : I2C Module 0 Present
bits : 12 - 24 (13 bit)
SYSCTL_DC2_I2C1 : I2C Module 1 Present
bits : 14 - 28 (15 bit)
SYSCTL_DC2_TIMER0 : Timer Module 0 Present
bits : 16 - 32 (17 bit)
SYSCTL_DC2_TIMER1 : Timer Module 1 Present
bits : 17 - 34 (18 bit)
SYSCTL_DC2_TIMER2 : Timer Module 2 Present
bits : 18 - 36 (19 bit)
SYSCTL_DC2_TIMER3 : Timer Module 3 Present
bits : 19 - 38 (20 bit)
SYSCTL_DC2_COMP0 : Analog Comparator 0 Present
bits : 24 - 48 (25 bit)
SYSCTL_DC2_COMP1 : Analog Comparator 1 Present
bits : 25 - 50 (26 bit)
SYSCTL_DC2_COMP2 : Analog Comparator 2 Present
bits : 26 - 52 (27 bit)
SYSCTL_DC2_I2S0 : I2S Module 0 Present
bits : 28 - 56 (29 bit)
SYSCTL_DC2_EPI0 : EPI Module 0 Present
bits : 30 - 60 (31 bit)
Deep Sleep Clock Configuration
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DSLPCLKCFG_O : Clock Source
bits : 4 - 10 (7 bit)
Enumeration:
0x0 : SYSCTL_DSLPCLKCFG_O_IGN
MOSC
0x1 : SYSCTL_DSLPCLKCFG_O_IO
PIOSC
0x3 : SYSCTL_DSLPCLKCFG_O_30
30 kHz
End of enumeration elements list.
SYSCTL_DSLPCLKCFG_D : Divider Field Override
bits : 23 - 51 (29 bit)
Enumeration:
0x0 : SYSCTL_DSLPCLKCFG_D_1
System clock /1
0x1 : SYSCTL_DSLPCLKCFG_D_2
System clock /2
0x2 : SYSCTL_DSLPCLKCFG_D_3
System clock /3
0x3 : SYSCTL_DSLPCLKCFG_D_4
System clock /4
0x4 : SYSCTL_DSLPCLKCFG_D_5
System clock /5
0x5 : SYSCTL_DSLPCLKCFG_D_6
System clock /6
0x6 : SYSCTL_DSLPCLKCFG_D_7
System clock /7
0x7 : SYSCTL_DSLPCLKCFG_D_8
System clock /8
0x8 : SYSCTL_DSLPCLKCFG_D_9
System clock /9
0x9 : SYSCTL_DSLPCLKCFG_D_10
System clock /10
0xa : SYSCTL_DSLPCLKCFG_D_11
System clock /11
0xb : SYSCTL_DSLPCLKCFG_D_12
System clock /12
0xc : SYSCTL_DSLPCLKCFG_D_13
System clock /13
0xd : SYSCTL_DSLPCLKCFG_D_14
System clock /14
0xe : SYSCTL_DSLPCLKCFG_D_15
System clock /15
0xf : SYSCTL_DSLPCLKCFG_D_16
System clock /16
0x10 : SYSCTL_DSLPCLKCFG_D_17
System clock /17
0x11 : SYSCTL_DSLPCLKCFG_D_18
System clock /18
0x12 : SYSCTL_DSLPCLKCFG_D_19
System clock /19
0x13 : SYSCTL_DSLPCLKCFG_D_20
System clock /20
0x14 : SYSCTL_DSLPCLKCFG_D_21
System clock /21
0x15 : SYSCTL_DSLPCLKCFG_D_22
System clock /22
0x16 : SYSCTL_DSLPCLKCFG_D_23
System clock /23
0x17 : SYSCTL_DSLPCLKCFG_D_24
System clock /24
0x18 : SYSCTL_DSLPCLKCFG_D_25
System clock /25
0x19 : SYSCTL_DSLPCLKCFG_D_26
System clock /26
0x1a : SYSCTL_DSLPCLKCFG_D_27
System clock /27
0x1b : SYSCTL_DSLPCLKCFG_D_28
System clock /28
0x1c : SYSCTL_DSLPCLKCFG_D_29
System clock /29
0x1d : SYSCTL_DSLPCLKCFG_D_30
System clock /30
0x1e : SYSCTL_DSLPCLKCFG_D_31
System clock /31
0x1f : SYSCTL_DSLPCLKCFG_D_32
System clock /32
0x20 : SYSCTL_DSLPCLKCFG_D_33
System clock /33
0x21 : SYSCTL_DSLPCLKCFG_D_34
System clock /34
0x22 : SYSCTL_DSLPCLKCFG_D_35
System clock /35
0x23 : SYSCTL_DSLPCLKCFG_D_36
System clock /36
0x24 : SYSCTL_DSLPCLKCFG_D_37
System clock /37
0x25 : SYSCTL_DSLPCLKCFG_D_38
System clock /38
0x26 : SYSCTL_DSLPCLKCFG_D_39
System clock /39
0x27 : SYSCTL_DSLPCLKCFG_D_40
System clock /40
0x28 : SYSCTL_DSLPCLKCFG_D_41
System clock /41
0x29 : SYSCTL_DSLPCLKCFG_D_42
System clock /42
0x2a : SYSCTL_DSLPCLKCFG_D_43
System clock /43
0x2b : SYSCTL_DSLPCLKCFG_D_44
System clock /44
0x2c : SYSCTL_DSLPCLKCFG_D_45
System clock /45
0x2d : SYSCTL_DSLPCLKCFG_D_46
System clock /46
0x2e : SYSCTL_DSLPCLKCFG_D_47
System clock /47
0x2f : SYSCTL_DSLPCLKCFG_D_48
System clock /48
0x30 : SYSCTL_DSLPCLKCFG_D_49
System clock /49
0x31 : SYSCTL_DSLPCLKCFG_D_50
System clock /50
0x32 : SYSCTL_DSLPCLKCFG_D_51
System clock /51
0x33 : SYSCTL_DSLPCLKCFG_D_52
System clock /52
0x34 : SYSCTL_DSLPCLKCFG_D_53
System clock /53
0x35 : SYSCTL_DSLPCLKCFG_D_54
System clock /54
0x36 : SYSCTL_DSLPCLKCFG_D_55
System clock /55
0x37 : SYSCTL_DSLPCLKCFG_D_56
System clock /56
0x38 : SYSCTL_DSLPCLKCFG_D_57
System clock /57
0x39 : SYSCTL_DSLPCLKCFG_D_58
System clock /58
0x3a : SYSCTL_DSLPCLKCFG_D_59
System clock /59
0x3b : SYSCTL_DSLPCLKCFG_D_60
System clock /60
0x3c : SYSCTL_DSLPCLKCFG_D_61
System clock /61
0x3d : SYSCTL_DSLPCLKCFG_D_62
System clock /62
0x3e : SYSCTL_DSLPCLKCFG_D_63
System clock /63
0x3f : SYSCTL_DSLPCLKCFG_D_64
System clock /64
End of enumeration elements list.
Deep Sleep Clock Configuration
address_offset : 0x144 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DSLPCLKCFG_O : Clock Source
bits : 4 - 10 (7 bit)
Enumeration:
0x0 : SYSCTL_DSLPCLKCFG_O_IGN
MOSC
0x1 : SYSCTL_DSLPCLKCFG_O_IO
PIOSC
0x3 : SYSCTL_DSLPCLKCFG_O_30
30 kHz
End of enumeration elements list.
SYSCTL_DSLPCLKCFG_D : Divider Field Override
bits : 23 - 51 (29 bit)
Enumeration:
0x0 : SYSCTL_DSLPCLKCFG_D_1
System clock /1
0x1 : SYSCTL_DSLPCLKCFG_D_2
System clock /2
0x2 : SYSCTL_DSLPCLKCFG_D_3
System clock /3
0x3 : SYSCTL_DSLPCLKCFG_D_4
System clock /4
0x4 : SYSCTL_DSLPCLKCFG_D_5
System clock /5
0x5 : SYSCTL_DSLPCLKCFG_D_6
System clock /6
0x6 : SYSCTL_DSLPCLKCFG_D_7
System clock /7
0x7 : SYSCTL_DSLPCLKCFG_D_8
System clock /8
0x8 : SYSCTL_DSLPCLKCFG_D_9
System clock /9
0x9 : SYSCTL_DSLPCLKCFG_D_10
System clock /10
0xa : SYSCTL_DSLPCLKCFG_D_11
System clock /11
0xb : SYSCTL_DSLPCLKCFG_D_12
System clock /12
0xc : SYSCTL_DSLPCLKCFG_D_13
System clock /13
0xd : SYSCTL_DSLPCLKCFG_D_14
System clock /14
0xe : SYSCTL_DSLPCLKCFG_D_15
System clock /15
0xf : SYSCTL_DSLPCLKCFG_D_16
System clock /16
0x10 : SYSCTL_DSLPCLKCFG_D_17
System clock /17
0x11 : SYSCTL_DSLPCLKCFG_D_18
System clock /18
0x12 : SYSCTL_DSLPCLKCFG_D_19
System clock /19
0x13 : SYSCTL_DSLPCLKCFG_D_20
System clock /20
0x14 : SYSCTL_DSLPCLKCFG_D_21
System clock /21
0x15 : SYSCTL_DSLPCLKCFG_D_22
System clock /22
0x16 : SYSCTL_DSLPCLKCFG_D_23
System clock /23
0x17 : SYSCTL_DSLPCLKCFG_D_24
System clock /24
0x18 : SYSCTL_DSLPCLKCFG_D_25
System clock /25
0x19 : SYSCTL_DSLPCLKCFG_D_26
System clock /26
0x1a : SYSCTL_DSLPCLKCFG_D_27
System clock /27
0x1b : SYSCTL_DSLPCLKCFG_D_28
System clock /28
0x1c : SYSCTL_DSLPCLKCFG_D_29
System clock /29
0x1d : SYSCTL_DSLPCLKCFG_D_30
System clock /30
0x1e : SYSCTL_DSLPCLKCFG_D_31
System clock /31
0x1f : SYSCTL_DSLPCLKCFG_D_32
System clock /32
0x20 : SYSCTL_DSLPCLKCFG_D_33
System clock /33
0x21 : SYSCTL_DSLPCLKCFG_D_34
System clock /34
0x22 : SYSCTL_DSLPCLKCFG_D_35
System clock /35
0x23 : SYSCTL_DSLPCLKCFG_D_36
System clock /36
0x24 : SYSCTL_DSLPCLKCFG_D_37
System clock /37
0x25 : SYSCTL_DSLPCLKCFG_D_38
System clock /38
0x26 : SYSCTL_DSLPCLKCFG_D_39
System clock /39
0x27 : SYSCTL_DSLPCLKCFG_D_40
System clock /40
0x28 : SYSCTL_DSLPCLKCFG_D_41
System clock /41
0x29 : SYSCTL_DSLPCLKCFG_D_42
System clock /42
0x2a : SYSCTL_DSLPCLKCFG_D_43
System clock /43
0x2b : SYSCTL_DSLPCLKCFG_D_44
System clock /44
0x2c : SYSCTL_DSLPCLKCFG_D_45
System clock /45
0x2d : SYSCTL_DSLPCLKCFG_D_46
System clock /46
0x2e : SYSCTL_DSLPCLKCFG_D_47
System clock /47
0x2f : SYSCTL_DSLPCLKCFG_D_48
System clock /48
0x30 : SYSCTL_DSLPCLKCFG_D_49
System clock /49
0x31 : SYSCTL_DSLPCLKCFG_D_50
System clock /50
0x32 : SYSCTL_DSLPCLKCFG_D_51
System clock /51
0x33 : SYSCTL_DSLPCLKCFG_D_52
System clock /52
0x34 : SYSCTL_DSLPCLKCFG_D_53
System clock /53
0x35 : SYSCTL_DSLPCLKCFG_D_54
System clock /54
0x36 : SYSCTL_DSLPCLKCFG_D_55
System clock /55
0x37 : SYSCTL_DSLPCLKCFG_D_56
System clock /56
0x38 : SYSCTL_DSLPCLKCFG_D_57
System clock /57
0x39 : SYSCTL_DSLPCLKCFG_D_58
System clock /58
0x3a : SYSCTL_DSLPCLKCFG_D_59
System clock /59
0x3b : SYSCTL_DSLPCLKCFG_D_60
System clock /60
0x3c : SYSCTL_DSLPCLKCFG_D_61
System clock /61
0x3d : SYSCTL_DSLPCLKCFG_D_62
System clock /62
0x3e : SYSCTL_DSLPCLKCFG_D_63
System clock /63
0x3f : SYSCTL_DSLPCLKCFG_D_64
System clock /64
End of enumeration elements list.
Precision Internal Oscillator Calibration
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PIOSCCAL_UT : User Trim Value
bits : 0 - 6 (7 bit)
SYSCTL_PIOSCCAL_UPDATE : Update Trim
bits : 8 - 16 (9 bit)
SYSCTL_PIOSCCAL_UTEN : Use User Trim Value
bits : 31 - 62 (32 bit)
Precision Internal Oscillator Calibration
address_offset : 0x150 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PIOSCCAL_UT : User Trim Value
bits : 0 - 6 (7 bit)
SYSCTL_PIOSCCAL_UPDATE : Update Trim
bits : 8 - 16 (9 bit)
SYSCTL_PIOSCCAL_UTEN : Use User Trim Value
bits : 31 - 62 (32 bit)
I2S MCLK Configuration
address_offset : 0x170 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_I2SMCLKCFG_TXF : TX Clock Fractional Input
bits : 0 - 3 (4 bit)
SYSCTL_I2SMCLKCFG_TXI : TX Clock Integer Input
bits : 4 - 17 (14 bit)
SYSCTL_I2SMCLKCFG_TXEN : TX Clock Enable
bits : 15 - 30 (16 bit)
SYSCTL_I2SMCLKCFG_RXF : RX Clock Fractional Input
bits : 16 - 35 (20 bit)
SYSCTL_I2SMCLKCFG_RXI : RX Clock Integer Input
bits : 20 - 49 (30 bit)
SYSCTL_I2SMCLKCFG_RXEN : RX Clock Enable
bits : 31 - 62 (32 bit)
I2S MCLK Configuration
address_offset : 0x170 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_I2SMCLKCFG_TXF : TX Clock Fractional Input
bits : 0 - 3 (4 bit)
SYSCTL_I2SMCLKCFG_TXI : TX Clock Integer Input
bits : 4 - 17 (14 bit)
SYSCTL_I2SMCLKCFG_TXEN : TX Clock Enable
bits : 15 - 30 (16 bit)
SYSCTL_I2SMCLKCFG_RXF : RX Clock Fractional Input
bits : 16 - 35 (20 bit)
SYSCTL_I2SMCLKCFG_RXI : RX Clock Integer Input
bits : 20 - 49 (30 bit)
SYSCTL_I2SMCLKCFG_RXEN : RX Clock Enable
bits : 31 - 62 (32 bit)
Device Capabilities 3
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC3_PWM0 : PWM0 Pin Present
bits : 0 - 0 (1 bit)
SYSCTL_DC3_PWM1 : PWM1 Pin Present
bits : 1 - 2 (2 bit)
SYSCTL_DC3_PWM2 : PWM2 Pin Present
bits : 2 - 4 (3 bit)
SYSCTL_DC3_PWM3 : PWM3 Pin Present
bits : 3 - 6 (4 bit)
SYSCTL_DC3_PWM4 : PWM4 Pin Present
bits : 4 - 8 (5 bit)
SYSCTL_DC3_PWM5 : PWM5 Pin Present
bits : 5 - 10 (6 bit)
SYSCTL_DC3_C0MINUS : C0- Pin Present
bits : 6 - 12 (7 bit)
SYSCTL_DC3_C0PLUS : C0+ Pin Present
bits : 7 - 14 (8 bit)
SYSCTL_DC3_C0O : C0o Pin Present
bits : 8 - 16 (9 bit)
SYSCTL_DC3_C1MINUS : C1- Pin Present
bits : 9 - 18 (10 bit)
SYSCTL_DC3_C1PLUS : C1+ Pin Present
bits : 10 - 20 (11 bit)
SYSCTL_DC3_C1O : C1o Pin Present
bits : 11 - 22 (12 bit)
SYSCTL_DC3_C2MINUS : C2- Pin Present
bits : 12 - 24 (13 bit)
SYSCTL_DC3_C2PLUS : C2+ Pin Present
bits : 13 - 26 (14 bit)
SYSCTL_DC3_C2O : C2o Pin Present
bits : 14 - 28 (15 bit)
SYSCTL_DC3_PWMFAULT : PWM Fault Pin Present
bits : 15 - 30 (16 bit)
SYSCTL_DC3_ADC0AIN0 : ADC Module 0 AIN0 Pin Present
bits : 16 - 32 (17 bit)
SYSCTL_DC3_ADC0AIN1 : ADC Module 0 AIN1 Pin Present
bits : 17 - 34 (18 bit)
SYSCTL_DC3_ADC0AIN2 : ADC Module 0 AIN2 Pin Present
bits : 18 - 36 (19 bit)
SYSCTL_DC3_ADC0AIN3 : ADC Module 0 AIN3 Pin Present
bits : 19 - 38 (20 bit)
SYSCTL_DC3_ADC0AIN4 : ADC Module 0 AIN4 Pin Present
bits : 20 - 40 (21 bit)
SYSCTL_DC3_ADC0AIN5 : ADC Module 0 AIN5 Pin Present
bits : 21 - 42 (22 bit)
SYSCTL_DC3_ADC0AIN6 : ADC Module 0 AIN6 Pin Present
bits : 22 - 44 (23 bit)
SYSCTL_DC3_ADC0AIN7 : ADC Module 0 AIN7 Pin Present
bits : 23 - 46 (24 bit)
SYSCTL_DC3_CCP0 : CCP0 Pin Present
bits : 24 - 48 (25 bit)
SYSCTL_DC3_CCP1 : CCP1 Pin Present
bits : 25 - 50 (26 bit)
SYSCTL_DC3_CCP2 : CCP2 Pin Present
bits : 26 - 52 (27 bit)
SYSCTL_DC3_CCP3 : CCP3 Pin Present
bits : 27 - 54 (28 bit)
SYSCTL_DC3_CCP4 : CCP4 Pin Present
bits : 28 - 56 (29 bit)
SYSCTL_DC3_CCP5 : CCP5 Pin Present
bits : 29 - 58 (30 bit)
SYSCTL_DC3_32KHZ : 32KHz Input Clock Available
bits : 31 - 62 (32 bit)
Device Capabilities 3
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC3_PWM0 : PWM0 Pin Present
bits : 0 - 0 (1 bit)
SYSCTL_DC3_PWM1 : PWM1 Pin Present
bits : 1 - 2 (2 bit)
SYSCTL_DC3_PWM2 : PWM2 Pin Present
bits : 2 - 4 (3 bit)
SYSCTL_DC3_PWM3 : PWM3 Pin Present
bits : 3 - 6 (4 bit)
SYSCTL_DC3_PWM4 : PWM4 Pin Present
bits : 4 - 8 (5 bit)
SYSCTL_DC3_PWM5 : PWM5 Pin Present
bits : 5 - 10 (6 bit)
SYSCTL_DC3_C0MINUS : C0- Pin Present
bits : 6 - 12 (7 bit)
SYSCTL_DC3_C0PLUS : C0+ Pin Present
bits : 7 - 14 (8 bit)
SYSCTL_DC3_C0O : C0o Pin Present
bits : 8 - 16 (9 bit)
SYSCTL_DC3_C1MINUS : C1- Pin Present
bits : 9 - 18 (10 bit)
SYSCTL_DC3_C1PLUS : C1+ Pin Present
bits : 10 - 20 (11 bit)
SYSCTL_DC3_C1O : C1o Pin Present
bits : 11 - 22 (12 bit)
SYSCTL_DC3_C2MINUS : C2- Pin Present
bits : 12 - 24 (13 bit)
SYSCTL_DC3_C2PLUS : C2+ Pin Present
bits : 13 - 26 (14 bit)
SYSCTL_DC3_C2O : C2o Pin Present
bits : 14 - 28 (15 bit)
SYSCTL_DC3_PWMFAULT : PWM Fault Pin Present
bits : 15 - 30 (16 bit)
SYSCTL_DC3_ADC0AIN0 : ADC Module 0 AIN0 Pin Present
bits : 16 - 32 (17 bit)
SYSCTL_DC3_ADC0AIN1 : ADC Module 0 AIN1 Pin Present
bits : 17 - 34 (18 bit)
SYSCTL_DC3_ADC0AIN2 : ADC Module 0 AIN2 Pin Present
bits : 18 - 36 (19 bit)
SYSCTL_DC3_ADC0AIN3 : ADC Module 0 AIN3 Pin Present
bits : 19 - 38 (20 bit)
SYSCTL_DC3_ADC0AIN4 : ADC Module 0 AIN4 Pin Present
bits : 20 - 40 (21 bit)
SYSCTL_DC3_ADC0AIN5 : ADC Module 0 AIN5 Pin Present
bits : 21 - 42 (22 bit)
SYSCTL_DC3_ADC0AIN6 : ADC Module 0 AIN6 Pin Present
bits : 22 - 44 (23 bit)
SYSCTL_DC3_ADC0AIN7 : ADC Module 0 AIN7 Pin Present
bits : 23 - 46 (24 bit)
SYSCTL_DC3_CCP0 : CCP0 Pin Present
bits : 24 - 48 (25 bit)
SYSCTL_DC3_CCP1 : CCP1 Pin Present
bits : 25 - 50 (26 bit)
SYSCTL_DC3_CCP2 : CCP2 Pin Present
bits : 26 - 52 (27 bit)
SYSCTL_DC3_CCP3 : CCP3 Pin Present
bits : 27 - 54 (28 bit)
SYSCTL_DC3_CCP4 : CCP4 Pin Present
bits : 28 - 56 (29 bit)
SYSCTL_DC3_CCP5 : CCP5 Pin Present
bits : 29 - 58 (30 bit)
SYSCTL_DC3_32KHZ : 32KHz Input Clock Available
bits : 31 - 62 (32 bit)
Device Capabilities 9 ADC Digital Comparators
address_offset : 0x190 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC9_ADC0DC0 : ADC0 DC0 Present
bits : 0 - 0 (1 bit)
SYSCTL_DC9_ADC0DC1 : ADC0 DC1 Present
bits : 1 - 2 (2 bit)
SYSCTL_DC9_ADC0DC2 : ADC0 DC2 Present
bits : 2 - 4 (3 bit)
SYSCTL_DC9_ADC0DC3 : ADC0 DC3 Present
bits : 3 - 6 (4 bit)
SYSCTL_DC9_ADC0DC4 : ADC0 DC4 Present
bits : 4 - 8 (5 bit)
SYSCTL_DC9_ADC0DC5 : ADC0 DC5 Present
bits : 5 - 10 (6 bit)
SYSCTL_DC9_ADC0DC6 : ADC0 DC6 Present
bits : 6 - 12 (7 bit)
SYSCTL_DC9_ADC0DC7 : ADC0 DC7 Present
bits : 7 - 14 (8 bit)
SYSCTL_DC9_ADC1DC0 : ADC1 DC0 Present
bits : 16 - 32 (17 bit)
SYSCTL_DC9_ADC1DC1 : ADC1 DC1 Present
bits : 17 - 34 (18 bit)
SYSCTL_DC9_ADC1DC2 : ADC1 DC2 Present
bits : 18 - 36 (19 bit)
SYSCTL_DC9_ADC1DC3 : ADC1 DC3 Present
bits : 19 - 38 (20 bit)
SYSCTL_DC9_ADC1DC4 : ADC1 DC4 Present
bits : 20 - 40 (21 bit)
SYSCTL_DC9_ADC1DC5 : ADC1 DC5 Present
bits : 21 - 42 (22 bit)
SYSCTL_DC9_ADC1DC6 : ADC1 DC6 Present
bits : 22 - 44 (23 bit)
SYSCTL_DC9_ADC1DC7 : ADC1 DC7 Present
bits : 23 - 46 (24 bit)
Device Capabilities 9 ADC Digital Comparators
address_offset : 0x190 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC9_ADC0DC0 : ADC0 DC0 Present
bits : 0 - 0 (1 bit)
SYSCTL_DC9_ADC0DC1 : ADC0 DC1 Present
bits : 1 - 2 (2 bit)
SYSCTL_DC9_ADC0DC2 : ADC0 DC2 Present
bits : 2 - 4 (3 bit)
SYSCTL_DC9_ADC0DC3 : ADC0 DC3 Present
bits : 3 - 6 (4 bit)
SYSCTL_DC9_ADC0DC4 : ADC0 DC4 Present
bits : 4 - 8 (5 bit)
SYSCTL_DC9_ADC0DC5 : ADC0 DC5 Present
bits : 5 - 10 (6 bit)
SYSCTL_DC9_ADC0DC6 : ADC0 DC6 Present
bits : 6 - 12 (7 bit)
SYSCTL_DC9_ADC0DC7 : ADC0 DC7 Present
bits : 7 - 14 (8 bit)
SYSCTL_DC9_ADC1DC0 : ADC1 DC0 Present
bits : 16 - 32 (17 bit)
SYSCTL_DC9_ADC1DC1 : ADC1 DC1 Present
bits : 17 - 34 (18 bit)
SYSCTL_DC9_ADC1DC2 : ADC1 DC2 Present
bits : 18 - 36 (19 bit)
SYSCTL_DC9_ADC1DC3 : ADC1 DC3 Present
bits : 19 - 38 (20 bit)
SYSCTL_DC9_ADC1DC4 : ADC1 DC4 Present
bits : 20 - 40 (21 bit)
SYSCTL_DC9_ADC1DC5 : ADC1 DC5 Present
bits : 21 - 42 (22 bit)
SYSCTL_DC9_ADC1DC6 : ADC1 DC6 Present
bits : 22 - 44 (23 bit)
SYSCTL_DC9_ADC1DC7 : ADC1 DC7 Present
bits : 23 - 46 (24 bit)
Non-Volatile Memory Information
address_offset : 0x1A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_NVMSTAT_FWB : 32 Word Flash Write Buffer Active
bits : 0 - 0 (1 bit)
Non-Volatile Memory Information
address_offset : 0x1A0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_NVMSTAT_FWB : 32 Word Flash Write Buffer Active
bits : 0 - 0 (1 bit)
Device Capabilities 4
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC4_GPIOA : GPIO Port A Present
bits : 0 - 0 (1 bit)
SYSCTL_DC4_GPIOB : GPIO Port B Present
bits : 1 - 2 (2 bit)
SYSCTL_DC4_GPIOC : GPIO Port C Present
bits : 2 - 4 (3 bit)
SYSCTL_DC4_GPIOD : GPIO Port D Present
bits : 3 - 6 (4 bit)
SYSCTL_DC4_GPIOE : GPIO Port E Present
bits : 4 - 8 (5 bit)
SYSCTL_DC4_GPIOF : GPIO Port F Present
bits : 5 - 10 (6 bit)
SYSCTL_DC4_GPIOG : GPIO Port G Present
bits : 6 - 12 (7 bit)
SYSCTL_DC4_GPIOH : GPIO Port H Present
bits : 7 - 14 (8 bit)
SYSCTL_DC4_GPIOJ : GPIO Port J Present
bits : 8 - 16 (9 bit)
SYSCTL_DC4_ROM : Internal Code ROM Present
bits : 12 - 24 (13 bit)
SYSCTL_DC4_UDMA : Micro-DMA Module Present
bits : 13 - 26 (14 bit)
SYSCTL_DC4_CCP6 : CCP6 Pin Present
bits : 14 - 28 (15 bit)
SYSCTL_DC4_CCP7 : CCP7 Pin Present
bits : 15 - 30 (16 bit)
SYSCTL_DC4_PICAL : PIOSC Calibrate
bits : 18 - 36 (19 bit)
SYSCTL_DC4_EMAC0 : Ethernet MAC Layer 0 Present
bits : 28 - 56 (29 bit)
SYSCTL_DC4_EPHY0 : Ethernet PHY Layer 0 Present
bits : 30 - 60 (31 bit)
Device Capabilities 4
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC4_GPIOA : GPIO Port A Present
bits : 0 - 0 (1 bit)
SYSCTL_DC4_GPIOB : GPIO Port B Present
bits : 1 - 2 (2 bit)
SYSCTL_DC4_GPIOC : GPIO Port C Present
bits : 2 - 4 (3 bit)
SYSCTL_DC4_GPIOD : GPIO Port D Present
bits : 3 - 6 (4 bit)
SYSCTL_DC4_GPIOE : GPIO Port E Present
bits : 4 - 8 (5 bit)
SYSCTL_DC4_GPIOF : GPIO Port F Present
bits : 5 - 10 (6 bit)
SYSCTL_DC4_GPIOG : GPIO Port G Present
bits : 6 - 12 (7 bit)
SYSCTL_DC4_GPIOH : GPIO Port H Present
bits : 7 - 14 (8 bit)
SYSCTL_DC4_GPIOJ : GPIO Port J Present
bits : 8 - 16 (9 bit)
SYSCTL_DC4_ROM : Internal Code ROM Present
bits : 12 - 24 (13 bit)
SYSCTL_DC4_UDMA : Micro-DMA Module Present
bits : 13 - 26 (14 bit)
SYSCTL_DC4_CCP6 : CCP6 Pin Present
bits : 14 - 28 (15 bit)
SYSCTL_DC4_CCP7 : CCP7 Pin Present
bits : 15 - 30 (16 bit)
SYSCTL_DC4_PICAL : PIOSC Calibrate
bits : 18 - 36 (19 bit)
SYSCTL_DC4_EMAC0 : Ethernet MAC Layer 0 Present
bits : 28 - 56 (29 bit)
SYSCTL_DC4_EPHY0 : Ethernet PHY Layer 0 Present
bits : 30 - 60 (31 bit)
Device Capabilities 5
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC5_PWM0 : PWM0 Pin Present
bits : 0 - 0 (1 bit)
SYSCTL_DC5_PWM1 : PWM1 Pin Present
bits : 1 - 2 (2 bit)
SYSCTL_DC5_PWM2 : PWM2 Pin Present
bits : 2 - 4 (3 bit)
SYSCTL_DC5_PWM3 : PWM3 Pin Present
bits : 3 - 6 (4 bit)
SYSCTL_DC5_PWM4 : PWM4 Pin Present
bits : 4 - 8 (5 bit)
SYSCTL_DC5_PWM5 : PWM5 Pin Present
bits : 5 - 10 (6 bit)
SYSCTL_DC5_PWM6 : PWM6 Pin Present
bits : 6 - 12 (7 bit)
SYSCTL_DC5_PWM7 : PWM7 Pin Present
bits : 7 - 14 (8 bit)
SYSCTL_DC5_PWMESYNC : PWM Extended SYNC Active
bits : 20 - 40 (21 bit)
SYSCTL_DC5_PWMEFLT : PWM Extended Fault Active
bits : 21 - 42 (22 bit)
SYSCTL_DC5_PWMFAULT0 : PWM Fault 0 Pin Present
bits : 24 - 48 (25 bit)
SYSCTL_DC5_PWMFAULT1 : PWM Fault 1 Pin Present
bits : 25 - 50 (26 bit)
SYSCTL_DC5_PWMFAULT2 : PWM Fault 2 Pin Present
bits : 26 - 52 (27 bit)
SYSCTL_DC5_PWMFAULT3 : PWM Fault 3 Pin Present
bits : 27 - 54 (28 bit)
Device Capabilities 5
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC5_PWM0 : PWM0 Pin Present
bits : 0 - 0 (1 bit)
SYSCTL_DC5_PWM1 : PWM1 Pin Present
bits : 1 - 2 (2 bit)
SYSCTL_DC5_PWM2 : PWM2 Pin Present
bits : 2 - 4 (3 bit)
SYSCTL_DC5_PWM3 : PWM3 Pin Present
bits : 3 - 6 (4 bit)
SYSCTL_DC5_PWM4 : PWM4 Pin Present
bits : 4 - 8 (5 bit)
SYSCTL_DC5_PWM5 : PWM5 Pin Present
bits : 5 - 10 (6 bit)
SYSCTL_DC5_PWM6 : PWM6 Pin Present
bits : 6 - 12 (7 bit)
SYSCTL_DC5_PWM7 : PWM7 Pin Present
bits : 7 - 14 (8 bit)
SYSCTL_DC5_PWMESYNC : PWM Extended SYNC Active
bits : 20 - 40 (21 bit)
SYSCTL_DC5_PWMEFLT : PWM Extended Fault Active
bits : 21 - 42 (22 bit)
SYSCTL_DC5_PWMFAULT0 : PWM Fault 0 Pin Present
bits : 24 - 48 (25 bit)
SYSCTL_DC5_PWMFAULT1 : PWM Fault 1 Pin Present
bits : 25 - 50 (26 bit)
SYSCTL_DC5_PWMFAULT2 : PWM Fault 2 Pin Present
bits : 26 - 52 (27 bit)
SYSCTL_DC5_PWMFAULT3 : PWM Fault 3 Pin Present
bits : 27 - 54 (28 bit)
Device Capabilities 6
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC6_USB0 : USB Module 0 Present
bits : 0 - 1 (2 bit)
Enumeration:
0x3 : SYSCTL_DC6_USB0_OTG
USB0 is OTG
End of enumeration elements list.
SYSCTL_DC6_USB0PHY : USB Module 0 PHY Present
bits : 4 - 8 (5 bit)
Device Capabilities 6
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC6_USB0 : USB Module 0 Present
bits : 0 - 1 (2 bit)
Enumeration:
0x3 : SYSCTL_DC6_USB0_OTG
USB0 is OTG
End of enumeration elements list.
SYSCTL_DC6_USB0PHY : USB Module 0 PHY Present
bits : 4 - 8 (5 bit)
Device Capabilities 7
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC7_DMACH0 : USB_EP1_RX / UART2_RX
bits : 0 - 0 (1 bit)
SYSCTL_DC7_DMACH1 : USB_EP1_TX / UART2_TX
bits : 1 - 2 (2 bit)
SYSCTL_DC7_DMACH2 : USB_EP2_RX / Timer3A
bits : 2 - 4 (3 bit)
SYSCTL_DC7_DMACH3 : USB_EP2_TX / Timer3B
bits : 3 - 6 (4 bit)
SYSCTL_DC7_DMACH4 : USB_EP3_RX / Timer2A
bits : 4 - 8 (5 bit)
SYSCTL_DC7_DMACH5 : USB_EP3_TX / Timer2B
bits : 5 - 10 (6 bit)
SYSCTL_DC7_DMACH6 : ETH_RX / Timer2A
bits : 6 - 12 (7 bit)
SYSCTL_DC7_DMACH7 : ETH_TX / Timer2B
bits : 7 - 14 (8 bit)
SYSCTL_DC7_DMACH8 : UART0_RX / UART1_RX
bits : 8 - 16 (9 bit)
SYSCTL_DC7_DMACH9 : UART0_TX / UART1_TX
bits : 9 - 18 (10 bit)
SYSCTL_DC7_DMACH10 : SSI0_RX / SSI1_RX
bits : 10 - 20 (11 bit)
SYSCTL_DC7_DMACH11 : SSI0_TX / SSI1_TX
bits : 11 - 22 (12 bit)
SYSCTL_DC7_DMACH12 : CAN0_RX / UART2_RX
bits : 12 - 24 (13 bit)
SYSCTL_DC7_DMACH13 : CAN0_TX / UART2_TX
bits : 13 - 26 (14 bit)
SYSCTL_DC7_DMACH14 : ADC0_SS0 / Timer2A
bits : 14 - 28 (15 bit)
SYSCTL_DC7_DMACH15 : ADC0_SS1 / Timer2B
bits : 15 - 30 (16 bit)
SYSCTL_DC7_DMACH16 : ADC0_SS2
bits : 16 - 32 (17 bit)
SYSCTL_DC7_DMACH17 : ADC0_SS3
bits : 17 - 34 (18 bit)
SYSCTL_DC7_DMACH18 : Timer0A / Timer1A
bits : 18 - 36 (19 bit)
SYSCTL_DC7_DMACH19 : Timer0B / Timer1B
bits : 19 - 38 (20 bit)
SYSCTL_DC7_DMACH20 : Timer1A / EPI0_NBRFIFO
bits : 20 - 40 (21 bit)
SYSCTL_DC7_DMACH21 : Timer1B / EPI0_WFIFO
bits : 21 - 42 (22 bit)
SYSCTL_DC7_DMACH22 : UART1_RX / CAN2_RX
bits : 22 - 44 (23 bit)
SYSCTL_DC7_DMACH23 : UART1_TX / CAN2_TX
bits : 23 - 46 (24 bit)
SYSCTL_DC7_DMACH24 : SSI1_RX / ADC1_SS0
bits : 24 - 48 (25 bit)
SYSCTL_DC7_DMACH25 : SSI1_TX / ADC1_SS1
bits : 25 - 50 (26 bit)
SYSCTL_DC7_DMACH26 : CAN1_RX / ADC1_SS2
bits : 26 - 52 (27 bit)
SYSCTL_DC7_DMACH27 : CAN1_TX / ADC1_SS3
bits : 27 - 54 (28 bit)
SYSCTL_DC7_DMACH28 : I2S0_RX / CAN1_RX
bits : 28 - 56 (29 bit)
SYSCTL_DC7_DMACH29 : I2S0_TX / CAN1_TX
bits : 29 - 58 (30 bit)
SYSCTL_DC7_DMACH30 : SW
bits : 30 - 60 (31 bit)
Device Capabilities 7
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC7_DMACH0 : USB_EP1_RX / UART2_RX
bits : 0 - 0 (1 bit)
SYSCTL_DC7_DMACH1 : USB_EP1_TX / UART2_TX
bits : 1 - 2 (2 bit)
SYSCTL_DC7_DMACH2 : USB_EP2_RX / Timer3A
bits : 2 - 4 (3 bit)
SYSCTL_DC7_DMACH3 : USB_EP2_TX / Timer3B
bits : 3 - 6 (4 bit)
SYSCTL_DC7_DMACH4 : USB_EP3_RX / Timer2A
bits : 4 - 8 (5 bit)
SYSCTL_DC7_DMACH5 : USB_EP3_TX / Timer2B
bits : 5 - 10 (6 bit)
SYSCTL_DC7_DMACH6 : ETH_RX / Timer2A
bits : 6 - 12 (7 bit)
SYSCTL_DC7_DMACH7 : ETH_TX / Timer2B
bits : 7 - 14 (8 bit)
SYSCTL_DC7_DMACH8 : UART0_RX / UART1_RX
bits : 8 - 16 (9 bit)
SYSCTL_DC7_DMACH9 : UART0_TX / UART1_TX
bits : 9 - 18 (10 bit)
SYSCTL_DC7_DMACH10 : SSI0_RX / SSI1_RX
bits : 10 - 20 (11 bit)
SYSCTL_DC7_DMACH11 : SSI0_TX / SSI1_TX
bits : 11 - 22 (12 bit)
SYSCTL_DC7_DMACH12 : CAN0_RX / UART2_RX
bits : 12 - 24 (13 bit)
SYSCTL_DC7_DMACH13 : CAN0_TX / UART2_TX
bits : 13 - 26 (14 bit)
SYSCTL_DC7_DMACH14 : ADC0_SS0 / Timer2A
bits : 14 - 28 (15 bit)
SYSCTL_DC7_DMACH15 : ADC0_SS1 / Timer2B
bits : 15 - 30 (16 bit)
SYSCTL_DC7_DMACH16 : ADC0_SS2
bits : 16 - 32 (17 bit)
SYSCTL_DC7_DMACH17 : ADC0_SS3
bits : 17 - 34 (18 bit)
SYSCTL_DC7_DMACH18 : Timer0A / Timer1A
bits : 18 - 36 (19 bit)
SYSCTL_DC7_DMACH19 : Timer0B / Timer1B
bits : 19 - 38 (20 bit)
SYSCTL_DC7_DMACH20 : Timer1A / EPI0_NBRFIFO
bits : 20 - 40 (21 bit)
SYSCTL_DC7_DMACH21 : Timer1B / EPI0_WFIFO
bits : 21 - 42 (22 bit)
SYSCTL_DC7_DMACH22 : UART1_RX / CAN2_RX
bits : 22 - 44 (23 bit)
SYSCTL_DC7_DMACH23 : UART1_TX / CAN2_TX
bits : 23 - 46 (24 bit)
SYSCTL_DC7_DMACH24 : SSI1_RX / ADC1_SS0
bits : 24 - 48 (25 bit)
SYSCTL_DC7_DMACH25 : SSI1_TX / ADC1_SS1
bits : 25 - 50 (26 bit)
SYSCTL_DC7_DMACH26 : CAN1_RX / ADC1_SS2
bits : 26 - 52 (27 bit)
SYSCTL_DC7_DMACH27 : CAN1_TX / ADC1_SS3
bits : 27 - 54 (28 bit)
SYSCTL_DC7_DMACH28 : I2S0_RX / CAN1_RX
bits : 28 - 56 (29 bit)
SYSCTL_DC7_DMACH29 : I2S0_TX / CAN1_TX
bits : 29 - 58 (30 bit)
SYSCTL_DC7_DMACH30 : SW
bits : 30 - 60 (31 bit)
Device Capabilities 8 ADC Channels
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC8_ADC0AIN0 : ADC Module 0 AIN0 Pin Present
bits : 0 - 0 (1 bit)
SYSCTL_DC8_ADC0AIN1 : ADC Module 0 AIN1 Pin Present
bits : 1 - 2 (2 bit)
SYSCTL_DC8_ADC0AIN2 : ADC Module 0 AIN2 Pin Present
bits : 2 - 4 (3 bit)
SYSCTL_DC8_ADC0AIN3 : ADC Module 0 AIN3 Pin Present
bits : 3 - 6 (4 bit)
SYSCTL_DC8_ADC0AIN4 : ADC Module 0 AIN4 Pin Present
bits : 4 - 8 (5 bit)
SYSCTL_DC8_ADC0AIN5 : ADC Module 0 AIN5 Pin Present
bits : 5 - 10 (6 bit)
SYSCTL_DC8_ADC0AIN6 : ADC Module 0 AIN6 Pin Present
bits : 6 - 12 (7 bit)
SYSCTL_DC8_ADC0AIN7 : ADC Module 0 AIN7 Pin Present
bits : 7 - 14 (8 bit)
SYSCTL_DC8_ADC0AIN8 : ADC Module 0 AIN8 Pin Present
bits : 8 - 16 (9 bit)
SYSCTL_DC8_ADC0AIN9 : ADC Module 0 AIN9 Pin Present
bits : 9 - 18 (10 bit)
SYSCTL_DC8_ADC0AIN10 : ADC Module 0 AIN10 Pin Present
bits : 10 - 20 (11 bit)
SYSCTL_DC8_ADC0AIN11 : ADC Module 0 AIN11 Pin Present
bits : 11 - 22 (12 bit)
SYSCTL_DC8_ADC0AIN12 : ADC Module 0 AIN12 Pin Present
bits : 12 - 24 (13 bit)
SYSCTL_DC8_ADC0AIN13 : ADC Module 0 AIN13 Pin Present
bits : 13 - 26 (14 bit)
SYSCTL_DC8_ADC0AIN14 : ADC Module 0 AIN14 Pin Present
bits : 14 - 28 (15 bit)
SYSCTL_DC8_ADC0AIN15 : ADC Module 0 AIN15 Pin Present
bits : 15 - 30 (16 bit)
SYSCTL_DC8_ADC1AIN0 : ADC Module 1 AIN0 Pin Present
bits : 16 - 32 (17 bit)
SYSCTL_DC8_ADC1AIN1 : ADC Module 1 AIN1 Pin Present
bits : 17 - 34 (18 bit)
SYSCTL_DC8_ADC1AIN2 : ADC Module 1 AIN2 Pin Present
bits : 18 - 36 (19 bit)
SYSCTL_DC8_ADC1AIN3 : ADC Module 1 AIN3 Pin Present
bits : 19 - 38 (20 bit)
SYSCTL_DC8_ADC1AIN4 : ADC Module 1 AIN4 Pin Present
bits : 20 - 40 (21 bit)
SYSCTL_DC8_ADC1AIN5 : ADC Module 1 AIN5 Pin Present
bits : 21 - 42 (22 bit)
SYSCTL_DC8_ADC1AIN6 : ADC Module 1 AIN6 Pin Present
bits : 22 - 44 (23 bit)
SYSCTL_DC8_ADC1AIN7 : ADC Module 1 AIN7 Pin Present
bits : 23 - 46 (24 bit)
SYSCTL_DC8_ADC1AIN8 : ADC Module 1 AIN8 Pin Present
bits : 24 - 48 (25 bit)
SYSCTL_DC8_ADC1AIN9 : ADC Module 1 AIN9 Pin Present
bits : 25 - 50 (26 bit)
SYSCTL_DC8_ADC1AIN10 : ADC Module 1 AIN10 Pin Present
bits : 26 - 52 (27 bit)
SYSCTL_DC8_ADC1AIN11 : ADC Module 1 AIN11 Pin Present
bits : 27 - 54 (28 bit)
SYSCTL_DC8_ADC1AIN12 : ADC Module 1 AIN12 Pin Present
bits : 28 - 56 (29 bit)
SYSCTL_DC8_ADC1AIN13 : ADC Module 1 AIN13 Pin Present
bits : 29 - 58 (30 bit)
SYSCTL_DC8_ADC1AIN14 : ADC Module 1 AIN14 Pin Present
bits : 30 - 60 (31 bit)
SYSCTL_DC8_ADC1AIN15 : ADC Module 1 AIN15 Pin Present
bits : 31 - 62 (32 bit)
Device Capabilities 8 ADC Channels
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC8_ADC0AIN0 : ADC Module 0 AIN0 Pin Present
bits : 0 - 0 (1 bit)
SYSCTL_DC8_ADC0AIN1 : ADC Module 0 AIN1 Pin Present
bits : 1 - 2 (2 bit)
SYSCTL_DC8_ADC0AIN2 : ADC Module 0 AIN2 Pin Present
bits : 2 - 4 (3 bit)
SYSCTL_DC8_ADC0AIN3 : ADC Module 0 AIN3 Pin Present
bits : 3 - 6 (4 bit)
SYSCTL_DC8_ADC0AIN4 : ADC Module 0 AIN4 Pin Present
bits : 4 - 8 (5 bit)
SYSCTL_DC8_ADC0AIN5 : ADC Module 0 AIN5 Pin Present
bits : 5 - 10 (6 bit)
SYSCTL_DC8_ADC0AIN6 : ADC Module 0 AIN6 Pin Present
bits : 6 - 12 (7 bit)
SYSCTL_DC8_ADC0AIN7 : ADC Module 0 AIN7 Pin Present
bits : 7 - 14 (8 bit)
SYSCTL_DC8_ADC0AIN8 : ADC Module 0 AIN8 Pin Present
bits : 8 - 16 (9 bit)
SYSCTL_DC8_ADC0AIN9 : ADC Module 0 AIN9 Pin Present
bits : 9 - 18 (10 bit)
SYSCTL_DC8_ADC0AIN10 : ADC Module 0 AIN10 Pin Present
bits : 10 - 20 (11 bit)
SYSCTL_DC8_ADC0AIN11 : ADC Module 0 AIN11 Pin Present
bits : 11 - 22 (12 bit)
SYSCTL_DC8_ADC0AIN12 : ADC Module 0 AIN12 Pin Present
bits : 12 - 24 (13 bit)
SYSCTL_DC8_ADC0AIN13 : ADC Module 0 AIN13 Pin Present
bits : 13 - 26 (14 bit)
SYSCTL_DC8_ADC0AIN14 : ADC Module 0 AIN14 Pin Present
bits : 14 - 28 (15 bit)
SYSCTL_DC8_ADC0AIN15 : ADC Module 0 AIN15 Pin Present
bits : 15 - 30 (16 bit)
SYSCTL_DC8_ADC1AIN0 : ADC Module 1 AIN0 Pin Present
bits : 16 - 32 (17 bit)
SYSCTL_DC8_ADC1AIN1 : ADC Module 1 AIN1 Pin Present
bits : 17 - 34 (18 bit)
SYSCTL_DC8_ADC1AIN2 : ADC Module 1 AIN2 Pin Present
bits : 18 - 36 (19 bit)
SYSCTL_DC8_ADC1AIN3 : ADC Module 1 AIN3 Pin Present
bits : 19 - 38 (20 bit)
SYSCTL_DC8_ADC1AIN4 : ADC Module 1 AIN4 Pin Present
bits : 20 - 40 (21 bit)
SYSCTL_DC8_ADC1AIN5 : ADC Module 1 AIN5 Pin Present
bits : 21 - 42 (22 bit)
SYSCTL_DC8_ADC1AIN6 : ADC Module 1 AIN6 Pin Present
bits : 22 - 44 (23 bit)
SYSCTL_DC8_ADC1AIN7 : ADC Module 1 AIN7 Pin Present
bits : 23 - 46 (24 bit)
SYSCTL_DC8_ADC1AIN8 : ADC Module 1 AIN8 Pin Present
bits : 24 - 48 (25 bit)
SYSCTL_DC8_ADC1AIN9 : ADC Module 1 AIN9 Pin Present
bits : 25 - 50 (26 bit)
SYSCTL_DC8_ADC1AIN10 : ADC Module 1 AIN10 Pin Present
bits : 26 - 52 (27 bit)
SYSCTL_DC8_ADC1AIN11 : ADC Module 1 AIN11 Pin Present
bits : 27 - 54 (28 bit)
SYSCTL_DC8_ADC1AIN12 : ADC Module 1 AIN12 Pin Present
bits : 28 - 56 (29 bit)
SYSCTL_DC8_ADC1AIN13 : ADC Module 1 AIN13 Pin Present
bits : 29 - 58 (30 bit)
SYSCTL_DC8_ADC1AIN14 : ADC Module 1 AIN14 Pin Present
bits : 30 - 60 (31 bit)
SYSCTL_DC8_ADC1AIN15 : ADC Module 1 AIN15 Pin Present
bits : 31 - 62 (32 bit)
Brown-Out Reset Control
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PBORCTL_BORIOR : BOR Interrupt or Reset
bits : 1 - 2 (2 bit)
Brown-Out Reset Control
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PBORCTL_BORIOR : BOR Interrupt or Reset
bits : 1 - 2 (2 bit)
Device Identification 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DID1_QUAL : Qualification Status
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : SYSCTL_DID1_QUAL_ES
Engineering Sample (unqualified)
0x1 : SYSCTL_DID1_QUAL_PP
Pilot Production (unqualified)
0x2 : SYSCTL_DID1_QUAL_FQ
Fully Qualified
End of enumeration elements list.
SYSCTL_DID1_ROHS : RoHS-Compliance
bits : 2 - 4 (3 bit)
SYSCTL_DID1_PKG : Package Type
bits : 3 - 7 (5 bit)
Enumeration:
0x0 : SYSCTL_DID1_PKG_SOIC
SOIC package
0x1 : SYSCTL_DID1_PKG_QFP
LQFP package
0x2 : SYSCTL_DID1_PKG_BGA
BGA package
End of enumeration elements list.
SYSCTL_DID1_TEMP : Temperature Range
bits : 5 - 12 (8 bit)
Enumeration:
0x0 : SYSCTL_DID1_TEMP_C
Commercial temperature range (0C to 70C)
0x1 : SYSCTL_DID1_TEMP_I
Industrial temperature range (-40C to 85C)
0x2 : SYSCTL_DID1_TEMP_E
Extended temperature range (-40C to 105C)
End of enumeration elements list.
SYSCTL_DID1_PINCNT : Package Pin Count
bits : 13 - 28 (16 bit)
Enumeration:
0x2 : SYSCTL_DID1_PINCNT_100
100-pin package
End of enumeration elements list.
SYSCTL_DID1_PRTNO : Part Number
bits : 16 - 39 (24 bit)
Enumeration:
0x6a : SYSCTL_DID1_PRTNO_9B92
LM3S9B92
End of enumeration elements list.
SYSCTL_DID1_FAM : Family
bits : 24 - 51 (28 bit)
Enumeration:
0x0 : SYSCTL_DID1_FAM_STELLARIS
Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S
End of enumeration elements list.
SYSCTL_DID1_VER : DID1 Version
bits : 28 - 59 (32 bit)
Enumeration:
0x1 : SYSCTL_DID1_VER_1
Second version of the DID1 register format
End of enumeration elements list.
Device Identification 1
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DID1_QUAL : Qualification Status
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : SYSCTL_DID1_QUAL_ES
Engineering Sample (unqualified)
0x1 : SYSCTL_DID1_QUAL_PP
Pilot Production (unqualified)
0x2 : SYSCTL_DID1_QUAL_FQ
Fully Qualified
End of enumeration elements list.
SYSCTL_DID1_ROHS : RoHS-Compliance
bits : 2 - 4 (3 bit)
SYSCTL_DID1_PKG : Package Type
bits : 3 - 7 (5 bit)
Enumeration:
0x0 : SYSCTL_DID1_PKG_SOIC
SOIC package
0x1 : SYSCTL_DID1_PKG_QFP
LQFP package
0x2 : SYSCTL_DID1_PKG_BGA
BGA package
End of enumeration elements list.
SYSCTL_DID1_TEMP : Temperature Range
bits : 5 - 12 (8 bit)
Enumeration:
0x0 : SYSCTL_DID1_TEMP_C
Commercial temperature range (0C to 70C)
0x1 : SYSCTL_DID1_TEMP_I
Industrial temperature range (-40C to 85C)
0x2 : SYSCTL_DID1_TEMP_E
Extended temperature range (-40C to 105C)
End of enumeration elements list.
SYSCTL_DID1_PINCNT : Package Pin Count
bits : 13 - 28 (16 bit)
Enumeration:
0x2 : SYSCTL_DID1_PINCNT_100
100-pin package
End of enumeration elements list.
SYSCTL_DID1_PRTNO : Part Number
bits : 16 - 39 (24 bit)
Enumeration:
0x6a : SYSCTL_DID1_PRTNO_9B92
LM3S9B92
End of enumeration elements list.
SYSCTL_DID1_FAM : Family
bits : 24 - 51 (28 bit)
Enumeration:
0x0 : SYSCTL_DID1_FAM_STELLARIS
Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S
End of enumeration elements list.
SYSCTL_DID1_VER : DID1 Version
bits : 28 - 59 (32 bit)
Enumeration:
0x1 : SYSCTL_DID1_VER_1
Second version of the DID1 register format
End of enumeration elements list.
Software Reset Control 0
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRCR0_WDT0 : WDT0 Reset Control
bits : 3 - 6 (4 bit)
SYSCTL_SRCR0_ADC0 : ADC0 Reset Control
bits : 16 - 32 (17 bit)
SYSCTL_SRCR0_ADC1 : ADC1 Reset Control
bits : 17 - 34 (18 bit)
SYSCTL_SRCR0_CAN0 : CAN0 Reset Control
bits : 24 - 48 (25 bit)
SYSCTL_SRCR0_CAN1 : CAN1 Reset Control
bits : 25 - 50 (26 bit)
SYSCTL_SRCR0_WDT1 : WDT1 Reset Control
bits : 28 - 56 (29 bit)
Software Reset Control 0
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRCR0_WDT0 : WDT0 Reset Control
bits : 3 - 6 (4 bit)
SYSCTL_SRCR0_ADC0 : ADC0 Reset Control
bits : 16 - 32 (17 bit)
SYSCTL_SRCR0_ADC1 : ADC1 Reset Control
bits : 17 - 34 (18 bit)
SYSCTL_SRCR0_CAN0 : CAN0 Reset Control
bits : 24 - 48 (25 bit)
SYSCTL_SRCR0_CAN1 : CAN1 Reset Control
bits : 25 - 50 (26 bit)
SYSCTL_SRCR0_WDT1 : WDT1 Reset Control
bits : 28 - 56 (29 bit)
Software Reset Control 1
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRCR1_UART0 : UART0 Reset Control
bits : 0 - 0 (1 bit)
SYSCTL_SRCR1_UART1 : UART1 Reset Control
bits : 1 - 2 (2 bit)
SYSCTL_SRCR1_UART2 : UART2 Reset Control
bits : 2 - 4 (3 bit)
SYSCTL_SRCR1_SSI0 : SSI0 Reset Control
bits : 4 - 8 (5 bit)
SYSCTL_SRCR1_SSI1 : SSI1 Reset Control
bits : 5 - 10 (6 bit)
SYSCTL_SRCR1_QEI0 : QEI0 Reset Control
bits : 8 - 16 (9 bit)
SYSCTL_SRCR1_QEI1 : QEI1 Reset Control
bits : 9 - 18 (10 bit)
SYSCTL_SRCR1_I2C0 : I2C0 Reset Control
bits : 12 - 24 (13 bit)
SYSCTL_SRCR1_I2C1 : I2C1 Reset Control
bits : 14 - 28 (15 bit)
SYSCTL_SRCR1_TIMER0 : Timer 0 Reset Control
bits : 16 - 32 (17 bit)
SYSCTL_SRCR1_TIMER1 : Timer 1 Reset Control
bits : 17 - 34 (18 bit)
SYSCTL_SRCR1_TIMER2 : Timer 2 Reset Control
bits : 18 - 36 (19 bit)
SYSCTL_SRCR1_TIMER3 : Timer 3 Reset Control
bits : 19 - 38 (20 bit)
SYSCTL_SRCR1_COMP0 : Analog Comp 0 Reset Control
bits : 24 - 48 (25 bit)
SYSCTL_SRCR1_COMP1 : Analog Comp 1 Reset Control
bits : 25 - 50 (26 bit)
SYSCTL_SRCR1_COMP2 : Analog Comp 2 Reset Control
bits : 26 - 52 (27 bit)
SYSCTL_SRCR1_I2S0 : I2S0 Reset Control
bits : 28 - 56 (29 bit)
SYSCTL_SRCR1_EPI0 : EPI0 Reset Control
bits : 30 - 60 (31 bit)
Software Reset Control 1
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRCR1_UART0 : UART0 Reset Control
bits : 0 - 0 (1 bit)
SYSCTL_SRCR1_UART1 : UART1 Reset Control
bits : 1 - 2 (2 bit)
SYSCTL_SRCR1_UART2 : UART2 Reset Control
bits : 2 - 4 (3 bit)
SYSCTL_SRCR1_SSI0 : SSI0 Reset Control
bits : 4 - 8 (5 bit)
SYSCTL_SRCR1_SSI1 : SSI1 Reset Control
bits : 5 - 10 (6 bit)
SYSCTL_SRCR1_QEI0 : QEI0 Reset Control
bits : 8 - 16 (9 bit)
SYSCTL_SRCR1_QEI1 : QEI1 Reset Control
bits : 9 - 18 (10 bit)
SYSCTL_SRCR1_I2C0 : I2C0 Reset Control
bits : 12 - 24 (13 bit)
SYSCTL_SRCR1_I2C1 : I2C1 Reset Control
bits : 14 - 28 (15 bit)
SYSCTL_SRCR1_TIMER0 : Timer 0 Reset Control
bits : 16 - 32 (17 bit)
SYSCTL_SRCR1_TIMER1 : Timer 1 Reset Control
bits : 17 - 34 (18 bit)
SYSCTL_SRCR1_TIMER2 : Timer 2 Reset Control
bits : 18 - 36 (19 bit)
SYSCTL_SRCR1_TIMER3 : Timer 3 Reset Control
bits : 19 - 38 (20 bit)
SYSCTL_SRCR1_COMP0 : Analog Comp 0 Reset Control
bits : 24 - 48 (25 bit)
SYSCTL_SRCR1_COMP1 : Analog Comp 1 Reset Control
bits : 25 - 50 (26 bit)
SYSCTL_SRCR1_COMP2 : Analog Comp 2 Reset Control
bits : 26 - 52 (27 bit)
SYSCTL_SRCR1_I2S0 : I2S0 Reset Control
bits : 28 - 56 (29 bit)
SYSCTL_SRCR1_EPI0 : EPI0 Reset Control
bits : 30 - 60 (31 bit)
Software Reset Control 2
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRCR2_GPIOA : Port A Reset Control
bits : 0 - 0 (1 bit)
SYSCTL_SRCR2_GPIOB : Port B Reset Control
bits : 1 - 2 (2 bit)
SYSCTL_SRCR2_GPIOC : Port C Reset Control
bits : 2 - 4 (3 bit)
SYSCTL_SRCR2_GPIOD : Port D Reset Control
bits : 3 - 6 (4 bit)
SYSCTL_SRCR2_GPIOE : Port E Reset Control
bits : 4 - 8 (5 bit)
SYSCTL_SRCR2_GPIOF : Port F Reset Control
bits : 5 - 10 (6 bit)
SYSCTL_SRCR2_GPIOG : Port G Reset Control
bits : 6 - 12 (7 bit)
SYSCTL_SRCR2_GPIOH : Port H Reset Control
bits : 7 - 14 (8 bit)
SYSCTL_SRCR2_GPIOJ : Port J Reset Control
bits : 8 - 16 (9 bit)
SYSCTL_SRCR2_UDMA : Micro-DMA Reset Control
bits : 13 - 26 (14 bit)
SYSCTL_SRCR2_USB0 : USB0 Reset Control
bits : 16 - 32 (17 bit)
SYSCTL_SRCR2_EMAC0 : MAC0 Reset Control
bits : 28 - 56 (29 bit)
SYSCTL_SRCR2_EPHY0 : PHY0 Reset Control
bits : 30 - 60 (31 bit)
Software Reset Control 2
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRCR2_GPIOA : Port A Reset Control
bits : 0 - 0 (1 bit)
SYSCTL_SRCR2_GPIOB : Port B Reset Control
bits : 1 - 2 (2 bit)
SYSCTL_SRCR2_GPIOC : Port C Reset Control
bits : 2 - 4 (3 bit)
SYSCTL_SRCR2_GPIOD : Port D Reset Control
bits : 3 - 6 (4 bit)
SYSCTL_SRCR2_GPIOE : Port E Reset Control
bits : 4 - 8 (5 bit)
SYSCTL_SRCR2_GPIOF : Port F Reset Control
bits : 5 - 10 (6 bit)
SYSCTL_SRCR2_GPIOG : Port G Reset Control
bits : 6 - 12 (7 bit)
SYSCTL_SRCR2_GPIOH : Port H Reset Control
bits : 7 - 14 (8 bit)
SYSCTL_SRCR2_GPIOJ : Port J Reset Control
bits : 8 - 16 (9 bit)
SYSCTL_SRCR2_UDMA : Micro-DMA Reset Control
bits : 13 - 26 (14 bit)
SYSCTL_SRCR2_USB0 : USB0 Reset Control
bits : 16 - 32 (17 bit)
SYSCTL_SRCR2_EMAC0 : MAC0 Reset Control
bits : 28 - 56 (29 bit)
SYSCTL_SRCR2_EPHY0 : PHY0 Reset Control
bits : 30 - 60 (31 bit)
Raw Interrupt Status
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RIS_BORRIS : Brown-Out Reset Raw Interrupt Status
bits : 1 - 2 (2 bit)
SYSCTL_RIS_PLLLRIS : PLL Lock Raw Interrupt Status
bits : 6 - 12 (7 bit)
SYSCTL_RIS_USBPLLLRIS : USB PLL Lock Raw Interrupt Status
bits : 7 - 14 (8 bit)
SYSCTL_RIS_MOSCPUPRIS : MOSC Power Up Raw Interrupt Status
bits : 8 - 16 (9 bit)
Raw Interrupt Status
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RIS_BORRIS : Brown-Out Reset Raw Interrupt Status
bits : 1 - 2 (2 bit)
SYSCTL_RIS_PLLLRIS : PLL Lock Raw Interrupt Status
bits : 6 - 12 (7 bit)
SYSCTL_RIS_USBPLLLRIS : USB PLL Lock Raw Interrupt Status
bits : 7 - 14 (8 bit)
SYSCTL_RIS_MOSCPUPRIS : MOSC Power Up Raw Interrupt Status
bits : 8 - 16 (9 bit)
Interrupt Mask Control
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_IMC_BORIM : Brown-Out Reset Interrupt Mask
bits : 1 - 2 (2 bit)
SYSCTL_IMC_PLLLIM : PLL Lock Interrupt Mask
bits : 6 - 12 (7 bit)
SYSCTL_IMC_USBPLLLIM : USB PLL Lock Interrupt Mask
bits : 7 - 14 (8 bit)
SYSCTL_IMC_MOSCPUPIM : MOSC Power Up Interrupt Mask
bits : 8 - 16 (9 bit)
Interrupt Mask Control
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_IMC_BORIM : Brown-Out Reset Interrupt Mask
bits : 1 - 2 (2 bit)
SYSCTL_IMC_PLLLIM : PLL Lock Interrupt Mask
bits : 6 - 12 (7 bit)
SYSCTL_IMC_USBPLLLIM : USB PLL Lock Interrupt Mask
bits : 7 - 14 (8 bit)
SYSCTL_IMC_MOSCPUPIM : MOSC Power Up Interrupt Mask
bits : 8 - 16 (9 bit)
Masked Interrupt Status and Clear
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_MISC_BORMIS : BOR Masked Interrupt Status
bits : 1 - 2 (2 bit)
SYSCTL_MISC_PLLLMIS : PLL Lock Masked Interrupt Status
bits : 6 - 12 (7 bit)
SYSCTL_MISC_USBPLLLMIS : USB PLL Lock Masked Interrupt Status
bits : 7 - 14 (8 bit)
SYSCTL_MISC_MOSCPUPMIS : MOSC Power Up Masked Interrupt Status
bits : 8 - 16 (9 bit)
Masked Interrupt Status and Clear
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_MISC_BORMIS : BOR Masked Interrupt Status
bits : 1 - 2 (2 bit)
SYSCTL_MISC_PLLLMIS : PLL Lock Masked Interrupt Status
bits : 6 - 12 (7 bit)
SYSCTL_MISC_USBPLLLMIS : USB PLL Lock Masked Interrupt Status
bits : 7 - 14 (8 bit)
SYSCTL_MISC_MOSCPUPMIS : MOSC Power Up Masked Interrupt Status
bits : 8 - 16 (9 bit)
Reset Cause
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RESC_EXT : External Reset
bits : 0 - 0 (1 bit)
SYSCTL_RESC_POR : Power-On Reset
bits : 1 - 2 (2 bit)
SYSCTL_RESC_BOR : Brown-Out Reset
bits : 2 - 4 (3 bit)
SYSCTL_RESC_WDT0 : Watchdog Timer 0 Reset
bits : 3 - 6 (4 bit)
SYSCTL_RESC_SW : Software Reset
bits : 4 - 8 (5 bit)
SYSCTL_RESC_WDT1 : Watchdog Timer 1 Reset
bits : 5 - 10 (6 bit)
SYSCTL_RESC_MOSCFAIL : MOSC Failure Reset
bits : 16 - 32 (17 bit)
Reset Cause
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RESC_EXT : External Reset
bits : 0 - 0 (1 bit)
SYSCTL_RESC_POR : Power-On Reset
bits : 1 - 2 (2 bit)
SYSCTL_RESC_BOR : Brown-Out Reset
bits : 2 - 4 (3 bit)
SYSCTL_RESC_WDT0 : Watchdog Timer 0 Reset
bits : 3 - 6 (4 bit)
SYSCTL_RESC_SW : Software Reset
bits : 4 - 8 (5 bit)
SYSCTL_RESC_WDT1 : Watchdog Timer 1 Reset
bits : 5 - 10 (6 bit)
SYSCTL_RESC_MOSCFAIL : MOSC Failure Reset
bits : 16 - 32 (17 bit)
Run-Mode Clock Configuration
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCC_MOSCDIS : Main Oscillator Disable
bits : 0 - 0 (1 bit)
SYSCTL_RCC_IOSCDIS : Internal Oscillator Disable
bits : 1 - 2 (2 bit)
SYSCTL_RCC_OSCSRC : Oscillator Source
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : SYSCTL_RCC_OSCSRC_MAIN
MOSC
0x1 : SYSCTL_RCC_OSCSRC_INT
IOSC
0x2 : SYSCTL_RCC_OSCSRC_INT4
IOSC/4
0x3 : SYSCTL_RCC_OSCSRC_30
30 kHz
End of enumeration elements list.
SYSCTL_RCC_XTAL : Crystal Value
bits : 6 - 16 (11 bit)
Enumeration:
0x0 : SYSCTL_RCC_XTAL_1MHZ
1 MHz
0x1 : SYSCTL_RCC_XTAL_1_84MHZ
1.8432 MHz
0x2 : SYSCTL_RCC_XTAL_2MHZ
2 MHz
0x3 : SYSCTL_RCC_XTAL_2_45MHZ
2.4576 MHz
0x4 : SYSCTL_RCC_XTAL_3_57MHZ
3.579545 MHz
0x5 : SYSCTL_RCC_XTAL_3_68MHZ
3.6864 MHz
0x6 : SYSCTL_RCC_XTAL_4MHZ
4 MHz
0x7 : SYSCTL_RCC_XTAL_4_09MHZ
4.096 MHz
0x8 : SYSCTL_RCC_XTAL_4_91MHZ
4.9152 MHz
0x9 : SYSCTL_RCC_XTAL_5MHZ
5 MHz
0xa : SYSCTL_RCC_XTAL_5_12MHZ
5.12 MHz
0xb : SYSCTL_RCC_XTAL_6MHZ
6 MHz
0xc : SYSCTL_RCC_XTAL_6_14MHZ
6.144 MHz
0xd : SYSCTL_RCC_XTAL_7_37MHZ
7.3728 MHz
0xe : SYSCTL_RCC_XTAL_8MHZ
8 MHz
0xf : SYSCTL_RCC_XTAL_8_19MHZ
8.192 MHz
0x10 : SYSCTL_RCC_XTAL_10MHZ
10 MHz
0x11 : SYSCTL_RCC_XTAL_12MHZ
12 MHz
0x12 : SYSCTL_RCC_XTAL_12_2MHZ
12.288 MHz
0x13 : SYSCTL_RCC_XTAL_13_5MHZ
13.56 MHz
0x14 : SYSCTL_RCC_XTAL_14_3MHZ
14.31818 MHz
0x15 : SYSCTL_RCC_XTAL_16MHZ
16 MHz
0x16 : SYSCTL_RCC_XTAL_16_3MHZ
16.384 MHz
End of enumeration elements list.
SYSCTL_RCC_BYPASS : PLL Bypass
bits : 11 - 22 (12 bit)
SYSCTL_RCC_PWRDN : PLL Power Down
bits : 13 - 26 (14 bit)
SYSCTL_RCC_PWMDIV : PWM Unit Clock Divisor
bits : 17 - 36 (20 bit)
Enumeration:
0x0 : SYSCTL_RCC_PWMDIV_2
PWM clock /2
0x1 : SYSCTL_RCC_PWMDIV_4
PWM clock /4
0x2 : SYSCTL_RCC_PWMDIV_8
PWM clock /8
0x3 : SYSCTL_RCC_PWMDIV_16
PWM clock /16
0x4 : SYSCTL_RCC_PWMDIV_32
PWM clock /32
0x5 : SYSCTL_RCC_PWMDIV_64
PWM clock /64
End of enumeration elements list.
SYSCTL_RCC_USEPWMDIV : Enable PWM Clock Divisor
bits : 20 - 40 (21 bit)
SYSCTL_RCC_USESYSDIV : Enable System Clock Divider
bits : 22 - 44 (23 bit)
SYSCTL_RCC_SYSDIV : System Clock Divisor
bits : 23 - 49 (27 bit)
Enumeration:
0x1 : SYSCTL_RCC_SYSDIV_2
System clock /2
0x2 : SYSCTL_RCC_SYSDIV_3
System clock /3
0x3 : SYSCTL_RCC_SYSDIV_4
System clock /4
0x4 : SYSCTL_RCC_SYSDIV_5
System clock /5
0x5 : SYSCTL_RCC_SYSDIV_6
System clock /6
0x6 : SYSCTL_RCC_SYSDIV_7
System clock /7
0x7 : SYSCTL_RCC_SYSDIV_8
System clock /8
0x8 : SYSCTL_RCC_SYSDIV_9
System clock /9
0x9 : SYSCTL_RCC_SYSDIV_10
System clock /10
0xa : SYSCTL_RCC_SYSDIV_11
System clock /11
0xb : SYSCTL_RCC_SYSDIV_12
System clock /12
0xc : SYSCTL_RCC_SYSDIV_13
System clock /13
0xd : SYSCTL_RCC_SYSDIV_14
System clock /14
0xe : SYSCTL_RCC_SYSDIV_15
System clock /15
0xf : SYSCTL_RCC_SYSDIV_16
System clock /16
End of enumeration elements list.
SYSCTL_RCC_ACG : Auto Clock Gating
bits : 27 - 54 (28 bit)
Run-Mode Clock Configuration
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCC_MOSCDIS : Main Oscillator Disable
bits : 0 - 0 (1 bit)
SYSCTL_RCC_IOSCDIS : Internal Oscillator Disable
bits : 1 - 2 (2 bit)
SYSCTL_RCC_OSCSRC : Oscillator Source
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : SYSCTL_RCC_OSCSRC_MAIN
MOSC
0x1 : SYSCTL_RCC_OSCSRC_INT
IOSC
0x2 : SYSCTL_RCC_OSCSRC_INT4
IOSC/4
0x3 : SYSCTL_RCC_OSCSRC_30
30 kHz
End of enumeration elements list.
SYSCTL_RCC_XTAL : Crystal Value
bits : 6 - 16 (11 bit)
Enumeration:
0x0 : SYSCTL_RCC_XTAL_1MHZ
1 MHz
0x1 : SYSCTL_RCC_XTAL_1_84MHZ
1.8432 MHz
0x2 : SYSCTL_RCC_XTAL_2MHZ
2 MHz
0x3 : SYSCTL_RCC_XTAL_2_45MHZ
2.4576 MHz
0x4 : SYSCTL_RCC_XTAL_3_57MHZ
3.579545 MHz
0x5 : SYSCTL_RCC_XTAL_3_68MHZ
3.6864 MHz
0x6 : SYSCTL_RCC_XTAL_4MHZ
4 MHz
0x7 : SYSCTL_RCC_XTAL_4_09MHZ
4.096 MHz
0x8 : SYSCTL_RCC_XTAL_4_91MHZ
4.9152 MHz
0x9 : SYSCTL_RCC_XTAL_5MHZ
5 MHz
0xa : SYSCTL_RCC_XTAL_5_12MHZ
5.12 MHz
0xb : SYSCTL_RCC_XTAL_6MHZ
6 MHz
0xc : SYSCTL_RCC_XTAL_6_14MHZ
6.144 MHz
0xd : SYSCTL_RCC_XTAL_7_37MHZ
7.3728 MHz
0xe : SYSCTL_RCC_XTAL_8MHZ
8 MHz
0xf : SYSCTL_RCC_XTAL_8_19MHZ
8.192 MHz
0x10 : SYSCTL_RCC_XTAL_10MHZ
10 MHz
0x11 : SYSCTL_RCC_XTAL_12MHZ
12 MHz
0x12 : SYSCTL_RCC_XTAL_12_2MHZ
12.288 MHz
0x13 : SYSCTL_RCC_XTAL_13_5MHZ
13.56 MHz
0x14 : SYSCTL_RCC_XTAL_14_3MHZ
14.31818 MHz
0x15 : SYSCTL_RCC_XTAL_16MHZ
16 MHz
0x16 : SYSCTL_RCC_XTAL_16_3MHZ
16.384 MHz
End of enumeration elements list.
SYSCTL_RCC_BYPASS : PLL Bypass
bits : 11 - 22 (12 bit)
SYSCTL_RCC_PWRDN : PLL Power Down
bits : 13 - 26 (14 bit)
SYSCTL_RCC_PWMDIV : PWM Unit Clock Divisor
bits : 17 - 36 (20 bit)
Enumeration:
0x0 : SYSCTL_RCC_PWMDIV_2
PWM clock /2
0x1 : SYSCTL_RCC_PWMDIV_4
PWM clock /4
0x2 : SYSCTL_RCC_PWMDIV_8
PWM clock /8
0x3 : SYSCTL_RCC_PWMDIV_16
PWM clock /16
0x4 : SYSCTL_RCC_PWMDIV_32
PWM clock /32
0x5 : SYSCTL_RCC_PWMDIV_64
PWM clock /64
End of enumeration elements list.
SYSCTL_RCC_USEPWMDIV : Enable PWM Clock Divisor
bits : 20 - 40 (21 bit)
SYSCTL_RCC_USESYSDIV : Enable System Clock Divider
bits : 22 - 44 (23 bit)
SYSCTL_RCC_SYSDIV : System Clock Divisor
bits : 23 - 49 (27 bit)
Enumeration:
0x1 : SYSCTL_RCC_SYSDIV_2
System clock /2
0x2 : SYSCTL_RCC_SYSDIV_3
System clock /3
0x3 : SYSCTL_RCC_SYSDIV_4
System clock /4
0x4 : SYSCTL_RCC_SYSDIV_5
System clock /5
0x5 : SYSCTL_RCC_SYSDIV_6
System clock /6
0x6 : SYSCTL_RCC_SYSDIV_7
System clock /7
0x7 : SYSCTL_RCC_SYSDIV_8
System clock /8
0x8 : SYSCTL_RCC_SYSDIV_9
System clock /9
0x9 : SYSCTL_RCC_SYSDIV_10
System clock /10
0xa : SYSCTL_RCC_SYSDIV_11
System clock /11
0xb : SYSCTL_RCC_SYSDIV_12
System clock /12
0xc : SYSCTL_RCC_SYSDIV_13
System clock /13
0xd : SYSCTL_RCC_SYSDIV_14
System clock /14
0xe : SYSCTL_RCC_SYSDIV_15
System clock /15
0xf : SYSCTL_RCC_SYSDIV_16
System clock /16
End of enumeration elements list.
SYSCTL_RCC_ACG : Auto Clock Gating
bits : 27 - 54 (28 bit)
XTAL to PLL Translation
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PLLCFG_R : PLL R Value
bits : 0 - 4 (5 bit)
SYSCTL_PLLCFG_F : PLL F Value
bits : 5 - 18 (14 bit)
XTAL to PLL Translation
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PLLCFG_R : PLL R Value
bits : 0 - 4 (5 bit)
SYSCTL_PLLCFG_F : PLL F Value
bits : 5 - 18 (14 bit)
GPIO High-Performance Bus Control
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_GPIOHBCTL_PORTA : Port A Advanced High-Performance Bus
bits : 0 - 0 (1 bit)
SYSCTL_GPIOHBCTL_PORTB : Port B Advanced High-Performance Bus
bits : 1 - 2 (2 bit)
SYSCTL_GPIOHBCTL_PORTC : Port C Advanced High-Performance Bus
bits : 2 - 4 (3 bit)
SYSCTL_GPIOHBCTL_PORTD : Port D Advanced High-Performance Bus
bits : 3 - 6 (4 bit)
SYSCTL_GPIOHBCTL_PORTE : Port E Advanced High-Performance Bus
bits : 4 - 8 (5 bit)
SYSCTL_GPIOHBCTL_PORTF : Port F Advanced High-Performance Bus
bits : 5 - 10 (6 bit)
SYSCTL_GPIOHBCTL_PORTG : Port G Advanced High-Performance Bus
bits : 6 - 12 (7 bit)
SYSCTL_GPIOHBCTL_PORTH : Port H Advanced High-Performance Bus
bits : 7 - 14 (8 bit)
SYSCTL_GPIOHBCTL_PORTJ : Port J Advanced High-Performance Bus
bits : 8 - 16 (9 bit)
GPIO High-Performance Bus Control
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_GPIOHBCTL_PORTA : Port A Advanced High-Performance Bus
bits : 0 - 0 (1 bit)
SYSCTL_GPIOHBCTL_PORTB : Port B Advanced High-Performance Bus
bits : 1 - 2 (2 bit)
SYSCTL_GPIOHBCTL_PORTC : Port C Advanced High-Performance Bus
bits : 2 - 4 (3 bit)
SYSCTL_GPIOHBCTL_PORTD : Port D Advanced High-Performance Bus
bits : 3 - 6 (4 bit)
SYSCTL_GPIOHBCTL_PORTE : Port E Advanced High-Performance Bus
bits : 4 - 8 (5 bit)
SYSCTL_GPIOHBCTL_PORTF : Port F Advanced High-Performance Bus
bits : 5 - 10 (6 bit)
SYSCTL_GPIOHBCTL_PORTG : Port G Advanced High-Performance Bus
bits : 6 - 12 (7 bit)
SYSCTL_GPIOHBCTL_PORTH : Port H Advanced High-Performance Bus
bits : 7 - 14 (8 bit)
SYSCTL_GPIOHBCTL_PORTJ : Port J Advanced High-Performance Bus
bits : 8 - 16 (9 bit)
Run-Mode Clock Configuration 2
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCC2_OSCSRC2 : Oscillator Source 2
bits : 4 - 10 (7 bit)
Enumeration:
0x0 : SYSCTL_RCC2_OSCSRC2_MO
MOSC
0x1 : SYSCTL_RCC2_OSCSRC2_IO
PIOSC
0x2 : SYSCTL_RCC2_OSCSRC2_IO4
PIOSC/4
0x3 : SYSCTL_RCC2_OSCSRC2_30
30 kHz
End of enumeration elements list.
SYSCTL_RCC2_BYPASS2 : PLL Bypass 2
bits : 11 - 22 (12 bit)
SYSCTL_RCC2_PWRDN2 : Power-Down PLL 2
bits : 13 - 26 (14 bit)
SYSCTL_RCC2_USBPWRDN : Power-Down USB PLL
bits : 14 - 28 (15 bit)
SYSCTL_RCC2_SYSDIV2LSB : Additional LSB for SYSDIV2
bits : 22 - 44 (23 bit)
SYSCTL_RCC2_SYSDIV2 : System Clock Divisor 2
bits : 23 - 51 (29 bit)
Enumeration:
0x1 : SYSCTL_RCC2_SYSDIV2_2
System clock /2
0x2 : SYSCTL_RCC2_SYSDIV2_3
System clock /3
0x3 : SYSCTL_RCC2_SYSDIV2_4
System clock /4
0x4 : SYSCTL_RCC2_SYSDIV2_5
System clock /5
0x5 : SYSCTL_RCC2_SYSDIV2_6
System clock /6
0x6 : SYSCTL_RCC2_SYSDIV2_7
System clock /7
0x7 : SYSCTL_RCC2_SYSDIV2_8
System clock /8
0x8 : SYSCTL_RCC2_SYSDIV2_9
System clock /9
0x9 : SYSCTL_RCC2_SYSDIV2_10
System clock /10
0xa : SYSCTL_RCC2_SYSDIV2_11
System clock /11
0xb : SYSCTL_RCC2_SYSDIV2_12
System clock /12
0xc : SYSCTL_RCC2_SYSDIV2_13
System clock /13
0xd : SYSCTL_RCC2_SYSDIV2_14
System clock /14
0xe : SYSCTL_RCC2_SYSDIV2_15
System clock /15
0xf : SYSCTL_RCC2_SYSDIV2_16
System clock /16
0x10 : SYSCTL_RCC2_SYSDIV2_17
System clock /17
0x11 : SYSCTL_RCC2_SYSDIV2_18
System clock /18
0x12 : SYSCTL_RCC2_SYSDIV2_19
System clock /19
0x13 : SYSCTL_RCC2_SYSDIV2_20
System clock /20
0x14 : SYSCTL_RCC2_SYSDIV2_21
System clock /21
0x15 : SYSCTL_RCC2_SYSDIV2_22
System clock /22
0x16 : SYSCTL_RCC2_SYSDIV2_23
System clock /23
0x17 : SYSCTL_RCC2_SYSDIV2_24
System clock /24
0x18 : SYSCTL_RCC2_SYSDIV2_25
System clock /25
0x19 : SYSCTL_RCC2_SYSDIV2_26
System clock /26
0x1a : SYSCTL_RCC2_SYSDIV2_27
System clock /27
0x1b : SYSCTL_RCC2_SYSDIV2_28
System clock /28
0x1c : SYSCTL_RCC2_SYSDIV2_29
System clock /29
0x1d : SYSCTL_RCC2_SYSDIV2_30
System clock /30
0x1e : SYSCTL_RCC2_SYSDIV2_31
System clock /31
0x1f : SYSCTL_RCC2_SYSDIV2_32
System clock /32
0x20 : SYSCTL_RCC2_SYSDIV2_33
System clock /33
0x21 : SYSCTL_RCC2_SYSDIV2_34
System clock /34
0x22 : SYSCTL_RCC2_SYSDIV2_35
System clock /35
0x23 : SYSCTL_RCC2_SYSDIV2_36
System clock /36
0x24 : SYSCTL_RCC2_SYSDIV2_37
System clock /37
0x25 : SYSCTL_RCC2_SYSDIV2_38
System clock /38
0x26 : SYSCTL_RCC2_SYSDIV2_39
System clock /39
0x27 : SYSCTL_RCC2_SYSDIV2_40
System clock /40
0x28 : SYSCTL_RCC2_SYSDIV2_41
System clock /41
0x29 : SYSCTL_RCC2_SYSDIV2_42
System clock /42
0x2a : SYSCTL_RCC2_SYSDIV2_43
System clock /43
0x2b : SYSCTL_RCC2_SYSDIV2_44
System clock /44
0x2c : SYSCTL_RCC2_SYSDIV2_45
System clock /45
0x2d : SYSCTL_RCC2_SYSDIV2_46
System clock /46
0x2e : SYSCTL_RCC2_SYSDIV2_47
System clock /47
0x2f : SYSCTL_RCC2_SYSDIV2_48
System clock /48
0x30 : SYSCTL_RCC2_SYSDIV2_49
System clock /49
0x31 : SYSCTL_RCC2_SYSDIV2_50
System clock /50
0x32 : SYSCTL_RCC2_SYSDIV2_51
System clock /51
0x33 : SYSCTL_RCC2_SYSDIV2_52
System clock /52
0x34 : SYSCTL_RCC2_SYSDIV2_53
System clock /53
0x35 : SYSCTL_RCC2_SYSDIV2_54
System clock /54
0x36 : SYSCTL_RCC2_SYSDIV2_55
System clock /55
0x37 : SYSCTL_RCC2_SYSDIV2_56
System clock /56
0x38 : SYSCTL_RCC2_SYSDIV2_57
System clock /57
0x39 : SYSCTL_RCC2_SYSDIV2_58
System clock /58
0x3a : SYSCTL_RCC2_SYSDIV2_59
System clock /59
0x3b : SYSCTL_RCC2_SYSDIV2_60
System clock /60
0x3c : SYSCTL_RCC2_SYSDIV2_61
System clock /61
0x3d : SYSCTL_RCC2_SYSDIV2_62
System clock /62
0x3e : SYSCTL_RCC2_SYSDIV2_63
System clock /63
0x3f : SYSCTL_RCC2_SYSDIV2_64
System clock /64
End of enumeration elements list.
SYSCTL_RCC2_DIV400 : Divide PLL as 400 MHz vs. 200 MHz
bits : 30 - 60 (31 bit)
SYSCTL_RCC2_USERCC2 : Use RCC2
bits : 31 - 62 (32 bit)
Run-Mode Clock Configuration 2
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCC2_OSCSRC2 : Oscillator Source 2
bits : 4 - 10 (7 bit)
Enumeration:
0x0 : SYSCTL_RCC2_OSCSRC2_MO
MOSC
0x1 : SYSCTL_RCC2_OSCSRC2_IO
PIOSC
0x2 : SYSCTL_RCC2_OSCSRC2_IO4
PIOSC/4
0x3 : SYSCTL_RCC2_OSCSRC2_30
30 kHz
End of enumeration elements list.
SYSCTL_RCC2_BYPASS2 : PLL Bypass 2
bits : 11 - 22 (12 bit)
SYSCTL_RCC2_PWRDN2 : Power-Down PLL 2
bits : 13 - 26 (14 bit)
SYSCTL_RCC2_USBPWRDN : Power-Down USB PLL
bits : 14 - 28 (15 bit)
SYSCTL_RCC2_SYSDIV2LSB : Additional LSB for SYSDIV2
bits : 22 - 44 (23 bit)
SYSCTL_RCC2_SYSDIV2 : System Clock Divisor 2
bits : 23 - 51 (29 bit)
Enumeration:
0x1 : SYSCTL_RCC2_SYSDIV2_2
System clock /2
0x2 : SYSCTL_RCC2_SYSDIV2_3
System clock /3
0x3 : SYSCTL_RCC2_SYSDIV2_4
System clock /4
0x4 : SYSCTL_RCC2_SYSDIV2_5
System clock /5
0x5 : SYSCTL_RCC2_SYSDIV2_6
System clock /6
0x6 : SYSCTL_RCC2_SYSDIV2_7
System clock /7
0x7 : SYSCTL_RCC2_SYSDIV2_8
System clock /8
0x8 : SYSCTL_RCC2_SYSDIV2_9
System clock /9
0x9 : SYSCTL_RCC2_SYSDIV2_10
System clock /10
0xa : SYSCTL_RCC2_SYSDIV2_11
System clock /11
0xb : SYSCTL_RCC2_SYSDIV2_12
System clock /12
0xc : SYSCTL_RCC2_SYSDIV2_13
System clock /13
0xd : SYSCTL_RCC2_SYSDIV2_14
System clock /14
0xe : SYSCTL_RCC2_SYSDIV2_15
System clock /15
0xf : SYSCTL_RCC2_SYSDIV2_16
System clock /16
0x10 : SYSCTL_RCC2_SYSDIV2_17
System clock /17
0x11 : SYSCTL_RCC2_SYSDIV2_18
System clock /18
0x12 : SYSCTL_RCC2_SYSDIV2_19
System clock /19
0x13 : SYSCTL_RCC2_SYSDIV2_20
System clock /20
0x14 : SYSCTL_RCC2_SYSDIV2_21
System clock /21
0x15 : SYSCTL_RCC2_SYSDIV2_22
System clock /22
0x16 : SYSCTL_RCC2_SYSDIV2_23
System clock /23
0x17 : SYSCTL_RCC2_SYSDIV2_24
System clock /24
0x18 : SYSCTL_RCC2_SYSDIV2_25
System clock /25
0x19 : SYSCTL_RCC2_SYSDIV2_26
System clock /26
0x1a : SYSCTL_RCC2_SYSDIV2_27
System clock /27
0x1b : SYSCTL_RCC2_SYSDIV2_28
System clock /28
0x1c : SYSCTL_RCC2_SYSDIV2_29
System clock /29
0x1d : SYSCTL_RCC2_SYSDIV2_30
System clock /30
0x1e : SYSCTL_RCC2_SYSDIV2_31
System clock /31
0x1f : SYSCTL_RCC2_SYSDIV2_32
System clock /32
0x20 : SYSCTL_RCC2_SYSDIV2_33
System clock /33
0x21 : SYSCTL_RCC2_SYSDIV2_34
System clock /34
0x22 : SYSCTL_RCC2_SYSDIV2_35
System clock /35
0x23 : SYSCTL_RCC2_SYSDIV2_36
System clock /36
0x24 : SYSCTL_RCC2_SYSDIV2_37
System clock /37
0x25 : SYSCTL_RCC2_SYSDIV2_38
System clock /38
0x26 : SYSCTL_RCC2_SYSDIV2_39
System clock /39
0x27 : SYSCTL_RCC2_SYSDIV2_40
System clock /40
0x28 : SYSCTL_RCC2_SYSDIV2_41
System clock /41
0x29 : SYSCTL_RCC2_SYSDIV2_42
System clock /42
0x2a : SYSCTL_RCC2_SYSDIV2_43
System clock /43
0x2b : SYSCTL_RCC2_SYSDIV2_44
System clock /44
0x2c : SYSCTL_RCC2_SYSDIV2_45
System clock /45
0x2d : SYSCTL_RCC2_SYSDIV2_46
System clock /46
0x2e : SYSCTL_RCC2_SYSDIV2_47
System clock /47
0x2f : SYSCTL_RCC2_SYSDIV2_48
System clock /48
0x30 : SYSCTL_RCC2_SYSDIV2_49
System clock /49
0x31 : SYSCTL_RCC2_SYSDIV2_50
System clock /50
0x32 : SYSCTL_RCC2_SYSDIV2_51
System clock /51
0x33 : SYSCTL_RCC2_SYSDIV2_52
System clock /52
0x34 : SYSCTL_RCC2_SYSDIV2_53
System clock /53
0x35 : SYSCTL_RCC2_SYSDIV2_54
System clock /54
0x36 : SYSCTL_RCC2_SYSDIV2_55
System clock /55
0x37 : SYSCTL_RCC2_SYSDIV2_56
System clock /56
0x38 : SYSCTL_RCC2_SYSDIV2_57
System clock /57
0x39 : SYSCTL_RCC2_SYSDIV2_58
System clock /58
0x3a : SYSCTL_RCC2_SYSDIV2_59
System clock /59
0x3b : SYSCTL_RCC2_SYSDIV2_60
System clock /60
0x3c : SYSCTL_RCC2_SYSDIV2_61
System clock /61
0x3d : SYSCTL_RCC2_SYSDIV2_62
System clock /62
0x3e : SYSCTL_RCC2_SYSDIV2_63
System clock /63
0x3f : SYSCTL_RCC2_SYSDIV2_64
System clock /64
End of enumeration elements list.
SYSCTL_RCC2_DIV400 : Divide PLL as 400 MHz vs. 200 MHz
bits : 30 - 60 (31 bit)
SYSCTL_RCC2_USERCC2 : Use RCC2
bits : 31 - 62 (32 bit)
Main Oscillator Control
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_MOSCCTL_CVAL : Clock Validation for MOSC
bits : 0 - 0 (1 bit)
Main Oscillator Control
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_MOSCCTL_CVAL : Clock Validation for MOSC
bits : 0 - 0 (1 bit)
Device Capabilities 0
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC0_FLASHSZ : Flash Size
bits : 0 - 15 (16 bit)
Enumeration:
0x7f : SYSCTL_DC0_FLASHSZ_256K
256 KB of Flash
End of enumeration elements list.
SYSCTL_DC0_SRAMSZ : SRAM Size
bits : 16 - 47 (32 bit)
Enumeration:
0x17f : SYSCTL_DC0_SRAMSZ_96KB
96 KB of SRAM
End of enumeration elements list.
Device Capabilities 0
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DC0_FLASHSZ : Flash Size
bits : 0 - 15 (16 bit)
Enumeration:
0x7f : SYSCTL_DC0_FLASHSZ_256K
256 KB of Flash
End of enumeration elements list.
SYSCTL_DC0_SRAMSZ : SRAM Size
bits : 16 - 47 (32 bit)
Enumeration:
0x17f : SYSCTL_DC0_SRAMSZ_96KB
96 KB of SRAM
End of enumeration elements list.
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