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MAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MACRIS

RIS

MACDATA

DATA

MACIA0

IA0

MACIA1

IA1

MACTHR

THR

MACMCTL

MCTL

MACMDV

MDV

MACMTXD

MTXD

MACMRXD

MRXD

MACNP

NP

MACTR

TR

MACTS

TS

MACIM

IM

MACLED

LED

MACMDIX

MDIX

MACRCTL

RCTL

MACTCTL

TCTL


MACRIS

Ethernet MAC Raw Interrupt Status/Acknowledge
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACRIS MACRIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_RIS_RXINT MAC_RIS_TXER MAC_RIS_TXEMP MAC_RIS_FOV MAC_RIS_RXER MAC_RIS_MDINT MAC_RIS_PHYINT

MAC_RIS_RXINT : Packet Received
bits : 0 - 0 (1 bit)

MAC_RIS_TXER : Transmit Error
bits : 1 - 2 (2 bit)

MAC_RIS_TXEMP : Transmit FIFO Empty
bits : 2 - 4 (3 bit)

MAC_RIS_FOV : FIFO Overrun
bits : 3 - 6 (4 bit)

MAC_RIS_RXER : Receive Error
bits : 4 - 8 (5 bit)

MAC_RIS_MDINT : MII Transaction Complete
bits : 5 - 10 (6 bit)

MAC_RIS_PHYINT : PHY Interrupt
bits : 6 - 12 (7 bit)


RIS

Ethernet MAC Raw Interrupt Status/Acknowledge
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_RIS_RXINT MAC_RIS_TXER MAC_RIS_TXEMP MAC_RIS_FOV MAC_RIS_RXER MAC_RIS_MDINT MAC_RIS_PHYINT

MAC_RIS_RXINT : Packet Received
bits : 0 - 0 (1 bit)

MAC_RIS_TXER : Transmit Error
bits : 1 - 2 (2 bit)

MAC_RIS_TXEMP : Transmit FIFO Empty
bits : 2 - 4 (3 bit)

MAC_RIS_FOV : FIFO Overrun
bits : 3 - 6 (4 bit)

MAC_RIS_RXER : Receive Error
bits : 4 - 8 (5 bit)

MAC_RIS_MDINT : MII Transaction Complete
bits : 5 - 10 (6 bit)

MAC_RIS_PHYINT : PHY Interrupt
bits : 6 - 12 (7 bit)


MACDATA

Ethernet MAC Data
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACDATA MACDATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_DATA_RXDATA

MAC_DATA_RXDATA : Receive FIFO Data
bits : 0 - 31 (32 bit)


DATA

Ethernet MAC Data
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_DATA_RXDATA MAC_DATA_TXDATA

MAC_DATA_RXDATA : Receive FIFO Data
bits : 0 - 31 (32 bit)

MAC_DATA_TXDATA : Transmit FIFO Data
bits : 0 - 31 (32 bit)


MACIA0

Ethernet MAC Individual Address 0
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACIA0 MACIA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_IA0_MACOCT1 MAC_IA0_MACOCT2 MAC_IA0_MACOCT3 MAC_IA0_MACOCT4

MAC_IA0_MACOCT1 : MAC Address Octet 1
bits : 0 - 7 (8 bit)

MAC_IA0_MACOCT2 : MAC Address Octet 2
bits : 8 - 23 (16 bit)

MAC_IA0_MACOCT3 : MAC Address Octet 3
bits : 16 - 39 (24 bit)

MAC_IA0_MACOCT4 : MAC Address Octet 4
bits : 24 - 55 (32 bit)


IA0

Ethernet MAC Individual Address 0
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IA0 IA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_IA0_MACOCT1 MAC_IA0_MACOCT2 MAC_IA0_MACOCT3 MAC_IA0_MACOCT4

MAC_IA0_MACOCT1 : MAC Address Octet 1
bits : 0 - 7 (8 bit)

MAC_IA0_MACOCT2 : MAC Address Octet 2
bits : 8 - 23 (16 bit)

MAC_IA0_MACOCT3 : MAC Address Octet 3
bits : 16 - 39 (24 bit)

MAC_IA0_MACOCT4 : MAC Address Octet 4
bits : 24 - 55 (32 bit)


MACIA1

Ethernet MAC Individual Address 1
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACIA1 MACIA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_IA1_MACOCT5 MAC_IA1_MACOCT6

MAC_IA1_MACOCT5 : MAC Address Octet 5
bits : 0 - 7 (8 bit)

MAC_IA1_MACOCT6 : MAC Address Octet 6
bits : 8 - 23 (16 bit)


IA1

Ethernet MAC Individual Address 1
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IA1 IA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_IA1_MACOCT5 MAC_IA1_MACOCT6

MAC_IA1_MACOCT5 : MAC Address Octet 5
bits : 0 - 7 (8 bit)

MAC_IA1_MACOCT6 : MAC Address Octet 6
bits : 8 - 23 (16 bit)


MACTHR

Ethernet MAC Threshold
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACTHR MACTHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_THR_THRESH

MAC_THR_THRESH : Threshold Value
bits : 0 - 5 (6 bit)


THR

Ethernet MAC Threshold
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

THR THR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_THR_THRESH

MAC_THR_THRESH : Threshold Value
bits : 0 - 5 (6 bit)


MACMCTL

Ethernet MAC Management Control
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACMCTL MACMCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_MCTL_START MAC_MCTL_WRITE MAC_MCTL_REGADR

MAC_MCTL_START : MII Register Transaction Enable
bits : 0 - 0 (1 bit)

MAC_MCTL_WRITE : MII Register Transaction Type
bits : 1 - 2 (2 bit)

MAC_MCTL_REGADR : MII Register Address
bits : 3 - 10 (8 bit)


MCTL

Ethernet MAC Management Control
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL MCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_MCTL_START MAC_MCTL_WRITE MAC_MCTL_REGADR

MAC_MCTL_START : MII Register Transaction Enable
bits : 0 - 0 (1 bit)

MAC_MCTL_WRITE : MII Register Transaction Type
bits : 1 - 2 (2 bit)

MAC_MCTL_REGADR : MII Register Address
bits : 3 - 10 (8 bit)


MACMDV

Ethernet MAC Management Divider
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACMDV MACMDV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_MDV_DIV

MAC_MDV_DIV : Clock Divider
bits : 0 - 7 (8 bit)


MDV

Ethernet MAC Management Divider
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDV MDV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_MDV_DIV

MAC_MDV_DIV : Clock Divider
bits : 0 - 7 (8 bit)


MACMTXD

Ethernet MAC Management Transmit Data
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACMTXD MACMTXD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_MTXD_MDTX

MAC_MTXD_MDTX : MII Register Transmit Data
bits : 0 - 15 (16 bit)


MTXD

Ethernet MAC Management Transmit Data
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTXD MTXD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_MTXD_MDTX

MAC_MTXD_MDTX : MII Register Transmit Data
bits : 0 - 15 (16 bit)


MACMRXD

Ethernet MAC Management Receive Data
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACMRXD MACMRXD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_MRXD_MDRX

MAC_MRXD_MDRX : MII Register Receive Data
bits : 0 - 15 (16 bit)


MRXD

Ethernet MAC Management Receive Data
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MRXD MRXD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_MRXD_MDRX

MAC_MRXD_MDRX : MII Register Receive Data
bits : 0 - 15 (16 bit)


MACNP

Ethernet MAC Number of Packets
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACNP MACNP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_NP_NPR

MAC_NP_NPR : Number of Packets in Receive FIFO
bits : 0 - 5 (6 bit)


NP

Ethernet MAC Number of Packets
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NP NP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_NP_NPR

MAC_NP_NPR : Number of Packets in Receive FIFO
bits : 0 - 5 (6 bit)


MACTR

Ethernet MAC Transmission Request
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACTR MACTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_TR_NEWTX

MAC_TR_NEWTX : New Transmission
bits : 0 - 0 (1 bit)


TR

Ethernet MAC Transmission Request
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TR TR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_TR_NEWTX

MAC_TR_NEWTX : New Transmission
bits : 0 - 0 (1 bit)


MACTS

Ethernet MAC Timer Support
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACTS MACTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_TS_TSEN

MAC_TS_TSEN : Time Stamp Enable
bits : 0 - 0 (1 bit)


TS

Ethernet MAC Timer Support
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TS TS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_TS_TSEN

MAC_TS_TSEN : Time Stamp Enable
bits : 0 - 0 (1 bit)


MACIM

Ethernet MAC Interrupt Mask
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACIM MACIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_IM_RXINTM MAC_IM_TXERM MAC_IM_TXEMPM MAC_IM_FOVM MAC_IM_RXERM MAC_IM_MDINTM MAC_IM_PHYINTM

MAC_IM_RXINTM : Mask Packet Received
bits : 0 - 0 (1 bit)

MAC_IM_TXERM : Mask Transmit Error
bits : 1 - 2 (2 bit)

MAC_IM_TXEMPM : Mask Transmit FIFO Empty
bits : 2 - 4 (3 bit)

MAC_IM_FOVM : Mask FIFO Overrun
bits : 3 - 6 (4 bit)

MAC_IM_RXERM : Mask Receive Error
bits : 4 - 8 (5 bit)

MAC_IM_MDINTM : Mask MII Transaction Complete
bits : 5 - 10 (6 bit)

MAC_IM_PHYINTM : Mask PHY Interrupt
bits : 6 - 12 (7 bit)


IM

Ethernet MAC Interrupt Mask
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IM IM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_IM_RXINTM MAC_IM_TXERM MAC_IM_TXEMPM MAC_IM_FOVM MAC_IM_RXERM MAC_IM_MDINTM MAC_IM_PHYINTM

MAC_IM_RXINTM : Mask Packet Received
bits : 0 - 0 (1 bit)

MAC_IM_TXERM : Mask Transmit Error
bits : 1 - 2 (2 bit)

MAC_IM_TXEMPM : Mask Transmit FIFO Empty
bits : 2 - 4 (3 bit)

MAC_IM_FOVM : Mask FIFO Overrun
bits : 3 - 6 (4 bit)

MAC_IM_RXERM : Mask Receive Error
bits : 4 - 8 (5 bit)

MAC_IM_MDINTM : Mask MII Transaction Complete
bits : 5 - 10 (6 bit)

MAC_IM_PHYINTM : Mask PHY Interrupt
bits : 6 - 12 (7 bit)


MACLED

Ethernet MAC LED Encoding
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACLED MACLED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_LED_LED0 MAC_LED_LED1

MAC_LED_LED0 : LED0 Source
bits : 0 - 3 (4 bit)

Enumeration:

0x0 : MAC_LED_LED0_LINK

Link OK (Default LED0)

0x1 : MAC_LED_LED0_RXTX

RX or TX Activity

0x5 : MAC_LED_LED0_100

100BASE-TX mode

0x6 : MAC_LED_LED0_10

10BASE-T mode

0x7 : MAC_LED_LED0_DUPLEX

Full-Duplex

0x8 : MAC_LED_LED0_LINKACT

Link OK & Blink=RX or TX Activity

End of enumeration elements list.

MAC_LED_LED1 : LED1 Source
bits : 8 - 19 (12 bit)

Enumeration:

0x0 : MAC_LED_LED1_LINK

Link OK

0x1 : MAC_LED_LED1_RXTX

RX or TX Activity (Default LED1)

0x5 : MAC_LED_LED1_100

100BASE-TX mode

0x6 : MAC_LED_LED1_10

10BASE-T mode

0x7 : MAC_LED_LED1_DUPLEX

Full-Duplex

0x8 : MAC_LED_LED1_LINKACT

Link OK & Blink=RX or TX Activity

End of enumeration elements list.


LED

Ethernet MAC LED Encoding
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LED LED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_LED_LED0 MAC_LED_LED1

MAC_LED_LED0 : LED0 Source
bits : 0 - 3 (4 bit)

Enumeration:

0x0 : MAC_LED_LED0_LINK

Link OK (Default LED0)

0x1 : MAC_LED_LED0_RXTX

RX or TX Activity

0x5 : MAC_LED_LED0_100

100BASE-TX mode

0x6 : MAC_LED_LED0_10

10BASE-T mode

0x7 : MAC_LED_LED0_DUPLEX

Full-Duplex

0x8 : MAC_LED_LED0_LINKACT

Link OK and Blink=RX or TX Activity

End of enumeration elements list.

MAC_LED_LED1 : LED1 Source
bits : 8 - 19 (12 bit)

Enumeration:

0x0 : MAC_LED_LED1_LINK

Link OK

0x1 : MAC_LED_LED1_RXTX

RX or TX Activity (Default LED1)

0x5 : MAC_LED_LED1_100

100BASE-TX mode

0x6 : MAC_LED_LED1_10

10BASE-T mode

0x7 : MAC_LED_LED1_DUPLEX

Full-Duplex

0x8 : MAC_LED_LED1_LINKACT

Link OK and Blink=RX or TX Activity

End of enumeration elements list.


MACMDIX

Ethernet PHY MDIX
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACMDIX MACMDIX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_MDIX_EN

MAC_MDIX_EN : MDI/MDI-X Enable
bits : 0 - 0 (1 bit)


MDIX

Ethernet PHY MDIX
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDIX MDIX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_MDIX_EN

MAC_MDIX_EN : MDI/MDI-X Enable
bits : 0 - 0 (1 bit)


MACRCTL

Ethernet MAC Receive Control
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACRCTL MACRCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_RCTL_RXEN MAC_RCTL_AMUL MAC_RCTL_PRMS MAC_RCTL_BADCRC MAC_RCTL_RSTFIFO

MAC_RCTL_RXEN : Enable Receiver
bits : 0 - 0 (1 bit)

MAC_RCTL_AMUL : Enable Multicast Frames
bits : 1 - 2 (2 bit)

MAC_RCTL_PRMS : Enable Promiscuous Mode
bits : 2 - 4 (3 bit)

MAC_RCTL_BADCRC : Enable Reject Bad CRC
bits : 3 - 6 (4 bit)

MAC_RCTL_RSTFIFO : Clear Receive FIFO
bits : 4 - 8 (5 bit)


RCTL

Ethernet MAC Receive Control
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCTL RCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_RCTL_RXEN MAC_RCTL_AMUL MAC_RCTL_PRMS MAC_RCTL_BADCRC MAC_RCTL_RSTFIFO

MAC_RCTL_RXEN : Enable Receiver
bits : 0 - 0 (1 bit)

MAC_RCTL_AMUL : Enable Multicast Frames
bits : 1 - 2 (2 bit)

MAC_RCTL_PRMS : Enable Promiscuous Mode
bits : 2 - 4 (3 bit)

MAC_RCTL_BADCRC : Enable Reject Bad CRC
bits : 3 - 6 (4 bit)

MAC_RCTL_RSTFIFO : Clear Receive FIFO
bits : 4 - 8 (5 bit)


MACTCTL

Ethernet MAC Transmit Control
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACTCTL MACTCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_TCTL_TXEN MAC_TCTL_PADEN MAC_TCTL_CRC MAC_TCTL_DUPLEX

MAC_TCTL_TXEN : Enable Transmitter
bits : 0 - 0 (1 bit)

MAC_TCTL_PADEN : Enable Packet Padding
bits : 1 - 2 (2 bit)

MAC_TCTL_CRC : Enable CRC Generation
bits : 2 - 4 (3 bit)

MAC_TCTL_DUPLEX : Enable Duplex Mode
bits : 4 - 8 (5 bit)


TCTL

Ethernet MAC Transmit Control
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCTL TCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_TCTL_TXEN MAC_TCTL_PADEN MAC_TCTL_CRC MAC_TCTL_DUPLEX

MAC_TCTL_TXEN : Enable Transmitter
bits : 0 - 0 (1 bit)

MAC_TCTL_PADEN : Enable Packet Padding
bits : 1 - 2 (2 bit)

MAC_TCTL_CRC : Enable CRC Generation
bits : 2 - 4 (3 bit)

MAC_TCTL_DUPLEX : Enable Duplex Mode
bits : 4 - 8 (5 bit)



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