Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
I2S Transmit FIFO Data
address_offset : 0x0 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
I2S_TXFIFO : TX Data
bits : 0 - 31 (32 bit)
access : write-only
I2S Transmit FIFO Data
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
I2S_TXFIFO : TX Data
bits : 0 - 31 (32 bit)
access : write-only
I2S Transmit Interrupt Status and Mask
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_TXISM_FFM : FIFO Interrupt Mask
bits : 0 - 0 (1 bit)
I2S_TXISM_FFI : Transmit FIFO Service Request Interrupt
bits : 16 - 32 (17 bit)
I2S Transmit Interrupt Status and Mask
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_TXISM_FFM : FIFO Interrupt Mask
bits : 0 - 0 (1 bit)
I2S_TXISM_FFI : Transmit FIFO Service Request Interrupt
bits : 16 - 32 (17 bit)
I2S Transmit FIFO Level
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_TXLEV_LEVEL : Number of Audio Samples
bits : 0 - 4 (5 bit)
I2S Transmit FIFO Level
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_TXLEV_LEVEL : Number of Audio Samples
bits : 0 - 4 (5 bit)
I2S Transmit FIFO Configuration
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_TXFIFOCFG_LRS : Left-Right Sample Indicator
bits : 0 - 0 (1 bit)
I2S_TXFIFOCFG_CSS : Compact Stereo Sample Size
bits : 1 - 2 (2 bit)
I2S Transmit FIFO Configuration
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_TXFIFOCFG_LRS : Left-Right Sample Indicator
bits : 0 - 0 (1 bit)
I2S_TXFIFOCFG_CSS : Compact Stereo Sample Size
bits : 1 - 2 (2 bit)
I2S Transmit Module Configuration
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_TXCFG_SDSZ : System Data Size
bits : 4 - 13 (10 bit)
I2S_TXCFG_SSZ : Sample Size
bits : 10 - 25 (16 bit)
I2S_TXCFG_MSL : SCLK Master/Slave
bits : 22 - 44 (23 bit)
I2S_TXCFG_FMT : FIFO Empty
bits : 23 - 46 (24 bit)
I2S_TXCFG_WM : Write Mode
bits : 24 - 49 (26 bit)
Enumeration:
0x0 : I2S_TXCFG_WM_DUAL
Stereo mode
0x1 : I2S_TXCFG_WM_COMPACT
Compact Stereo mode
0x2 : I2S_TXCFG_WM_MONO
Mono mode
End of enumeration elements list.
I2S_TXCFG_LRP : Left/Right Clock Polarity
bits : 26 - 52 (27 bit)
I2S_TXCFG_SCP : SCLK Polarity
bits : 27 - 54 (28 bit)
I2S_TXCFG_DLY : Data Delay
bits : 28 - 56 (29 bit)
I2S_TXCFG_JST : Justification of Output Data
bits : 29 - 58 (30 bit)
I2S Transmit Module Configuration
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_TXCFG_SDSZ : System Data Size
bits : 4 - 13 (10 bit)
I2S_TXCFG_SSZ : Sample Size
bits : 10 - 25 (16 bit)
I2S_TXCFG_MSL : SCLK Master/Slave
bits : 22 - 44 (23 bit)
I2S_TXCFG_FMT : FIFO Empty
bits : 23 - 46 (24 bit)
I2S_TXCFG_WM : Write Mode
bits : 24 - 49 (26 bit)
Enumeration:
0x0 : I2S_TXCFG_WM_DUAL
Stereo mode
0x1 : I2S_TXCFG_WM_COMPACT
Compact Stereo mode
0x2 : I2S_TXCFG_WM_MONO
Mono mode
End of enumeration elements list.
I2S_TXCFG_LRP : Left/Right Clock Polarity
bits : 26 - 52 (27 bit)
I2S_TXCFG_SCP : SCLK Polarity
bits : 27 - 54 (28 bit)
I2S_TXCFG_DLY : Data Delay
bits : 28 - 56 (29 bit)
I2S_TXCFG_JST : Justification of Output Data
bits : 29 - 58 (30 bit)
I2S Receive FIFO Data
address_offset : 0x800 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_RXFIFO : RX Data
bits : 0 - 31 (32 bit)
I2S Receive FIFO Data
address_offset : 0x800 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_RXFIFO : RX Data
bits : 0 - 31 (32 bit)
I2S Receive FIFO Configuration
address_offset : 0x804 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_RXFIFOCFG_LRS : Left-Right Sample Indicator
bits : 0 - 0 (1 bit)
I2S_RXFIFOCFG_CSS : Compact Stereo Sample Size
bits : 1 - 2 (2 bit)
I2S_RXFIFOCFG_FMM : FIFO Mono Mode
bits : 2 - 4 (3 bit)
I2S Receive FIFO Configuration
address_offset : 0x804 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_RXFIFOCFG_LRS : Left-Right Sample Indicator
bits : 0 - 0 (1 bit)
I2S_RXFIFOCFG_CSS : Compact Stereo Sample Size
bits : 1 - 2 (2 bit)
I2S_RXFIFOCFG_FMM : FIFO Mono Mode
bits : 2 - 4 (3 bit)
I2S Receive Module Configuration
address_offset : 0x808 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_RXCFG_SDSZ : System Data Size
bits : 4 - 13 (10 bit)
I2S_RXCFG_SSZ : Sample Size
bits : 10 - 25 (16 bit)
I2S_RXCFG_MSL : SCLK Master/Slave
bits : 22 - 44 (23 bit)
I2S_RXCFG_RM : Read Mode
bits : 24 - 48 (25 bit)
I2S_RXCFG_LRP : Left/Right Clock Polarity
bits : 26 - 52 (27 bit)
I2S_RXCFG_SCP : SCLK Polarity
bits : 27 - 54 (28 bit)
I2S_RXCFG_DLY : Data Delay
bits : 28 - 56 (29 bit)
I2S_RXCFG_JST : Justification of Input Data
bits : 29 - 58 (30 bit)
I2S Receive Module Configuration
address_offset : 0x808 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_RXCFG_SDSZ : System Data Size
bits : 4 - 13 (10 bit)
I2S_RXCFG_SSZ : Sample Size
bits : 10 - 25 (16 bit)
I2S_RXCFG_MSL : SCLK Master/Slave
bits : 22 - 44 (23 bit)
I2S_RXCFG_RM : Read Mode
bits : 24 - 48 (25 bit)
I2S_RXCFG_LRP : Left/Right Clock Polarity
bits : 26 - 52 (27 bit)
I2S_RXCFG_SCP : SCLK Polarity
bits : 27 - 54 (28 bit)
I2S_RXCFG_DLY : Data Delay
bits : 28 - 56 (29 bit)
I2S_RXCFG_JST : Justification of Input Data
bits : 29 - 58 (30 bit)
I2S Receive FIFO Limit
address_offset : 0x80C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_RXLIMIT_LIMIT : FIFO Limit
bits : 0 - 4 (5 bit)
I2S Receive FIFO Limit
address_offset : 0x80C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_RXLIMIT_LIMIT : FIFO Limit
bits : 0 - 4 (5 bit)
I2S Receive Interrupt Status and Mask
address_offset : 0x810 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_RXISM_FFM : FIFO Interrupt Mask
bits : 0 - 0 (1 bit)
I2S_RXISM_FFI : Receive FIFO Service Request Interrupt
bits : 16 - 32 (17 bit)
I2S Receive Interrupt Status and Mask
address_offset : 0x810 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_RXISM_FFM : FIFO Interrupt Mask
bits : 0 - 0 (1 bit)
I2S_RXISM_FFI : Receive FIFO Service Request Interrupt
bits : 16 - 32 (17 bit)
I2S Receive FIFO Level
address_offset : 0x818 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_RXLEV_LEVEL : Number of Audio Samples
bits : 0 - 4 (5 bit)
I2S Receive FIFO Level
address_offset : 0x818 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_RXLEV_LEVEL : Number of Audio Samples
bits : 0 - 4 (5 bit)
I2S Transmit FIFO Limit
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_TXLIMIT_LIMIT : FIFO Limit
bits : 0 - 4 (5 bit)
I2S Transmit FIFO Limit
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_TXLIMIT_LIMIT : FIFO Limit
bits : 0 - 4 (5 bit)
I2S Module Configuration
address_offset : 0xC00 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_CFG_TXEN : Serial Transmit Engine Enable
bits : 0 - 0 (1 bit)
I2S_CFG_RXEN : Serial Receive Engine Enable
bits : 1 - 2 (2 bit)
I2S_CFG_TXSLV : Use External I2S0TXMCLK
bits : 4 - 8 (5 bit)
I2S_CFG_RXSLV : Use External I2S0RXMCLK
bits : 5 - 10 (6 bit)
I2S Module Configuration
address_offset : 0xC00 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_CFG_TXEN : Serial Transmit Engine Enable
bits : 0 - 0 (1 bit)
I2S_CFG_RXEN : Serial Receive Engine Enable
bits : 1 - 2 (2 bit)
I2S_CFG_TXSLV : Use External I2S0TXMCLK
bits : 4 - 8 (5 bit)
I2S_CFG_RXSLV : Use External I2S0RXMCLK
bits : 5 - 10 (6 bit)
I2S Interrupt Mask
address_offset : 0xC10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_IM_TXFSR : Transmit FIFO Service Request
bits : 0 - 0 (1 bit)
I2S_IM_TXWE : Transmit FIFO Write Error
bits : 1 - 2 (2 bit)
I2S_IM_RXFSR : Receive FIFO Service Request
bits : 4 - 8 (5 bit)
I2S_IM_RXRE : Receive FIFO Read Error
bits : 5 - 10 (6 bit)
I2S Interrupt Mask
address_offset : 0xC10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_IM_TXFSR : Transmit FIFO Service Request
bits : 0 - 0 (1 bit)
I2S_IM_TXWE : Transmit FIFO Write Error
bits : 1 - 2 (2 bit)
I2S_IM_RXFSR : Receive FIFO Service Request
bits : 4 - 8 (5 bit)
I2S_IM_RXRE : Receive FIFO Read Error
bits : 5 - 10 (6 bit)
I2S Raw Interrupt Status
address_offset : 0xC14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_RIS_TXFSR : Transmit FIFO Service Request
bits : 0 - 0 (1 bit)
I2S_RIS_TXWE : Transmit FIFO Write Error
bits : 1 - 2 (2 bit)
I2S_RIS_RXFSR : Receive FIFO Service Request
bits : 4 - 8 (5 bit)
I2S_RIS_RXRE : Receive FIFO Read Error
bits : 5 - 10 (6 bit)
I2S Raw Interrupt Status
address_offset : 0xC14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_RIS_TXFSR : Transmit FIFO Service Request
bits : 0 - 0 (1 bit)
I2S_RIS_TXWE : Transmit FIFO Write Error
bits : 1 - 2 (2 bit)
I2S_RIS_RXFSR : Receive FIFO Service Request
bits : 4 - 8 (5 bit)
I2S_RIS_RXRE : Receive FIFO Read Error
bits : 5 - 10 (6 bit)
I2S Masked Interrupt Status
address_offset : 0xC18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_MIS_TXFSR : Transmit FIFO Service Request
bits : 0 - 0 (1 bit)
I2S_MIS_TXWE : Transmit FIFO Write Error
bits : 1 - 2 (2 bit)
I2S_MIS_RXFSR : Receive FIFO Service Request
bits : 4 - 8 (5 bit)
I2S_MIS_RXRE : Receive FIFO Read Error
bits : 5 - 10 (6 bit)
I2S Masked Interrupt Status
address_offset : 0xC18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_MIS_TXFSR : Transmit FIFO Service Request
bits : 0 - 0 (1 bit)
I2S_MIS_TXWE : Transmit FIFO Write Error
bits : 1 - 2 (2 bit)
I2S_MIS_RXFSR : Receive FIFO Service Request
bits : 4 - 8 (5 bit)
I2S_MIS_RXRE : Receive FIFO Read Error
bits : 5 - 10 (6 bit)
I2S Interrupt Clear
address_offset : 0xC1C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
I2S_IC_TXWE : Transmit FIFO Write Error
bits : 1 - 2 (2 bit)
access : write-only
I2S_IC_RXRE : Receive FIFO Read Error
bits : 5 - 10 (6 bit)
access : write-only
I2S Interrupt Clear
address_offset : 0xC1C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
I2S_IC_TXWE : Transmit FIFO Write Error
bits : 1 - 2 (2 bit)
access : write-only
I2S_IC_RXRE : Receive FIFO Read Error
bits : 5 - 10 (6 bit)
access : write-only
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