Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
EPI Configuration
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_CFG_MODE : Mode Select
bits : 0 - 3 (4 bit)
Enumeration:
0x0 : EPI_CFG_MODE_NONE
General Purpose
0x1 : EPI_CFG_MODE_SDRAM
SDRAM
0x2 : EPI_CFG_MODE_HB8
8-Bit Host-Bus (HB8)
0x3 : EPI_CFG_MODE_HB16
16-Bit Host-Bus (HB16)
End of enumeration elements list.
EPI_CFG_BLKEN : Block Enable
bits : 4 - 8 (5 bit)
EPI Configuration
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_CFG_MODE : Mode Select
bits : 0 - 3 (4 bit)
Enumeration:
0x0 : EPI_CFG_MODE_NONE
General Purpose
0x1 : EPI_CFG_MODE_SDRAM
SDRAM
0x2 : EPI_CFG_MODE_HB8
8-Bit Host-Bus (HB8)
0x3 : EPI_CFG_MODE_HB16
16-Bit Host-Bus (HB16)
End of enumeration elements list.
EPI_CFG_BLKEN : Block Enable
bits : 4 - 8 (5 bit)
EPI Host-Bus 16 Configuration
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : EPI_ALT16
reset_Mask : 0x0
EPI_HB16CFG_MODE : Host Bus Sub-Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_HB16CFG_MODE_ADMUX
ADMUX - AD[15:0]
0x1 : EPI_HB16CFG_MODE_ADNMUX
ADNONMUX - D[15:0]
0x2 : EPI_HB16CFG_MODE_SRAM
Continuous Read - D[15:0]
0x3 : EPI_HB16CFG_MODE_XFIFO
XFIFO - D[15:0]
End of enumeration elements list.
EPI_HB16CFG_BSEL : Byte Select Configuration
bits : 2 - 4 (3 bit)
EPI_HB16CFG_RDWS : CS0n Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB16CFG_RDWS_0
No wait states
0x1 : EPI_HB16CFG_RDWS_1
1 wait state
0x2 : EPI_HB16CFG_RDWS_2
2 wait states
0x3 : EPI_HB16CFG_RDWS_3
3 wait states
End of enumeration elements list.
EPI_HB16CFG_WRWS : CS0n Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB16CFG_WRWS_0
No wait states
0x1 : EPI_HB16CFG_WRWS_1
1 wait state
0x2 : EPI_HB16CFG_WRWS_2
2 wait states
0x3 : EPI_HB16CFG_WRWS_3
3 wait states
End of enumeration elements list.
EPI_HB16CFG_MAXWAIT : Maximum Wait
bits : 8 - 23 (16 bit)
EPI_HB16CFG_RDHIGH : READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB16CFG_WRHIGH : WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI_HB16CFG_XFEEN : External FIFO EMPTY Enable
bits : 22 - 44 (23 bit)
EPI_HB16CFG_XFFEN : External FIFO FULL Enable
bits : 23 - 46 (24 bit)
EPI General-Purpose Configuration
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_GPCFG_DSIZE : Size of Data Bus
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_GPCFG_DSIZE_4BIT
8 Bits Wide (EPI0S0 to EPI0S7)
0x1 : EPI_GPCFG_DSIZE_16BIT
16 Bits Wide (EPI0S0 to EPI0S15)
0x2 : EPI_GPCFG_DSIZE_24BIT
24 Bits Wide (EPI0S0 to EPI0S23)
0x3 : EPI_GPCFG_DSIZE_32BIT
32 Bits Wide (EPI0S0 to EPI0S31)
End of enumeration elements list.
EPI_GPCFG_ASIZE : Address Bus Size
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_GPCFG_ASIZE_NONE
No address
0x1 : EPI_GPCFG_ASIZE_4BIT
Up to 4 bits wide
0x2 : EPI_GPCFG_ASIZE_12BIT
Up to 12 bits wide. This size cannot be used with 24-bit data
0x3 : EPI_GPCFG_ASIZE_20BIT
Up to 20 bits wide. This size cannot be used with data sizes other than 8
End of enumeration elements list.
EPI_GPCFG_MAXWAIT : Maximum Wait
bits : 8 - 23 (16 bit)
EPI_GPCFG_RD2CYC : 2-Cycle Reads
bits : 18 - 36 (19 bit)
EPI_GPCFG_WR2CYC : 2-Cycle Writes
bits : 19 - 38 (20 bit)
EPI_GPCFG_RW : Read and Write
bits : 21 - 42 (22 bit)
EPI_GPCFG_FRMCNT : Frame Count
bits : 22 - 47 (26 bit)
EPI_GPCFG_FRM50 : 50/50 Frame
bits : 26 - 52 (27 bit)
EPI_GPCFG_FRMPIN : Framing Pin
bits : 27 - 54 (28 bit)
EPI_GPCFG_RDYEN : Ready Enable
bits : 28 - 56 (29 bit)
EPI_GPCFG_CLKGATE : Clock Gated
bits : 30 - 60 (31 bit)
EPI_GPCFG_CLKPIN : Clock Pin
bits : 31 - 62 (32 bit)
EPI SDRAM Configuration
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : EPI_ALTSD
reset_Mask : 0x0
EPI_SDRAMCFG_SIZE : Size of SDRAM
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_SDRAMCFG_SIZE_8MB
64 megabits (8MB)
0x1 : EPI_SDRAMCFG_SIZE_16MB
128 megabits (16MB)
0x2 : EPI_SDRAMCFG_SIZE_32MB
256 megabits (32MB)
0x3 : EPI_SDRAMCFG_SIZE_64MB
512 megabits (64MB)
End of enumeration elements list.
EPI_SDRAMCFG_SLEEP : Sleep Mode
bits : 9 - 18 (10 bit)
EPI_SDRAMCFG_RFSH : Refresh Counter
bits : 16 - 42 (27 bit)
EPI_SDRAMCFG_FREQ : Frequency Range
bits : 30 - 61 (32 bit)
Enumeration:
0x0 : EPI_SDRAMCFG_FREQ_NONE
0 - 15 MHz
0x1 : EPI_SDRAMCFG_FREQ_15MHZ
15 - 30 MHz
0x2 : EPI_SDRAMCFG_FREQ_30MHZ
30 - 50 MHz
0x3 : EPI_SDRAMCFG_FREQ_50MHZ
50 - 100 MHz
End of enumeration elements list.
EPI Host-Bus 8 Configuration
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : EPI_ALT8
reset_Mask : 0x0
EPI_HB8CFG_MODE : Host Bus Sub-Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_HB8CFG_MODE_MUX
ADMUX - AD[7:0]
0x1 : EPI_HB8CFG_MODE_NMUX
ADNONMUX - D[7:0]
0x2 : EPI_HB8CFG_MODE_SRAM
Continuous Read - D[7:0]
0x3 : EPI_HB8CFG_MODE_FIFO
XFIFO - D[7:0]
End of enumeration elements list.
EPI_HB8CFG_RDWS : Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB8CFG_RDWS_0
No wait states
0x1 : EPI_HB8CFG_RDWS_1
1 wait state
0x2 : EPI_HB8CFG_RDWS_2
2 wait states
0x3 : EPI_HB8CFG_RDWS_3
3 wait states
End of enumeration elements list.
EPI_HB8CFG_WRWS : Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB8CFG_WRWS_0
No wait states
0x1 : EPI_HB8CFG_WRWS_1
1 wait state
0x2 : EPI_HB8CFG_WRWS_2
2 wait states
0x3 : EPI_HB8CFG_WRWS_3
3 wait states
End of enumeration elements list.
EPI_HB8CFG_MAXWAIT : Maximum Wait
bits : 8 - 23 (16 bit)
EPI_HB8CFG_RDHIGH : CS0n READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB8CFG_WRHIGH : CS0n WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI_HB8CFG_XFEEN : External FIFO EMPTY Enable
bits : 22 - 44 (23 bit)
EPI_HB8CFG_XFFEN : External FIFO FULL Enable
bits : 23 - 46 (24 bit)
EPI Host-Bus 16 Configuration
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB16CFG_MODE : Host Bus Sub-Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_HB16CFG_MODE_ADMUX
ADMUX - AD[15:0]
0x1 : EPI_HB16CFG_MODE_ADNMUX
ADNONMUX - D[15:0]
0x2 : EPI_HB16CFG_MODE_SRAM
Continuous Read - D[15:0]
0x3 : EPI_HB16CFG_MODE_XFIFO
XFIFO - D[15:0]
End of enumeration elements list.
EPI_HB16CFG_BSEL : Byte Select Configuration
bits : 2 - 4 (3 bit)
EPI_HB16CFG_RDWS : CS0n Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB16CFG_RDWS_0
No wait states
0x1 : EPI_HB16CFG_RDWS_1
1 wait state
0x2 : EPI_HB16CFG_RDWS_2
2 wait states
0x3 : EPI_HB16CFG_RDWS_3
3 wait states
End of enumeration elements list.
EPI_HB16CFG_WRWS : CS0n Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB16CFG_WRWS_0
No wait states
0x1 : EPI_HB16CFG_WRWS_1
1 wait state
0x2 : EPI_HB16CFG_WRWS_2
2 wait states
0x3 : EPI_HB16CFG_WRWS_3
3 wait states
End of enumeration elements list.
EPI_HB16CFG_MAXWAIT : Maximum Wait
bits : 8 - 23 (16 bit)
EPI_HB16CFG_RDHIGH : READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB16CFG_WRHIGH : WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI_HB16CFG_XFEEN : External FIFO EMPTY Enable
bits : 22 - 44 (23 bit)
EPI_HB16CFG_XFFEN : External FIFO FULL Enable
bits : 23 - 46 (24 bit)
EPI General-Purpose Configuration
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_GPCFG_DSIZE : Size of Data Bus
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_GPCFG_DSIZE_4BIT
8 Bits Wide (EPI0S0 to EPI0S7)
0x1 : EPI_GPCFG_DSIZE_16BIT
16 Bits Wide (EPI0S0 to EPI0S15)
0x2 : EPI_GPCFG_DSIZE_24BIT
24 Bits Wide (EPI0S0 to EPI0S23)
0x3 : EPI_GPCFG_DSIZE_32BIT
32 Bits Wide (EPI0S0 to EPI0S31)
End of enumeration elements list.
EPI_GPCFG_ASIZE : Address Bus Size
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_GPCFG_ASIZE_NONE
No address
0x1 : EPI_GPCFG_ASIZE_4BIT
Up to 4 bits wide
0x2 : EPI_GPCFG_ASIZE_12BIT
Up to 12 bits wide. This size cannot be used with 24-bit data
0x3 : EPI_GPCFG_ASIZE_20BIT
Up to 20 bits wide. This size cannot be used with data sizes other than 8
End of enumeration elements list.
EPI_GPCFG_MAXWAIT : Maximum Wait
bits : 8 - 23 (16 bit)
EPI_GPCFG_RD2CYC : 2-Cycle Reads
bits : 18 - 36 (19 bit)
EPI_GPCFG_WR2CYC : 2-Cycle Writes
bits : 19 - 38 (20 bit)
EPI_GPCFG_RW : Read and Write
bits : 21 - 42 (22 bit)
EPI_GPCFG_FRMCNT : Frame Count
bits : 22 - 47 (26 bit)
EPI_GPCFG_FRM50 : 50/50 Frame
bits : 26 - 52 (27 bit)
EPI_GPCFG_FRMPIN : Framing Pin
bits : 27 - 54 (28 bit)
EPI_GPCFG_RDYEN : Ready Enable
bits : 28 - 56 (29 bit)
EPI_GPCFG_CLKGATE : Clock Gated
bits : 30 - 60 (31 bit)
EPI_GPCFG_CLKPIN : Clock Pin
bits : 31 - 62 (32 bit)
EPI SDRAM Configuration
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_SDRAMCFG_SIZE : Size of SDRAM
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_SDRAMCFG_SIZE_8MB
64 megabits (8MB)
0x1 : EPI_SDRAMCFG_SIZE_16MB
128 megabits (16MB)
0x2 : EPI_SDRAMCFG_SIZE_32MB
256 megabits (32MB)
0x3 : EPI_SDRAMCFG_SIZE_64MB
512 megabits (64MB)
End of enumeration elements list.
EPI_SDRAMCFG_SLEEP : Sleep Mode
bits : 9 - 18 (10 bit)
EPI_SDRAMCFG_RFSH : Refresh Counter
bits : 16 - 42 (27 bit)
EPI_SDRAMCFG_FREQ : Frequency Range
bits : 30 - 61 (32 bit)
Enumeration:
0x0 : EPI_SDRAMCFG_FREQ_NONE
0 - 15 MHz
0x1 : EPI_SDRAMCFG_FREQ_15MHZ
15 - 30 MHz
0x2 : EPI_SDRAMCFG_FREQ_30MHZ
30 - 50 MHz
0x3 : EPI_SDRAMCFG_FREQ_50MHZ
50 - 100 MHz
End of enumeration elements list.
EPI Host-Bus 8 Configuration
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB8CFG_MODE : Host Bus Sub-Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_HB8CFG_MODE_MUX
ADMUX - AD[7:0]
0x1 : EPI_HB8CFG_MODE_NMUX
ADNONMUX - D[7:0]
0x2 : EPI_HB8CFG_MODE_SRAM
Continuous Read - D[7:0]
0x3 : EPI_HB8CFG_MODE_FIFO
XFIFO - D[7:0]
End of enumeration elements list.
EPI_HB8CFG_RDWS : Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB8CFG_RDWS_0
No wait states
0x1 : EPI_HB8CFG_RDWS_1
1 wait state
0x2 : EPI_HB8CFG_RDWS_2
2 wait states
0x3 : EPI_HB8CFG_RDWS_3
3 wait states
End of enumeration elements list.
EPI_HB8CFG_WRWS : Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB8CFG_WRWS_0
No wait states
0x1 : EPI_HB8CFG_WRWS_1
1 wait state
0x2 : EPI_HB8CFG_WRWS_2
2 wait states
0x3 : EPI_HB8CFG_WRWS_3
3 wait states
End of enumeration elements list.
EPI_HB8CFG_MAXWAIT : Maximum Wait
bits : 8 - 23 (16 bit)
EPI_HB8CFG_RDHIGH : CS0n READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB8CFG_WRHIGH : CS0n WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI_HB8CFG_XFEEN : External FIFO EMPTY Enable
bits : 22 - 44 (23 bit)
EPI_HB8CFG_XFFEN : External FIFO FULL Enable
bits : 23 - 46 (24 bit)
EPI Host-Bus 8 Configuration 2
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : EPI_ALT8
reset_Mask : 0x0
EPI_HB8CFG2_RDWS : CS1n Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB8CFG2_RDWS_0
No wait states
0x1 : EPI_HB8CFG2_RDWS_1
1 wait state
0x2 : EPI_HB8CFG2_RDWS_2
2 wait states
0x3 : EPI_HB8CFG2_RDWS_3
3 wait states
End of enumeration elements list.
EPI_HB8CFG2_WRWS : CS1n Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB8CFG2_WRWS_0
No wait states
0x1 : EPI_HB8CFG2_WRWS_1
1 wait state
0x2 : EPI_HB8CFG2_WRWS_2
2 wait states
0x3 : EPI_HB8CFG2_WRWS_3
3 wait states
End of enumeration elements list.
EPI_HB8CFG2_RDHIGH : CS1n READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB8CFG2_WRHIGH : CS1n WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI_HB8CFG2_CSCFG : Chip Select Configuration
bits : 24 - 49 (26 bit)
Enumeration:
0x0 : EPI_HB8CFG2_CSCFG_ALE
ALE Configuration
0x1 : EPI_HB8CFG2_CSCFG_CS
CSn Configuration
0x2 : EPI_HB8CFG2_CSCFG_DCS
Dual CSn Configuration
0x3 : EPI_HB8CFG2_CSCFG_ADCS
ALE with Dual CSn Configuration
End of enumeration elements list.
EPI_HB8CFG2_CSBAUD : Chip Select Baud Rate
bits : 26 - 52 (27 bit)
EPI_HB8CFG2_WORD : Word Access Mode
bits : 31 - 62 (32 bit)
EPI Host-Bus 16 Configuration 2
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : EPI_ALT16
reset_Mask : 0x0
EPI_HB16CFG2_RDWS : CS1n Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB16CFG2_RDWS_0
No wait states
0x1 : EPI_HB16CFG2_RDWS_1
1 wait state
0x2 : EPI_HB16CFG2_RDWS_2
2 wait states
0x3 : EPI_HB16CFG2_RDWS_3
3 wait states
End of enumeration elements list.
EPI_HB16CFG2_WRWS : CS1n Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB16CFG2_WRWS_0
No wait states
0x1 : EPI_HB16CFG2_WRWS_1
1 wait state
0x2 : EPI_HB16CFG2_WRWS_2
2 wait states
0x3 : EPI_HB16CFG2_WRWS_3
3 wait states
End of enumeration elements list.
EPI_HB16CFG2_RDHIGH : CS1n READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB16CFG2_WRHIGH : CS1n WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI_HB16CFG2_CSCFG : Chip Select Configuration
bits : 24 - 49 (26 bit)
Enumeration:
0x0 : EPI_HB16CFG2_CSCFG_ALE
ALE Configuration
0x1 : EPI_HB16CFG2_CSCFG_CS
CSn Configuration
0x2 : EPI_HB16CFG2_CSCFG_DCS
Dual CSn Configuration
0x3 : EPI_HB16CFG2_CSCFG_ADCS
ALE with Dual CSn Configuration
End of enumeration elements list.
EPI_HB16CFG2_CSBAUD : Chip Select Baud Rate
bits : 26 - 52 (27 bit)
EPI_HB16CFG2_WORD : Word Access Mode
bits : 31 - 62 (32 bit)
EPI General-Purpose Configuration 2
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_GPCFG2_WORD : Word Access Mode
bits : 31 - 62 (32 bit)
EPI Host-Bus 8 Configuration 2
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB8CFG2_RDWS : CS1n Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB8CFG2_RDWS_0
No wait states
0x1 : EPI_HB8CFG2_RDWS_1
1 wait state
0x2 : EPI_HB8CFG2_RDWS_2
2 wait states
0x3 : EPI_HB8CFG2_RDWS_3
3 wait states
End of enumeration elements list.
EPI_HB8CFG2_WRWS : CS1n Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB8CFG2_WRWS_0
No wait states
0x1 : EPI_HB8CFG2_WRWS_1
1 wait state
0x2 : EPI_HB8CFG2_WRWS_2
2 wait states
0x3 : EPI_HB8CFG2_WRWS_3
3 wait states
End of enumeration elements list.
EPI_HB8CFG2_RDHIGH : CS1n READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB8CFG2_WRHIGH : CS1n WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI_HB8CFG2_CSCFG : Chip Select Configuration
bits : 24 - 49 (26 bit)
Enumeration:
0x0 : EPI_HB8CFG2_CSCFG_ALE
ALE Configuration
0x1 : EPI_HB8CFG2_CSCFG_CS
CSn Configuration
0x2 : EPI_HB8CFG2_CSCFG_DCS
Dual CSn Configuration
0x3 : EPI_HB8CFG2_CSCFG_ADCS
ALE with Dual CSn Configuration
End of enumeration elements list.
EPI_HB8CFG2_CSBAUD : Chip Select Baud Rate
bits : 26 - 52 (27 bit)
EPI_HB8CFG2_WORD : Word Access Mode
bits : 31 - 62 (32 bit)
EPI Host-Bus 16 Configuration 2
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB16CFG2_RDWS : CS1n Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB16CFG2_RDWS_0
No wait states
0x1 : EPI_HB16CFG2_RDWS_1
1 wait state
0x2 : EPI_HB16CFG2_RDWS_2
2 wait states
0x3 : EPI_HB16CFG2_RDWS_3
3 wait states
End of enumeration elements list.
EPI_HB16CFG2_WRWS : CS1n Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB16CFG2_WRWS_0
No wait states
0x1 : EPI_HB16CFG2_WRWS_1
1 wait state
0x2 : EPI_HB16CFG2_WRWS_2
2 wait states
0x3 : EPI_HB16CFG2_WRWS_3
3 wait states
End of enumeration elements list.
EPI_HB16CFG2_RDHIGH : CS1n READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB16CFG2_WRHIGH : CS1n WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI_HB16CFG2_CSCFG : Chip Select Configuration
bits : 24 - 49 (26 bit)
Enumeration:
0x0 : EPI_HB16CFG2_CSCFG_ALE
ALE Configuration
0x1 : EPI_HB16CFG2_CSCFG_CS
CSn Configuration
0x2 : EPI_HB16CFG2_CSCFG_DCS
Dual CSn Configuration
0x3 : EPI_HB16CFG2_CSCFG_ADCS
ALE with Dual CSn Configuration
End of enumeration elements list.
EPI_HB16CFG2_CSBAUD : Chip Select Baud Rate
bits : 26 - 52 (27 bit)
EPI_HB16CFG2_WORD : Word Access Mode
bits : 31 - 62 (32 bit)
EPI General-Purpose Configuration 2
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_GPCFG2_WORD : Word Access Mode
bits : 31 - 62 (32 bit)
EPI Address Map
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_ADDRMAP_ERADR : External RAM Address
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_ADDRMAP_ERADR_NONE
Not mapped
0x1 : EPI_ADDRMAP_ERADR_6000
At 0x6000.0000
0x2 : EPI_ADDRMAP_ERADR_8000
At 0x8000.0000
End of enumeration elements list.
EPI_ADDRMAP_ERSZ : External RAM Size
bits : 2 - 5 (4 bit)
Enumeration:
0x0 : EPI_ADDRMAP_ERSZ_256B
256 bytes; lower address range: 0x00 to 0xFF
0x1 : EPI_ADDRMAP_ERSZ_64KB
64 KB; lower address range: 0x0000 to 0xFFFF
0x2 : EPI_ADDRMAP_ERSZ_16MB
16 MB; lower address range: 0x00.0000 to 0xFF.FFFF
0x3 : EPI_ADDRMAP_ERSZ_256MB
256 MB; lower address range: 0x000.0000 to 0xFFF.FFFF
End of enumeration elements list.
EPI_ADDRMAP_EPADR : External Peripheral Address
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_ADDRMAP_EPADR_NONE
Not mapped
0x1 : EPI_ADDRMAP_EPADR_A000
At 0xA000.0000
0x2 : EPI_ADDRMAP_EPADR_C000
At 0xC000.0000
End of enumeration elements list.
EPI_ADDRMAP_EPSZ : External Peripheral Size
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_ADDRMAP_EPSZ_256B
256 bytes; lower address range: 0x00 to 0xFF
0x1 : EPI_ADDRMAP_EPSZ_64KB
64 KB; lower address range: 0x0000 to 0xFFFF
0x2 : EPI_ADDRMAP_EPSZ_16MB
16 MB; lower address range: 0x00.0000 to 0xFF.FFFF
0x3 : EPI_ADDRMAP_EPSZ_256MB
256 MB; lower address range: 0x000.0000 to 0xFFF.FFFF
End of enumeration elements list.
EPI Address Map
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_ADDRMAP_ERADR : External RAM Address
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_ADDRMAP_ERADR_NONE
Not mapped
0x1 : EPI_ADDRMAP_ERADR_6000
At 0x6000.0000
0x2 : EPI_ADDRMAP_ERADR_8000
At 0x8000.0000
End of enumeration elements list.
EPI_ADDRMAP_ERSZ : External RAM Size
bits : 2 - 5 (4 bit)
Enumeration:
0x0 : EPI_ADDRMAP_ERSZ_256B
256 bytes lower address range: 0x00 to 0xFF
0x1 : EPI_ADDRMAP_ERSZ_64KB
64 KB lower address range: 0x0000 to 0xFFFF
0x2 : EPI_ADDRMAP_ERSZ_16MB
16 MB lower address range: 0x00.0000 to 0xFF.FFFF
0x3 : EPI_ADDRMAP_ERSZ_256MB
256 MB lower address range: 0x000.0000 to 0xFFF.FFFF
End of enumeration elements list.
EPI_ADDRMAP_EPADR : External Peripheral Address
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_ADDRMAP_EPADR_NONE
Not mapped
0x1 : EPI_ADDRMAP_EPADR_A000
At 0xA000.0000
0x2 : EPI_ADDRMAP_EPADR_C000
At 0xC000.0000
End of enumeration elements list.
EPI_ADDRMAP_EPSZ : External Peripheral Size
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_ADDRMAP_EPSZ_256B
256 bytes lower address range: 0x00 to 0xFF
0x1 : EPI_ADDRMAP_EPSZ_64KB
64 KB lower address range: 0x0000 to 0xFFFF
0x2 : EPI_ADDRMAP_EPSZ_16MB
16 MB lower address range: 0x00.0000 to 0xFF.FFFF
0x3 : EPI_ADDRMAP_EPSZ_256MB
256 MB lower address range: 0x000.0000 to 0xFFF.FFFF
End of enumeration elements list.
EPI Read Size 0
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RSIZE0_SIZE : Current Size
bits : 0 - 1 (2 bit)
Enumeration:
0x1 : EPI_RSIZE0_SIZE_8BIT
Byte (8 bits)
0x2 : EPI_RSIZE0_SIZE_16BIT
Half-word (16 bits)
0x3 : EPI_RSIZE0_SIZE_32BIT
Word (32 bits)
End of enumeration elements list.
EPI Read Size 0
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RSIZE0_SIZE : Current Size
bits : 0 - 1 (2 bit)
Enumeration:
0x1 : EPI_RSIZE0_SIZE_8BIT
Byte (8 bits)
0x2 : EPI_RSIZE0_SIZE_16BIT
Half-word (16 bits)
0x3 : EPI_RSIZE0_SIZE_32BIT
Word (32 bits)
End of enumeration elements list.
EPI FIFO Level Selects
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_FIFOLVL_RDFIFO : Read FIFO
bits : 0 - 2 (3 bit)
Enumeration:
0x0 : EPI_FIFOLVL_RDFIFO_EMPT
Empty
0x1 : EPI_FIFOLVL_RDFIFO_1_8
Trigger when there are 1 or more entries in the NBRFIFO
0x2 : EPI_FIFOLVL_RDFIFO_1_4
Trigger when there are 2 or more entries in the NBRFIFO
0x3 : EPI_FIFOLVL_RDFIFO_1_2
Trigger when there are 4 or more entries in the NBRFIFO
0x4 : EPI_FIFOLVL_RDFIFO_3_4
Trigger when there are 6 or more entries in the NBRFIFO
0x5 : EPI_FIFOLVL_RDFIFO_7_8
Trigger when there are 7 or more entries in the NBRFIFO
0x6 : EPI_FIFOLVL_RDFIFO_FULL
Trigger when there are 8 entries in the NBRFIFO
End of enumeration elements list.
EPI_FIFOLVL_WRFIFO : Write FIFO
bits : 4 - 10 (7 bit)
Enumeration:
0x0 : EPI_FIFOLVL_WRFIFO_EMPT
Trigger when there are 1 to 4 spaces available in the WFIFO
0x2 : EPI_FIFOLVL_WRFIFO_1_4
Trigger when there are 1 to 3 spaces available in the WFIFO
0x3 : EPI_FIFOLVL_WRFIFO_1_2
Trigger when there are 1 to 2 spaces available in the WFIFO
0x4 : EPI_FIFOLVL_WRFIFO_3_4
Trigger when there is 1 space available in the WFIFO
End of enumeration elements list.
EPI_FIFOLVL_RSERR : Read Stall Error
bits : 16 - 32 (17 bit)
EPI_FIFOLVL_WFERR : Write Full Error
bits : 17 - 34 (18 bit)
EPI FIFO Level Selects
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_FIFOLVL_RDFIFO : Read FIFO
bits : 0 - 2 (3 bit)
Enumeration:
0x0 : EPI_FIFOLVL_RDFIFO_EMPT
Empty
0x1 : EPI_FIFOLVL_RDFIFO_1_8
Trigger when there are 1 or more entries in the NBRFIFO
0x2 : EPI_FIFOLVL_RDFIFO_1_4
Trigger when there are 2 or more entries in the NBRFIFO
0x3 : EPI_FIFOLVL_RDFIFO_1_2
Trigger when there are 4 or more entries in the NBRFIFO
0x4 : EPI_FIFOLVL_RDFIFO_3_4
Trigger when there are 6 or more entries in the NBRFIFO
0x5 : EPI_FIFOLVL_RDFIFO_7_8
Trigger when there are 7 or more entries in the NBRFIFO
0x6 : EPI_FIFOLVL_RDFIFO_FULL
Trigger when there are 8 entries in the NBRFIFO
End of enumeration elements list.
EPI_FIFOLVL_WRFIFO : Write FIFO
bits : 4 - 10 (7 bit)
Enumeration:
0x0 : EPI_FIFOLVL_WRFIFO_EMPT
Trigger when there are 1 to 4 spaces available in the WFIFO
0x2 : EPI_FIFOLVL_WRFIFO_1_4
Trigger when there are 1 to 3 spaces available in the WFIFO
0x3 : EPI_FIFOLVL_WRFIFO_1_2
Trigger when there are 1 to 2 spaces available in the WFIFO
0x4 : EPI_FIFOLVL_WRFIFO_3_4
Trigger when there is 1 space available in the WFIFO
End of enumeration elements list.
EPI_FIFOLVL_RSERR : Read Stall Error
bits : 16 - 32 (17 bit)
EPI_FIFOLVL_WFERR : Write Full Error
bits : 17 - 34 (18 bit)
EPI Write FIFO Count
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_WFIFOCNT_WTAV : Available Write Transactions
bits : 0 - 2 (3 bit)
EPI Write FIFO Count
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_WFIFOCNT_WTAV : Available Write Transactions
bits : 0 - 2 (3 bit)
EPI Interrupt Mask
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_IM_ERRIM : Error Interrupt Mask
bits : 0 - 0 (1 bit)
EPI_IM_RDIM : Read Interrupt Mask
bits : 1 - 2 (2 bit)
EPI_IM_WRIM : Write Interrupt Mask
bits : 2 - 4 (3 bit)
EPI Interrupt Mask
address_offset : 0x210 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_IM_ERRIM : Error Interrupt Mask
bits : 0 - 0 (1 bit)
EPI_IM_RDIM : Read Interrupt Mask
bits : 1 - 2 (2 bit)
EPI_IM_WRIM : Write Interrupt Mask
bits : 2 - 4 (3 bit)
EPI Raw Interrupt Status
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RIS_ERRRIS : Error Raw Interrupt Status
bits : 0 - 0 (1 bit)
EPI_RIS_RDRIS : Read Raw Interrupt Status
bits : 1 - 2 (2 bit)
EPI_RIS_WRRIS : Write Raw Interrupt Status
bits : 2 - 4 (3 bit)
EPI Raw Interrupt Status
address_offset : 0x214 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RIS_ERRRIS : Error Raw Interrupt Status
bits : 0 - 0 (1 bit)
EPI_RIS_RDRIS : Read Raw Interrupt Status
bits : 1 - 2 (2 bit)
EPI_RIS_WRRIS : Write Raw Interrupt Status
bits : 2 - 4 (3 bit)
EPI Masked Interrupt Status
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_MIS_ERRMIS : Error Masked Interrupt Status
bits : 0 - 0 (1 bit)
EPI_MIS_RDMIS : Read Masked Interrupt Status
bits : 1 - 2 (2 bit)
EPI_MIS_WRMIS : Write Masked Interrupt Status
bits : 2 - 4 (3 bit)
EPI Masked Interrupt Status
address_offset : 0x218 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_MIS_ERRMIS : Error Masked Interrupt Status
bits : 0 - 0 (1 bit)
EPI_MIS_RDMIS : Read Masked Interrupt Status
bits : 1 - 2 (2 bit)
EPI_MIS_WRMIS : Write Masked Interrupt Status
bits : 2 - 4 (3 bit)
EPI Error Interrupt Status and Clear
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_EISC_TOUT : Timeout Error
bits : 0 - 0 (1 bit)
EPI_EISC_RSTALL : Read Stalled Error
bits : 1 - 2 (2 bit)
EPI_EISC_WTFULL : Write FIFO Full Error
bits : 2 - 4 (3 bit)
EPI Error Interrupt Status and Clear
address_offset : 0x21C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_EISC_TOUT : Timeout Error
bits : 0 - 0 (1 bit)
EPI_EISC_RSTALL : Read Stalled Error
bits : 1 - 2 (2 bit)
EPI_EISC_WTFULL : Write FIFO Full Error
bits : 2 - 4 (3 bit)
EPI Read Address 0
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RADDR0_ADDR : Current Address
bits : 0 - 28 (29 bit)
EPI Read Address 0
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RADDR0_ADDR : Current Address
bits : 0 - 28 (29 bit)
EPI Non-Blocking Read Data 0
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RPSTD0_POSTCNT : Post Count
bits : 0 - 12 (13 bit)
EPI Non-Blocking Read Data 0
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RPSTD0_POSTCNT : Post Count
bits : 0 - 12 (13 bit)
EPI Read Size 1
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RSIZE1_SIZE : Current Size
bits : 0 - 1 (2 bit)
Enumeration:
0x1 : EPI_RSIZE1_SIZE_8BIT
Byte (8 bits)
0x2 : EPI_RSIZE1_SIZE_16BIT
Half-word (16 bits)
0x3 : EPI_RSIZE1_SIZE_32BIT
Word (32 bits)
End of enumeration elements list.
EPI Read Size 1
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RSIZE1_SIZE : Current Size
bits : 0 - 1 (2 bit)
Enumeration:
0x1 : EPI_RSIZE1_SIZE_8BIT
Byte (8 bits)
0x2 : EPI_RSIZE1_SIZE_16BIT
Half-word (16 bits)
0x3 : EPI_RSIZE1_SIZE_32BIT
Word (32 bits)
End of enumeration elements list.
EPI Read Address 1
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RADDR1_ADDR : Current Address
bits : 0 - 28 (29 bit)
EPI Read Address 1
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RADDR1_ADDR : Current Address
bits : 0 - 28 (29 bit)
EPI Non-Blocking Read Data 1
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RPSTD1_POSTCNT : Post Count
bits : 0 - 12 (13 bit)
EPI Non-Blocking Read Data 1
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RPSTD1_POSTCNT : Post Count
bits : 0 - 12 (13 bit)
EPI Main Baud Rate
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_BAUD_COUNT0 : Baud Rate Counter 0
bits : 0 - 15 (16 bit)
EPI_BAUD_COUNT1 : Baud Rate Counter 1
bits : 16 - 47 (32 bit)
EPI Main Baud Rate
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_BAUD_COUNT0 : Baud Rate Counter 0
bits : 0 - 15 (16 bit)
EPI_BAUD_COUNT1 : Baud Rate Counter 1
bits : 16 - 47 (32 bit)
EPI Status
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_STAT_ACTIVE : Register Active
bits : 0 - 0 (1 bit)
EPI_STAT_NBRBUSY : Non-Blocking Read Busy
bits : 4 - 8 (5 bit)
EPI_STAT_WBUSY : Write Busy
bits : 5 - 10 (6 bit)
EPI_STAT_INITSEQ : Initialization Sequence
bits : 6 - 12 (7 bit)
EPI_STAT_XFEMPTY : External FIFO Empty
bits : 7 - 14 (8 bit)
EPI_STAT_XFFULL : External FIFO Full
bits : 8 - 16 (9 bit)
EPI_STAT_CELOW : Clock Enable Low
bits : 9 - 18 (10 bit)
EPI Status
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_STAT_ACTIVE : Register Active
bits : 0 - 0 (1 bit)
EPI_STAT_NBRBUSY : Non-Blocking Read Busy
bits : 4 - 8 (5 bit)
EPI_STAT_WBUSY : Write Busy
bits : 5 - 10 (6 bit)
EPI_STAT_INITSEQ : Initialization Sequence
bits : 6 - 12 (7 bit)
EPI_STAT_XFEMPTY : External FIFO Empty
bits : 7 - 14 (8 bit)
EPI_STAT_XFFULL : External FIFO Full
bits : 8 - 16 (9 bit)
EPI_STAT_CELOW : Clock Enable Low
bits : 9 - 18 (10 bit)
EPI Read FIFO Count
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RFIFOCNT_COUNT : FIFO Count
bits : 0 - 2 (3 bit)
EPI Read FIFO Count
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RFIFOCNT_COUNT : FIFO Count
bits : 0 - 2 (3 bit)
EPI Read FIFO
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 1
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO1_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 1
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO1_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 2
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO2_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 2
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO2_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 3
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO3_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 3
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO3_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 4
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO4_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 4
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO4_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 5
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO5_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 5
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO5_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 6
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO6_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 6
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO6_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 7
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO7_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 7
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO7_DATA : Reads Data
bits : 0 - 31 (32 bit)
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