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NVIC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

NVICST_CTRL

ST_CTRL

NVICEN0

EN0

NVICEN1

EN1

NVICEN2

EN2

NVICEN3

EN3

NVICEN4

EN4

NVICST_RELOAD

ST_RELOAD

NVICST_CURRENT

ST_CURRENT

NVICDIS0

DIS0

NVICDIS1

DIS1

NVICDIS2

DIS2

NVICDIS3

DIS3

NVICDIS4

DIS4

NVICST_CAL

ST_CAL

NVICPEND0

PEND0

NVICPEND1

PEND1

NVICPEND2

PEND2

NVICPEND3

PEND3

NVICPEND4

PEND4

NVICUNPEND0

UNPEND0

NVICUNPEND1

UNPEND1

NVICUNPEND2

UNPEND2

NVICUNPEND3

UNPEND3

NVICUNPEND4

UNPEND4

NVICACTIVE0

ACTIVE0

NVICACTIVE1

ACTIVE1

NVICACTIVE2

ACTIVE2

NVICACTIVE3

ACTIVE3

NVICACTIVE4

ACTIVE4

NVICINT_TYPE

INT_TYPE

NVICPRI0

PRI0

NVICPRI1

PRI1

NVICPRI2

PRI2

NVICPRI3

PRI3

NVICPRI4

PRI4

NVICPRI5

PRI5

NVICPRI6

PRI6

NVICPRI7

PRI7

NVICPRI8

PRI8

NVICPRI9

PRI9

NVICPRI10

PRI10

NVICPRI11

PRI11

NVICPRI12

PRI12

NVICPRI13

PRI13

NVICPRI14

PRI14

NVICPRI15

PRI15

NVICPRI16

PRI16

NVICPRI17

PRI17

NVICPRI18

PRI18

NVICPRI19

PRI19

NVICPRI20

PRI20

NVICPRI21

PRI21

NVICPRI22

PRI22

NVICPRI23

PRI23

NVICPRI24

PRI24

NVICPRI25

PRI25

NVICPRI26

PRI26

NVICPRI27

PRI27

NVICPRI28

PRI28

NVICPRI29

PRI29

NVICPRI30

PRI30

NVICPRI31

PRI31

NVICPRI32

PRI32

NVICACTLR

ACTLR

NVICCPUID

CPUID

NVICINT_CTRL

INT_CTRL

NVICVTABLE

VTABLE

NVICAPINT

APINT

NVICSYS_CTRL

SYS_CTRL

NVICCFG_CTRL

CFG_CTRL

NVICSYS_PRI1

SYS_PRI1

NVICSYS_PRI2

SYS_PRI2

NVICSYS_PRI3

SYS_PRI3

NVICSYS_HND_CTRL

SYS_HND_CTRL

NVICFAULT_STAT

FAULT_STAT

NVICHFAULT_STAT

HFAULT_STAT

NVICDEBUG_STAT

DEBUG_STAT

NVICMM_ADDR

MM_ADDR

NVICFAULT_ADDR

FAULT_ADDR

NVICCPAC

CPAC

NVICMPU_TYPE

MPU_TYPE

NVICMPU_CTRL

MPU_CTRL

NVICMPU_NUMBER

MPU_NUMBER

NVICMPU_BASE

MPU_BASE

NVICMPU_ATTR

MPU_ATTR

NVICMPU_BASE1

MPU_BASE1

NVICMPU_ATTR1

MPU_ATTR1

NVICMPU_BASE2

MPU_BASE2

NVICMPU_ATTR2

MPU_ATTR2

NVICMPU_BASE3

MPU_BASE3

NVICMPU_ATTR3

MPU_ATTR3

NVICDBG_CTRL

DBG_CTRL

NVICDBG_XFER

DBG_XFER

NVICDBG_DATA

DBG_DATA

NVICDBG_INT

DBG_INT

NVICSW_TRIG

SW_TRIG

NVICFPCC

FPCC

NVICFPCA

FPCA

NVICFPDSC

FPDSC


NVICST_CTRL

SysTick Control and Status Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICST_CTRL NVICST_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_ST_CTRL_ENABLE NVIC_ST_CTRL_INTEN NVIC_ST_CTRL_CLK_SRC NVIC_ST_CTRL_COUNT

NVIC_ST_CTRL_ENABLE : Enable
bits : 0 - 0 (1 bit)

NVIC_ST_CTRL_INTEN : Interrupt Enable
bits : 1 - 2 (2 bit)

NVIC_ST_CTRL_CLK_SRC : Clock Source
bits : 2 - 4 (3 bit)

NVIC_ST_CTRL_COUNT : Count Flag
bits : 16 - 32 (17 bit)


ST_CTRL

SysTick Control and Status Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ST_CTRL ST_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_ST_CTRL_ENABLE NVIC_ST_CTRL_INTEN NVIC_ST_CTRL_CLK_SRC NVIC_ST_CTRL_COUNT

NVIC_ST_CTRL_ENABLE : Enable
bits : 0 - 0 (1 bit)

NVIC_ST_CTRL_INTEN : Interrupt Enable
bits : 1 - 2 (2 bit)

NVIC_ST_CTRL_CLK_SRC : Clock Source
bits : 2 - 4 (3 bit)

NVIC_ST_CTRL_COUNT : Count Flag
bits : 16 - 32 (17 bit)


NVICEN0

Interrupt 0-31 Set Enable
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICEN0 NVICEN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_EN0_INT

NVIC_EN0_INT : Interrupt Enable
bits : 0 - 31 (32 bit)

Enumeration:

0x1 : NVIC_EN0_INT0

Interrupt 0 enable

0x2 : NVIC_EN0_INT1

Interrupt 1 enable

0x4 : NVIC_EN0_INT2

Interrupt 2 enable

0x8 : NVIC_EN0_INT3

Interrupt 3 enable

0x10 : NVIC_EN0_INT4

Interrupt 4 enable

0x20 : NVIC_EN0_INT5

Interrupt 5 enable

0x40 : NVIC_EN0_INT6

Interrupt 6 enable

0x80 : NVIC_EN0_INT7

Interrupt 7 enable

0x100 : NVIC_EN0_INT8

Interrupt 8 enable

0x200 : NVIC_EN0_INT9

Interrupt 9 enable

0x400 : NVIC_EN0_INT10

Interrupt 10 enable

0x800 : NVIC_EN0_INT11

Interrupt 11 enable

0x1000 : NVIC_EN0_INT12

Interrupt 12 enable

0x2000 : NVIC_EN0_INT13

Interrupt 13 enable

0x4000 : NVIC_EN0_INT14

Interrupt 14 enable

0x8000 : NVIC_EN0_INT15

Interrupt 15 enable

0x10000 : NVIC_EN0_INT16

Interrupt 16 enable

0x20000 : NVIC_EN0_INT17

Interrupt 17 enable

0x40000 : NVIC_EN0_INT18

Interrupt 18 enable

0x80000 : NVIC_EN0_INT19

Interrupt 19 enable

0x100000 : NVIC_EN0_INT20

Interrupt 20 enable

0x200000 : NVIC_EN0_INT21

Interrupt 21 enable

0x400000 : NVIC_EN0_INT22

Interrupt 22 enable

0x800000 : NVIC_EN0_INT23

Interrupt 23 enable

0x1000000 : NVIC_EN0_INT24

Interrupt 24 enable

0x2000000 : NVIC_EN0_INT25

Interrupt 25 enable

0x4000000 : NVIC_EN0_INT26

Interrupt 26 enable

0x8000000 : NVIC_EN0_INT27

Interrupt 27 enable

0x10000000 : NVIC_EN0_INT28

Interrupt 28 enable

0x20000000 : NVIC_EN0_INT29

Interrupt 29 enable

0x40000000 : NVIC_EN0_INT30

Interrupt 30 enable

0x80000000 : NVIC_EN0_INT31

Interrupt 31 enable

End of enumeration elements list.


EN0

Interrupt 0-31 Set Enable
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN0 EN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_EN0_INT

NVIC_EN0_INT : Interrupt Enable
bits : 0 - 31 (32 bit)

Enumeration:

0x1 : NVIC_EN0_INT0

Interrupt 0 enable

0x2 : NVIC_EN0_INT1

Interrupt 1 enable

0x4 : NVIC_EN0_INT2

Interrupt 2 enable

0x8 : NVIC_EN0_INT3

Interrupt 3 enable

0x10 : NVIC_EN0_INT4

Interrupt 4 enable

0x20 : NVIC_EN0_INT5

Interrupt 5 enable

0x40 : NVIC_EN0_INT6

Interrupt 6 enable

0x80 : NVIC_EN0_INT7

Interrupt 7 enable

0x100 : NVIC_EN0_INT8

Interrupt 8 enable

0x200 : NVIC_EN0_INT9

Interrupt 9 enable

0x400 : NVIC_EN0_INT10

Interrupt 10 enable

0x800 : NVIC_EN0_INT11

Interrupt 11 enable

0x1000 : NVIC_EN0_INT12

Interrupt 12 enable

0x2000 : NVIC_EN0_INT13

Interrupt 13 enable

0x4000 : NVIC_EN0_INT14

Interrupt 14 enable

0x8000 : NVIC_EN0_INT15

Interrupt 15 enable

0x10000 : NVIC_EN0_INT16

Interrupt 16 enable

0x20000 : NVIC_EN0_INT17

Interrupt 17 enable

0x40000 : NVIC_EN0_INT18

Interrupt 18 enable

0x80000 : NVIC_EN0_INT19

Interrupt 19 enable

0x100000 : NVIC_EN0_INT20

Interrupt 20 enable

0x200000 : NVIC_EN0_INT21

Interrupt 21 enable

0x400000 : NVIC_EN0_INT22

Interrupt 22 enable

0x800000 : NVIC_EN0_INT23

Interrupt 23 enable

0x1000000 : NVIC_EN0_INT24

Interrupt 24 enable

0x2000000 : NVIC_EN0_INT25

Interrupt 25 enable

0x4000000 : NVIC_EN0_INT26

Interrupt 26 enable

0x8000000 : NVIC_EN0_INT27

Interrupt 27 enable

0x10000000 : NVIC_EN0_INT28

Interrupt 28 enable

0x20000000 : NVIC_EN0_INT29

Interrupt 29 enable

0x40000000 : NVIC_EN0_INT30

Interrupt 30 enable

0x80000000 : NVIC_EN0_INT31

Interrupt 31 enable

End of enumeration elements list.


NVICEN1

Interrupt 32-54 Set Enable
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICEN1 NVICEN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_EN1_INT

NVIC_EN1_INT : Interrupt Enable
bits : 0 - 31 (32 bit)


EN1

Interrupt 32-54 Set Enable
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN1 EN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_EN1_INT

NVIC_EN1_INT : Interrupt Enable
bits : 0 - 31 (32 bit)


NVICEN2

Interrupt 64-95 Set Enable
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICEN2 NVICEN2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_EN2_INT

NVIC_EN2_INT : Interrupt Enable
bits : 0 - 31 (32 bit)


EN2

Interrupt 64-95 Set Enable
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN2 EN2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_EN2_INT

NVIC_EN2_INT : Interrupt Enable
bits : 0 - 31 (32 bit)


NVICEN3

Interrupt 96-127 Set Enable
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICEN3 NVICEN3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_EN3_INT

NVIC_EN3_INT : Interrupt Enable
bits : 0 - 31 (32 bit)


EN3

Interrupt 96-127 Set Enable
address_offset : 0x10C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN3 EN3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_EN3_INT

NVIC_EN3_INT : Interrupt Enable
bits : 0 - 31 (32 bit)


NVICEN4

Interrupt 128-131 Set Enable
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICEN4 NVICEN4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_EN4_INT

NVIC_EN4_INT : Interrupt Enable
bits : 0 - 3 (4 bit)


EN4

Interrupt 128-131 Set Enable
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN4 EN4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_EN4_INT

NVIC_EN4_INT : Interrupt Enable
bits : 0 - 3 (4 bit)


NVICST_RELOAD

SysTick Reload Value Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICST_RELOAD NVICST_RELOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_ST_RELOAD

NVIC_ST_RELOAD : Reload Value
bits : 0 - 23 (24 bit)


ST_RELOAD

SysTick Reload Value Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ST_RELOAD ST_RELOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_ST_RELOAD

NVIC_ST_RELOAD : Reload Value
bits : 0 - 23 (24 bit)


NVICST_CURRENT

SysTick Current Value Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICST_CURRENT NVICST_CURRENT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_ST_CURRENT

NVIC_ST_CURRENT : Current Value
bits : 0 - 23 (24 bit)


ST_CURRENT

SysTick Current Value Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ST_CURRENT ST_CURRENT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_ST_CURRENT

NVIC_ST_CURRENT : Current Value
bits : 0 - 23 (24 bit)


NVICDIS0

Interrupt 0-31 Clear Enable
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICDIS0 NVICDIS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_DIS0_INT

NVIC_DIS0_INT : Interrupt Disable
bits : 0 - 31 (32 bit)

Enumeration:

0x1 : NVIC_DIS0_INT0

Interrupt 0 disable

0x2 : NVIC_DIS0_INT1

Interrupt 1 disable

0x4 : NVIC_DIS0_INT2

Interrupt 2 disable

0x8 : NVIC_DIS0_INT3

Interrupt 3 disable

0x10 : NVIC_DIS0_INT4

Interrupt 4 disable

0x20 : NVIC_DIS0_INT5

Interrupt 5 disable

0x40 : NVIC_DIS0_INT6

Interrupt 6 disable

0x80 : NVIC_DIS0_INT7

Interrupt 7 disable

0x100 : NVIC_DIS0_INT8

Interrupt 8 disable

0x200 : NVIC_DIS0_INT9

Interrupt 9 disable

0x400 : NVIC_DIS0_INT10

Interrupt 10 disable

0x800 : NVIC_DIS0_INT11

Interrupt 11 disable

0x1000 : NVIC_DIS0_INT12

Interrupt 12 disable

0x2000 : NVIC_DIS0_INT13

Interrupt 13 disable

0x4000 : NVIC_DIS0_INT14

Interrupt 14 disable

0x8000 : NVIC_DIS0_INT15

Interrupt 15 disable

0x10000 : NVIC_DIS0_INT16

Interrupt 16 disable

0x20000 : NVIC_DIS0_INT17

Interrupt 17 disable

0x40000 : NVIC_DIS0_INT18

Interrupt 18 disable

0x80000 : NVIC_DIS0_INT19

Interrupt 19 disable

0x100000 : NVIC_DIS0_INT20

Interrupt 20 disable

0x200000 : NVIC_DIS0_INT21

Interrupt 21 disable

0x400000 : NVIC_DIS0_INT22

Interrupt 22 disable

0x800000 : NVIC_DIS0_INT23

Interrupt 23 disable

0x1000000 : NVIC_DIS0_INT24

Interrupt 24 disable

0x2000000 : NVIC_DIS0_INT25

Interrupt 25 disable

0x4000000 : NVIC_DIS0_INT26

Interrupt 26 disable

0x8000000 : NVIC_DIS0_INT27

Interrupt 27 disable

0x10000000 : NVIC_DIS0_INT28

Interrupt 28 disable

0x20000000 : NVIC_DIS0_INT29

Interrupt 29 disable

0x40000000 : NVIC_DIS0_INT30

Interrupt 30 disable

0x80000000 : NVIC_DIS0_INT31

Interrupt 31 disable

End of enumeration elements list.


DIS0

Interrupt 0-31 Clear Enable
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIS0 DIS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_DIS0_INT

NVIC_DIS0_INT : Interrupt Disable
bits : 0 - 31 (32 bit)

Enumeration:

0x1 : NVIC_DIS0_INT0

Interrupt 0 disable

0x2 : NVIC_DIS0_INT1

Interrupt 1 disable

0x4 : NVIC_DIS0_INT2

Interrupt 2 disable

0x8 : NVIC_DIS0_INT3

Interrupt 3 disable

0x10 : NVIC_DIS0_INT4

Interrupt 4 disable

0x20 : NVIC_DIS0_INT5

Interrupt 5 disable

0x40 : NVIC_DIS0_INT6

Interrupt 6 disable

0x80 : NVIC_DIS0_INT7

Interrupt 7 disable

0x100 : NVIC_DIS0_INT8

Interrupt 8 disable

0x200 : NVIC_DIS0_INT9

Interrupt 9 disable

0x400 : NVIC_DIS0_INT10

Interrupt 10 disable

0x800 : NVIC_DIS0_INT11

Interrupt 11 disable

0x1000 : NVIC_DIS0_INT12

Interrupt 12 disable

0x2000 : NVIC_DIS0_INT13

Interrupt 13 disable

0x4000 : NVIC_DIS0_INT14

Interrupt 14 disable

0x8000 : NVIC_DIS0_INT15

Interrupt 15 disable

0x10000 : NVIC_DIS0_INT16

Interrupt 16 disable

0x20000 : NVIC_DIS0_INT17

Interrupt 17 disable

0x40000 : NVIC_DIS0_INT18

Interrupt 18 disable

0x80000 : NVIC_DIS0_INT19

Interrupt 19 disable

0x100000 : NVIC_DIS0_INT20

Interrupt 20 disable

0x200000 : NVIC_DIS0_INT21

Interrupt 21 disable

0x400000 : NVIC_DIS0_INT22

Interrupt 22 disable

0x800000 : NVIC_DIS0_INT23

Interrupt 23 disable

0x1000000 : NVIC_DIS0_INT24

Interrupt 24 disable

0x2000000 : NVIC_DIS0_INT25

Interrupt 25 disable

0x4000000 : NVIC_DIS0_INT26

Interrupt 26 disable

0x8000000 : NVIC_DIS0_INT27

Interrupt 27 disable

0x10000000 : NVIC_DIS0_INT28

Interrupt 28 disable

0x20000000 : NVIC_DIS0_INT29

Interrupt 29 disable

0x40000000 : NVIC_DIS0_INT30

Interrupt 30 disable

0x80000000 : NVIC_DIS0_INT31

Interrupt 31 disable

End of enumeration elements list.


NVICDIS1

Interrupt 32-54 Clear Enable
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICDIS1 NVICDIS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_DIS1_INT

NVIC_DIS1_INT : Interrupt Disable
bits : 0 - 31 (32 bit)


DIS1

Interrupt 32-54 Clear Enable
address_offset : 0x184 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIS1 DIS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_DIS1_INT

NVIC_DIS1_INT : Interrupt Disable
bits : 0 - 31 (32 bit)


NVICDIS2

Interrupt 64-95 Clear Enable
address_offset : 0x188 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICDIS2 NVICDIS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_DIS2_INT

NVIC_DIS2_INT : Interrupt Disable
bits : 0 - 31 (32 bit)


DIS2

Interrupt 64-95 Clear Enable
address_offset : 0x188 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIS2 DIS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_DIS2_INT

NVIC_DIS2_INT : Interrupt Disable
bits : 0 - 31 (32 bit)


NVICDIS3

Interrupt 96-127 Clear Enable
address_offset : 0x18C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICDIS3 NVICDIS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_DIS3_INT

NVIC_DIS3_INT : Interrupt Disable
bits : 0 - 31 (32 bit)


DIS3

Interrupt 96-127 Clear Enable
address_offset : 0x18C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIS3 DIS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_DIS3_INT

NVIC_DIS3_INT : Interrupt Disable
bits : 0 - 31 (32 bit)


NVICDIS4

Interrupt 128-131 Clear Enable
address_offset : 0x190 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICDIS4 NVICDIS4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_DIS4_INT

NVIC_DIS4_INT : Interrupt Disable
bits : 0 - 3 (4 bit)


DIS4

Interrupt 128-131 Clear Enable
address_offset : 0x190 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIS4 DIS4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_DIS4_INT

NVIC_DIS4_INT : Interrupt Disable
bits : 0 - 3 (4 bit)


NVICST_CAL

SysTick Calibration Value Reg
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICST_CAL NVICST_CAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_ST_CAL_ONEMS NVIC_ST_CAL_SKEW NVIC_ST_CAL_NOREF

NVIC_ST_CAL_ONEMS : 1ms reference value
bits : 0 - 23 (24 bit)

NVIC_ST_CAL_SKEW : Clock skew
bits : 30 - 60 (31 bit)

NVIC_ST_CAL_NOREF : No reference clock
bits : 31 - 62 (32 bit)


ST_CAL

SysTick Calibration Value Reg
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ST_CAL ST_CAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_ST_CAL_ONEMS NVIC_ST_CAL_SKEW NVIC_ST_CAL_NOREF

NVIC_ST_CAL_ONEMS : 1ms reference value
bits : 0 - 23 (24 bit)

NVIC_ST_CAL_SKEW : Clock skew
bits : 30 - 60 (31 bit)

NVIC_ST_CAL_NOREF : No reference clock
bits : 31 - 62 (32 bit)


NVICPEND0

Interrupt 0-31 Set Pending
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPEND0 NVICPEND0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PEND0_INT

NVIC_PEND0_INT : Interrupt Set Pending
bits : 0 - 31 (32 bit)

Enumeration:

0x1 : NVIC_PEND0_INT0

Interrupt 0 pend

0x2 : NVIC_PEND0_INT1

Interrupt 1 pend

0x4 : NVIC_PEND0_INT2

Interrupt 2 pend

0x8 : NVIC_PEND0_INT3

Interrupt 3 pend

0x10 : NVIC_PEND0_INT4

Interrupt 4 pend

0x20 : NVIC_PEND0_INT5

Interrupt 5 pend

0x40 : NVIC_PEND0_INT6

Interrupt 6 pend

0x80 : NVIC_PEND0_INT7

Interrupt 7 pend

0x100 : NVIC_PEND0_INT8

Interrupt 8 pend

0x200 : NVIC_PEND0_INT9

Interrupt 9 pend

0x400 : NVIC_PEND0_INT10

Interrupt 10 pend

0x800 : NVIC_PEND0_INT11

Interrupt 11 pend

0x1000 : NVIC_PEND0_INT12

Interrupt 12 pend

0x2000 : NVIC_PEND0_INT13

Interrupt 13 pend

0x4000 : NVIC_PEND0_INT14

Interrupt 14 pend

0x8000 : NVIC_PEND0_INT15

Interrupt 15 pend

0x10000 : NVIC_PEND0_INT16

Interrupt 16 pend

0x20000 : NVIC_PEND0_INT17

Interrupt 17 pend

0x40000 : NVIC_PEND0_INT18

Interrupt 18 pend

0x80000 : NVIC_PEND0_INT19

Interrupt 19 pend

0x100000 : NVIC_PEND0_INT20

Interrupt 20 pend

0x200000 : NVIC_PEND0_INT21

Interrupt 21 pend

0x400000 : NVIC_PEND0_INT22

Interrupt 22 pend

0x800000 : NVIC_PEND0_INT23

Interrupt 23 pend

0x1000000 : NVIC_PEND0_INT24

Interrupt 24 pend

0x2000000 : NVIC_PEND0_INT25

Interrupt 25 pend

0x4000000 : NVIC_PEND0_INT26

Interrupt 26 pend

0x8000000 : NVIC_PEND0_INT27

Interrupt 27 pend

0x10000000 : NVIC_PEND0_INT28

Interrupt 28 pend

0x20000000 : NVIC_PEND0_INT29

Interrupt 29 pend

0x40000000 : NVIC_PEND0_INT30

Interrupt 30 pend

0x80000000 : NVIC_PEND0_INT31

Interrupt 31 pend

End of enumeration elements list.


PEND0

Interrupt 0-31 Set Pending
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PEND0 PEND0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PEND0_INT

NVIC_PEND0_INT : Interrupt Set Pending
bits : 0 - 31 (32 bit)

Enumeration:

0x1 : NVIC_PEND0_INT0

Interrupt 0 pend

0x2 : NVIC_PEND0_INT1

Interrupt 1 pend

0x4 : NVIC_PEND0_INT2

Interrupt 2 pend

0x8 : NVIC_PEND0_INT3

Interrupt 3 pend

0x10 : NVIC_PEND0_INT4

Interrupt 4 pend

0x20 : NVIC_PEND0_INT5

Interrupt 5 pend

0x40 : NVIC_PEND0_INT6

Interrupt 6 pend

0x80 : NVIC_PEND0_INT7

Interrupt 7 pend

0x100 : NVIC_PEND0_INT8

Interrupt 8 pend

0x200 : NVIC_PEND0_INT9

Interrupt 9 pend

0x400 : NVIC_PEND0_INT10

Interrupt 10 pend

0x800 : NVIC_PEND0_INT11

Interrupt 11 pend

0x1000 : NVIC_PEND0_INT12

Interrupt 12 pend

0x2000 : NVIC_PEND0_INT13

Interrupt 13 pend

0x4000 : NVIC_PEND0_INT14

Interrupt 14 pend

0x8000 : NVIC_PEND0_INT15

Interrupt 15 pend

0x10000 : NVIC_PEND0_INT16

Interrupt 16 pend

0x20000 : NVIC_PEND0_INT17

Interrupt 17 pend

0x40000 : NVIC_PEND0_INT18

Interrupt 18 pend

0x80000 : NVIC_PEND0_INT19

Interrupt 19 pend

0x100000 : NVIC_PEND0_INT20

Interrupt 20 pend

0x200000 : NVIC_PEND0_INT21

Interrupt 21 pend

0x400000 : NVIC_PEND0_INT22

Interrupt 22 pend

0x800000 : NVIC_PEND0_INT23

Interrupt 23 pend

0x1000000 : NVIC_PEND0_INT24

Interrupt 24 pend

0x2000000 : NVIC_PEND0_INT25

Interrupt 25 pend

0x4000000 : NVIC_PEND0_INT26

Interrupt 26 pend

0x8000000 : NVIC_PEND0_INT27

Interrupt 27 pend

0x10000000 : NVIC_PEND0_INT28

Interrupt 28 pend

0x20000000 : NVIC_PEND0_INT29

Interrupt 29 pend

0x40000000 : NVIC_PEND0_INT30

Interrupt 30 pend

0x80000000 : NVIC_PEND0_INT31

Interrupt 31 pend

End of enumeration elements list.


NVICPEND1

Interrupt 32-54 Set Pending
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPEND1 NVICPEND1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PEND1_INT

NVIC_PEND1_INT : Interrupt Set Pending
bits : 0 - 31 (32 bit)


PEND1

Interrupt 32-54 Set Pending
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PEND1 PEND1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PEND1_INT

NVIC_PEND1_INT : Interrupt Set Pending
bits : 0 - 31 (32 bit)


NVICPEND2

Interrupt 64-95 Set Pending
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPEND2 NVICPEND2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PEND2_INT

NVIC_PEND2_INT : Interrupt Set Pending
bits : 0 - 31 (32 bit)


PEND2

Interrupt 64-95 Set Pending
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PEND2 PEND2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PEND2_INT

NVIC_PEND2_INT : Interrupt Set Pending
bits : 0 - 31 (32 bit)


NVICPEND3

Interrupt 96-127 Set Pending
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPEND3 NVICPEND3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PEND3_INT

NVIC_PEND3_INT : Interrupt Set Pending
bits : 0 - 31 (32 bit)


PEND3

Interrupt 96-127 Set Pending
address_offset : 0x20C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PEND3 PEND3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PEND3_INT

NVIC_PEND3_INT : Interrupt Set Pending
bits : 0 - 31 (32 bit)


NVICPEND4

Interrupt 128-131 Set Pending
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPEND4 NVICPEND4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PEND4_INT

NVIC_PEND4_INT : Interrupt Set Pending
bits : 0 - 3 (4 bit)


PEND4

Interrupt 128-131 Set Pending
address_offset : 0x210 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PEND4 PEND4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PEND4_INT

NVIC_PEND4_INT : Interrupt Set Pending
bits : 0 - 3 (4 bit)


NVICUNPEND0

Interrupt 0-31 Clear Pending
address_offset : 0x280 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICUNPEND0 NVICUNPEND0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_UNPEND0_INT

NVIC_UNPEND0_INT : Interrupt Clear Pending
bits : 0 - 31 (32 bit)

Enumeration:

0x1 : NVIC_UNPEND0_INT0

Interrupt 0 unpend

0x2 : NVIC_UNPEND0_INT1

Interrupt 1 unpend

0x4 : NVIC_UNPEND0_INT2

Interrupt 2 unpend

0x8 : NVIC_UNPEND0_INT3

Interrupt 3 unpend

0x10 : NVIC_UNPEND0_INT4

Interrupt 4 unpend

0x20 : NVIC_UNPEND0_INT5

Interrupt 5 unpend

0x40 : NVIC_UNPEND0_INT6

Interrupt 6 unpend

0x80 : NVIC_UNPEND0_INT7

Interrupt 7 unpend

0x100 : NVIC_UNPEND0_INT8

Interrupt 8 unpend

0x200 : NVIC_UNPEND0_INT9

Interrupt 9 unpend

0x400 : NVIC_UNPEND0_INT10

Interrupt 10 unpend

0x800 : NVIC_UNPEND0_INT11

Interrupt 11 unpend

0x1000 : NVIC_UNPEND0_INT12

Interrupt 12 unpend

0x2000 : NVIC_UNPEND0_INT13

Interrupt 13 unpend

0x4000 : NVIC_UNPEND0_INT14

Interrupt 14 unpend

0x8000 : NVIC_UNPEND0_INT15

Interrupt 15 unpend

0x10000 : NVIC_UNPEND0_INT16

Interrupt 16 unpend

0x20000 : NVIC_UNPEND0_INT17

Interrupt 17 unpend

0x40000 : NVIC_UNPEND0_INT18

Interrupt 18 unpend

0x80000 : NVIC_UNPEND0_INT19

Interrupt 19 unpend

0x100000 : NVIC_UNPEND0_INT20

Interrupt 20 unpend

0x200000 : NVIC_UNPEND0_INT21

Interrupt 21 unpend

0x400000 : NVIC_UNPEND0_INT22

Interrupt 22 unpend

0x800000 : NVIC_UNPEND0_INT23

Interrupt 23 unpend

0x1000000 : NVIC_UNPEND0_INT24

Interrupt 24 unpend

0x2000000 : NVIC_UNPEND0_INT25

Interrupt 25 unpend

0x4000000 : NVIC_UNPEND0_INT26

Interrupt 26 unpend

0x8000000 : NVIC_UNPEND0_INT27

Interrupt 27 unpend

0x10000000 : NVIC_UNPEND0_INT28

Interrupt 28 unpend

0x20000000 : NVIC_UNPEND0_INT29

Interrupt 29 unpend

0x40000000 : NVIC_UNPEND0_INT30

Interrupt 30 unpend

0x80000000 : NVIC_UNPEND0_INT31

Interrupt 31 unpend

End of enumeration elements list.


UNPEND0

Interrupt 0-31 Clear Pending
address_offset : 0x280 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UNPEND0 UNPEND0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_UNPEND0_INT

NVIC_UNPEND0_INT : Interrupt Clear Pending
bits : 0 - 31 (32 bit)

Enumeration:

0x1 : NVIC_UNPEND0_INT0

Interrupt 0 unpend

0x2 : NVIC_UNPEND0_INT1

Interrupt 1 unpend

0x4 : NVIC_UNPEND0_INT2

Interrupt 2 unpend

0x8 : NVIC_UNPEND0_INT3

Interrupt 3 unpend

0x10 : NVIC_UNPEND0_INT4

Interrupt 4 unpend

0x20 : NVIC_UNPEND0_INT5

Interrupt 5 unpend

0x40 : NVIC_UNPEND0_INT6

Interrupt 6 unpend

0x80 : NVIC_UNPEND0_INT7

Interrupt 7 unpend

0x100 : NVIC_UNPEND0_INT8

Interrupt 8 unpend

0x200 : NVIC_UNPEND0_INT9

Interrupt 9 unpend

0x400 : NVIC_UNPEND0_INT10

Interrupt 10 unpend

0x800 : NVIC_UNPEND0_INT11

Interrupt 11 unpend

0x1000 : NVIC_UNPEND0_INT12

Interrupt 12 unpend

0x2000 : NVIC_UNPEND0_INT13

Interrupt 13 unpend

0x4000 : NVIC_UNPEND0_INT14

Interrupt 14 unpend

0x8000 : NVIC_UNPEND0_INT15

Interrupt 15 unpend

0x10000 : NVIC_UNPEND0_INT16

Interrupt 16 unpend

0x20000 : NVIC_UNPEND0_INT17

Interrupt 17 unpend

0x40000 : NVIC_UNPEND0_INT18

Interrupt 18 unpend

0x80000 : NVIC_UNPEND0_INT19

Interrupt 19 unpend

0x100000 : NVIC_UNPEND0_INT20

Interrupt 20 unpend

0x200000 : NVIC_UNPEND0_INT21

Interrupt 21 unpend

0x400000 : NVIC_UNPEND0_INT22

Interrupt 22 unpend

0x800000 : NVIC_UNPEND0_INT23

Interrupt 23 unpend

0x1000000 : NVIC_UNPEND0_INT24

Interrupt 24 unpend

0x2000000 : NVIC_UNPEND0_INT25

Interrupt 25 unpend

0x4000000 : NVIC_UNPEND0_INT26

Interrupt 26 unpend

0x8000000 : NVIC_UNPEND0_INT27

Interrupt 27 unpend

0x10000000 : NVIC_UNPEND0_INT28

Interrupt 28 unpend

0x20000000 : NVIC_UNPEND0_INT29

Interrupt 29 unpend

0x40000000 : NVIC_UNPEND0_INT30

Interrupt 30 unpend

0x80000000 : NVIC_UNPEND0_INT31

Interrupt 31 unpend

End of enumeration elements list.


NVICUNPEND1

Interrupt 32-54 Clear Pending
address_offset : 0x284 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICUNPEND1 NVICUNPEND1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_UNPEND1_INT

NVIC_UNPEND1_INT : Interrupt Clear Pending
bits : 0 - 31 (32 bit)

Enumeration:

0x1 : NVIC_UNPEND1_INT32

Interrupt 32 unpend

0x2 : NVIC_UNPEND1_INT33

Interrupt 33 unpend

0x4 : NVIC_UNPEND1_INT34

Interrupt 34 unpend

0x8 : NVIC_UNPEND1_INT35

Interrupt 35 unpend

0x10 : NVIC_UNPEND1_INT36

Interrupt 36 unpend

0x20 : NVIC_UNPEND1_INT37

Interrupt 37 unpend

0x40 : NVIC_UNPEND1_INT38

Interrupt 38 unpend

0x80 : NVIC_UNPEND1_INT39

Interrupt 39 unpend

0x100 : NVIC_UNPEND1_INT40

Interrupt 40 unpend

0x200 : NVIC_UNPEND1_INT41

Interrupt 41 unpend

0x400 : NVIC_UNPEND1_INT42

Interrupt 42 unpend

0x800 : NVIC_UNPEND1_INT43

Interrupt 43 unpend

0x1000 : NVIC_UNPEND1_INT44

Interrupt 44 unpend

0x2000 : NVIC_UNPEND1_INT45

Interrupt 45 unpend

0x4000 : NVIC_UNPEND1_INT46

Interrupt 46 unpend

0x8000 : NVIC_UNPEND1_INT47

Interrupt 47 unpend

0x10000 : NVIC_UNPEND1_INT48

Interrupt 48 unpend

0x20000 : NVIC_UNPEND1_INT49

Interrupt 49 unpend

0x40000 : NVIC_UNPEND1_INT50

Interrupt 50 unpend

0x80000 : NVIC_UNPEND1_INT51

Interrupt 51 unpend

0x100000 : NVIC_UNPEND1_INT52

Interrupt 52 unpend

0x200000 : NVIC_UNPEND1_INT53

Interrupt 53 unpend

0x400000 : NVIC_UNPEND1_INT54

Interrupt 54 unpend

0x800000 : NVIC_UNPEND1_INT55

Interrupt 55 unpend

End of enumeration elements list.


UNPEND1

Interrupt 32-54 Clear Pending
address_offset : 0x284 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UNPEND1 UNPEND1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_UNPEND1_INT

NVIC_UNPEND1_INT : Interrupt Clear Pending
bits : 0 - 31 (32 bit)

Enumeration:

0x1 : NVIC_UNPEND1_INT32

Interrupt 32 unpend

0x2 : NVIC_UNPEND1_INT33

Interrupt 33 unpend

0x4 : NVIC_UNPEND1_INT34

Interrupt 34 unpend

0x8 : NVIC_UNPEND1_INT35

Interrupt 35 unpend

0x10 : NVIC_UNPEND1_INT36

Interrupt 36 unpend

0x20 : NVIC_UNPEND1_INT37

Interrupt 37 unpend

0x40 : NVIC_UNPEND1_INT38

Interrupt 38 unpend

0x80 : NVIC_UNPEND1_INT39

Interrupt 39 unpend

0x100 : NVIC_UNPEND1_INT40

Interrupt 40 unpend

0x200 : NVIC_UNPEND1_INT41

Interrupt 41 unpend

0x400 : NVIC_UNPEND1_INT42

Interrupt 42 unpend

0x800 : NVIC_UNPEND1_INT43

Interrupt 43 unpend

0x1000 : NVIC_UNPEND1_INT44

Interrupt 44 unpend

0x2000 : NVIC_UNPEND1_INT45

Interrupt 45 unpend

0x4000 : NVIC_UNPEND1_INT46

Interrupt 46 unpend

0x8000 : NVIC_UNPEND1_INT47

Interrupt 47 unpend

0x10000 : NVIC_UNPEND1_INT48

Interrupt 48 unpend

0x20000 : NVIC_UNPEND1_INT49

Interrupt 49 unpend

0x40000 : NVIC_UNPEND1_INT50

Interrupt 50 unpend

0x80000 : NVIC_UNPEND1_INT51

Interrupt 51 unpend

0x100000 : NVIC_UNPEND1_INT52

Interrupt 52 unpend

0x200000 : NVIC_UNPEND1_INT53

Interrupt 53 unpend

0x400000 : NVIC_UNPEND1_INT54

Interrupt 54 unpend

0x800000 : NVIC_UNPEND1_INT55

Interrupt 55 unpend

End of enumeration elements list.


NVICUNPEND2

Interrupt 64-95 Clear Pending
address_offset : 0x288 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICUNPEND2 NVICUNPEND2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_UNPEND2_INT

NVIC_UNPEND2_INT : Interrupt Clear Pending
bits : 0 - 31 (32 bit)


UNPEND2

Interrupt 64-95 Clear Pending
address_offset : 0x288 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UNPEND2 UNPEND2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_UNPEND2_INT

NVIC_UNPEND2_INT : Interrupt Clear Pending
bits : 0 - 31 (32 bit)


NVICUNPEND3

Interrupt 96-127 Clear Pending
address_offset : 0x28C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICUNPEND3 NVICUNPEND3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_UNPEND3_INT

NVIC_UNPEND3_INT : Interrupt Clear Pending
bits : 0 - 31 (32 bit)


UNPEND3

Interrupt 96-127 Clear Pending
address_offset : 0x28C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UNPEND3 UNPEND3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_UNPEND3_INT

NVIC_UNPEND3_INT : Interrupt Clear Pending
bits : 0 - 31 (32 bit)


NVICUNPEND4

Interrupt 128-131 Clear Pending
address_offset : 0x290 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICUNPEND4 NVICUNPEND4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_UNPEND4_INT

NVIC_UNPEND4_INT : Interrupt Clear Pending
bits : 0 - 3 (4 bit)


UNPEND4

Interrupt 128-131 Clear Pending
address_offset : 0x290 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UNPEND4 UNPEND4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_UNPEND4_INT

NVIC_UNPEND4_INT : Interrupt Clear Pending
bits : 0 - 3 (4 bit)


NVICACTIVE0

Interrupt 0-31 Active Bit
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICACTIVE0 NVICACTIVE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_ACTIVE0_INT

NVIC_ACTIVE0_INT : Interrupt Active
bits : 0 - 31 (32 bit)

Enumeration:

0x1 : NVIC_ACTIVE0_INT0

Interrupt 0 active

0x2 : NVIC_ACTIVE0_INT1

Interrupt 1 active

0x4 : NVIC_ACTIVE0_INT2

Interrupt 2 active

0x8 : NVIC_ACTIVE0_INT3

Interrupt 3 active

0x10 : NVIC_ACTIVE0_INT4

Interrupt 4 active

0x20 : NVIC_ACTIVE0_INT5

Interrupt 5 active

0x40 : NVIC_ACTIVE0_INT6

Interrupt 6 active

0x80 : NVIC_ACTIVE0_INT7

Interrupt 7 active

0x100 : NVIC_ACTIVE0_INT8

Interrupt 8 active

0x200 : NVIC_ACTIVE0_INT9

Interrupt 9 active

0x400 : NVIC_ACTIVE0_INT10

Interrupt 10 active

0x800 : NVIC_ACTIVE0_INT11

Interrupt 11 active

0x1000 : NVIC_ACTIVE0_INT12

Interrupt 12 active

0x2000 : NVIC_ACTIVE0_INT13

Interrupt 13 active

0x4000 : NVIC_ACTIVE0_INT14

Interrupt 14 active

0x8000 : NVIC_ACTIVE0_INT15

Interrupt 15 active

0x10000 : NVIC_ACTIVE0_INT16

Interrupt 16 active

0x20000 : NVIC_ACTIVE0_INT17

Interrupt 17 active

0x40000 : NVIC_ACTIVE0_INT18

Interrupt 18 active

0x80000 : NVIC_ACTIVE0_INT19

Interrupt 19 active

0x100000 : NVIC_ACTIVE0_INT20

Interrupt 20 active

0x200000 : NVIC_ACTIVE0_INT21

Interrupt 21 active

0x400000 : NVIC_ACTIVE0_INT22

Interrupt 22 active

0x800000 : NVIC_ACTIVE0_INT23

Interrupt 23 active

0x1000000 : NVIC_ACTIVE0_INT24

Interrupt 24 active

0x2000000 : NVIC_ACTIVE0_INT25

Interrupt 25 active

0x4000000 : NVIC_ACTIVE0_INT26

Interrupt 26 active

0x8000000 : NVIC_ACTIVE0_INT27

Interrupt 27 active

0x10000000 : NVIC_ACTIVE0_INT28

Interrupt 28 active

0x20000000 : NVIC_ACTIVE0_INT29

Interrupt 29 active

0x40000000 : NVIC_ACTIVE0_INT30

Interrupt 30 active

0x80000000 : NVIC_ACTIVE0_INT31

Interrupt 31 active

End of enumeration elements list.


ACTIVE0

Interrupt 0-31 Active Bit
address_offset : 0x300 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACTIVE0 ACTIVE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_ACTIVE0_INT

NVIC_ACTIVE0_INT : Interrupt Active
bits : 0 - 31 (32 bit)

Enumeration:

0x1 : NVIC_ACTIVE0_INT0

Interrupt 0 active

0x2 : NVIC_ACTIVE0_INT1

Interrupt 1 active

0x4 : NVIC_ACTIVE0_INT2

Interrupt 2 active

0x8 : NVIC_ACTIVE0_INT3

Interrupt 3 active

0x10 : NVIC_ACTIVE0_INT4

Interrupt 4 active

0x20 : NVIC_ACTIVE0_INT5

Interrupt 5 active

0x40 : NVIC_ACTIVE0_INT6

Interrupt 6 active

0x80 : NVIC_ACTIVE0_INT7

Interrupt 7 active

0x100 : NVIC_ACTIVE0_INT8

Interrupt 8 active

0x200 : NVIC_ACTIVE0_INT9

Interrupt 9 active

0x400 : NVIC_ACTIVE0_INT10

Interrupt 10 active

0x800 : NVIC_ACTIVE0_INT11

Interrupt 11 active

0x1000 : NVIC_ACTIVE0_INT12

Interrupt 12 active

0x2000 : NVIC_ACTIVE0_INT13

Interrupt 13 active

0x4000 : NVIC_ACTIVE0_INT14

Interrupt 14 active

0x8000 : NVIC_ACTIVE0_INT15

Interrupt 15 active

0x10000 : NVIC_ACTIVE0_INT16

Interrupt 16 active

0x20000 : NVIC_ACTIVE0_INT17

Interrupt 17 active

0x40000 : NVIC_ACTIVE0_INT18

Interrupt 18 active

0x80000 : NVIC_ACTIVE0_INT19

Interrupt 19 active

0x100000 : NVIC_ACTIVE0_INT20

Interrupt 20 active

0x200000 : NVIC_ACTIVE0_INT21

Interrupt 21 active

0x400000 : NVIC_ACTIVE0_INT22

Interrupt 22 active

0x800000 : NVIC_ACTIVE0_INT23

Interrupt 23 active

0x1000000 : NVIC_ACTIVE0_INT24

Interrupt 24 active

0x2000000 : NVIC_ACTIVE0_INT25

Interrupt 25 active

0x4000000 : NVIC_ACTIVE0_INT26

Interrupt 26 active

0x8000000 : NVIC_ACTIVE0_INT27

Interrupt 27 active

0x10000000 : NVIC_ACTIVE0_INT28

Interrupt 28 active

0x20000000 : NVIC_ACTIVE0_INT29

Interrupt 29 active

0x40000000 : NVIC_ACTIVE0_INT30

Interrupt 30 active

0x80000000 : NVIC_ACTIVE0_INT31

Interrupt 31 active

End of enumeration elements list.


NVICACTIVE1

Interrupt 32-54 Active Bit
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICACTIVE1 NVICACTIVE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_ACTIVE1_INT

NVIC_ACTIVE1_INT : Interrupt Active
bits : 0 - 31 (32 bit)


ACTIVE1

Interrupt 32-54 Active Bit
address_offset : 0x304 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACTIVE1 ACTIVE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_ACTIVE1_INT

NVIC_ACTIVE1_INT : Interrupt Active
bits : 0 - 31 (32 bit)


NVICACTIVE2

Interrupt 64-95 Active Bit
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICACTIVE2 NVICACTIVE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_ACTIVE2_INT

NVIC_ACTIVE2_INT : Interrupt Active
bits : 0 - 31 (32 bit)


ACTIVE2

Interrupt 64-95 Active Bit
address_offset : 0x308 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACTIVE2 ACTIVE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_ACTIVE2_INT

NVIC_ACTIVE2_INT : Interrupt Active
bits : 0 - 31 (32 bit)


NVICACTIVE3

Interrupt 96-127 Active Bit
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICACTIVE3 NVICACTIVE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_ACTIVE3_INT

NVIC_ACTIVE3_INT : Interrupt Active
bits : 0 - 31 (32 bit)


ACTIVE3

Interrupt 96-127 Active Bit
address_offset : 0x30C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACTIVE3 ACTIVE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_ACTIVE3_INT

NVIC_ACTIVE3_INT : Interrupt Active
bits : 0 - 31 (32 bit)


NVICACTIVE4

Interrupt 128-131 Active Bit
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICACTIVE4 NVICACTIVE4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_ACTIVE4_INT

NVIC_ACTIVE4_INT : Interrupt Active
bits : 0 - 3 (4 bit)


ACTIVE4

Interrupt 128-131 Active Bit
address_offset : 0x310 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACTIVE4 ACTIVE4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_ACTIVE4_INT

NVIC_ACTIVE4_INT : Interrupt Active
bits : 0 - 3 (4 bit)


NVICINT_TYPE

Interrupt Controller Type Reg
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICINT_TYPE NVICINT_TYPE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_INT_TYPE_LINES

NVIC_INT_TYPE_LINES : Number of interrupt lines (x32)
bits : 0 - 4 (5 bit)


INT_TYPE

Interrupt Controller Type Reg
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_TYPE INT_TYPE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_INT_TYPE_LINES

NVIC_INT_TYPE_LINES : Number of interrupt lines (x32)
bits : 0 - 4 (5 bit)


NVICPRI0

Interrupt 0-3 Priority
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI0 NVICPRI0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI0_INT0 NVIC_PRI0_INT1 NVIC_PRI0_INT2 NVIC_PRI0_INT3

NVIC_PRI0_INT0 : Interrupt 0 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI0_INT1 : Interrupt 1 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI0_INT2 : Interrupt 2 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI0_INT3 : Interrupt 3 Priority Mask
bits : 29 - 60 (32 bit)


PRI0

Interrupt 0-3 Priority
address_offset : 0x400 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI0 PRI0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI0_INT0 NVIC_PRI0_INT1 NVIC_PRI0_INT2 NVIC_PRI0_INT3

NVIC_PRI0_INT0 : Interrupt 0 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI0_INT1 : Interrupt 1 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI0_INT2 : Interrupt 2 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI0_INT3 : Interrupt 3 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI1

Interrupt 4-7 Priority
address_offset : 0x404 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI1 NVICPRI1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI1_INT4 NVIC_PRI1_INT5 NVIC_PRI1_INT6 NVIC_PRI1_INT7

NVIC_PRI1_INT4 : Interrupt 4 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI1_INT5 : Interrupt 5 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI1_INT6 : Interrupt 6 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI1_INT7 : Interrupt 7 Priority Mask
bits : 29 - 60 (32 bit)


PRI1

Interrupt 4-7 Priority
address_offset : 0x404 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI1 PRI1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI1_INT4 NVIC_PRI1_INT5 NVIC_PRI1_INT6 NVIC_PRI1_INT7

NVIC_PRI1_INT4 : Interrupt 4 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI1_INT5 : Interrupt 5 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI1_INT6 : Interrupt 6 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI1_INT7 : Interrupt 7 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI2

Interrupt 8-11 Priority
address_offset : 0x408 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI2 NVICPRI2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI2_INT8 NVIC_PRI2_INT9 NVIC_PRI2_INT10 NVIC_PRI2_INT11

NVIC_PRI2_INT8 : Interrupt 8 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI2_INT9 : Interrupt 9 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI2_INT10 : Interrupt 10 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI2_INT11 : Interrupt 11 Priority Mask
bits : 29 - 60 (32 bit)


PRI2

Interrupt 8-11 Priority
address_offset : 0x408 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI2 PRI2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI2_INT8 NVIC_PRI2_INT9 NVIC_PRI2_INT10 NVIC_PRI2_INT11

NVIC_PRI2_INT8 : Interrupt 8 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI2_INT9 : Interrupt 9 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI2_INT10 : Interrupt 10 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI2_INT11 : Interrupt 11 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI3

Interrupt 12-15 Priority
address_offset : 0x40C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI3 NVICPRI3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI3_INT12 NVIC_PRI3_INT13 NVIC_PRI3_INT14 NVIC_PRI3_INT15

NVIC_PRI3_INT12 : Interrupt 12 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI3_INT13 : Interrupt 13 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI3_INT14 : Interrupt 14 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI3_INT15 : Interrupt 15 Priority Mask
bits : 29 - 60 (32 bit)


PRI3

Interrupt 12-15 Priority
address_offset : 0x40C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI3 PRI3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI3_INT12 NVIC_PRI3_INT13 NVIC_PRI3_INT14 NVIC_PRI3_INT15

NVIC_PRI3_INT12 : Interrupt 12 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI3_INT13 : Interrupt 13 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI3_INT14 : Interrupt 14 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI3_INT15 : Interrupt 15 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI4

Interrupt 16-19 Priority
address_offset : 0x410 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI4 NVICPRI4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI4_INT16 NVIC_PRI4_INT17 NVIC_PRI4_INT18 NVIC_PRI4_INT19

NVIC_PRI4_INT16 : Interrupt 16 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI4_INT17 : Interrupt 17 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI4_INT18 : Interrupt 18 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI4_INT19 : Interrupt 19 Priority Mask
bits : 29 - 60 (32 bit)


PRI4

Interrupt 16-19 Priority
address_offset : 0x410 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI4 PRI4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI4_INT16 NVIC_PRI4_INT17 NVIC_PRI4_INT18 NVIC_PRI4_INT19

NVIC_PRI4_INT16 : Interrupt 16 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI4_INT17 : Interrupt 17 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI4_INT18 : Interrupt 18 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI4_INT19 : Interrupt 19 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI5

Interrupt 20-23 Priority
address_offset : 0x414 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI5 NVICPRI5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI5_INT20 NVIC_PRI5_INT21 NVIC_PRI5_INT22 NVIC_PRI5_INT23

NVIC_PRI5_INT20 : Interrupt 20 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI5_INT21 : Interrupt 21 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI5_INT22 : Interrupt 22 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI5_INT23 : Interrupt 23 Priority Mask
bits : 29 - 60 (32 bit)


PRI5

Interrupt 20-23 Priority
address_offset : 0x414 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI5 PRI5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI5_INT20 NVIC_PRI5_INT21 NVIC_PRI5_INT22 NVIC_PRI5_INT23

NVIC_PRI5_INT20 : Interrupt 20 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI5_INT21 : Interrupt 21 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI5_INT22 : Interrupt 22 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI5_INT23 : Interrupt 23 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI6

Interrupt 24-27 Priority
address_offset : 0x418 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI6 NVICPRI6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI6_INT24 NVIC_PRI6_INT25 NVIC_PRI6_INT26 NVIC_PRI6_INT27

NVIC_PRI6_INT24 : Interrupt 24 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI6_INT25 : Interrupt 25 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI6_INT26 : Interrupt 26 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI6_INT27 : Interrupt 27 Priority Mask
bits : 29 - 60 (32 bit)


PRI6

Interrupt 24-27 Priority
address_offset : 0x418 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI6 PRI6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI6_INT24 NVIC_PRI6_INT25 NVIC_PRI6_INT26 NVIC_PRI6_INT27

NVIC_PRI6_INT24 : Interrupt 24 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI6_INT25 : Interrupt 25 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI6_INT26 : Interrupt 26 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI6_INT27 : Interrupt 27 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI7

Interrupt 28-31 Priority
address_offset : 0x41C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI7 NVICPRI7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI7_INT28 NVIC_PRI7_INT29 NVIC_PRI7_INT30 NVIC_PRI7_INT31

NVIC_PRI7_INT28 : Interrupt 28 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI7_INT29 : Interrupt 29 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI7_INT30 : Interrupt 30 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI7_INT31 : Interrupt 31 Priority Mask
bits : 29 - 60 (32 bit)


PRI7

Interrupt 28-31 Priority
address_offset : 0x41C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI7 PRI7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI7_INT28 NVIC_PRI7_INT29 NVIC_PRI7_INT30 NVIC_PRI7_INT31

NVIC_PRI7_INT28 : Interrupt 28 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI7_INT29 : Interrupt 29 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI7_INT30 : Interrupt 30 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI7_INT31 : Interrupt 31 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI8

Interrupt 32-35 Priority
address_offset : 0x420 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI8 NVICPRI8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI8_INT32 NVIC_PRI8_INT33 NVIC_PRI8_INT34 NVIC_PRI8_INT35

NVIC_PRI8_INT32 : Interrupt 32 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI8_INT33 : Interrupt 33 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI8_INT34 : Interrupt 34 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI8_INT35 : Interrupt 35 Priority Mask
bits : 29 - 60 (32 bit)


PRI8

Interrupt 32-35 Priority
address_offset : 0x420 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI8 PRI8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI8_INT32 NVIC_PRI8_INT33 NVIC_PRI8_INT34 NVIC_PRI8_INT35

NVIC_PRI8_INT32 : Interrupt 32 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI8_INT33 : Interrupt 33 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI8_INT34 : Interrupt 34 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI8_INT35 : Interrupt 35 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI9

Interrupt 36-39 Priority
address_offset : 0x424 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI9 NVICPRI9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI9_INT36 NVIC_PRI9_INT37 NVIC_PRI9_INT38 NVIC_PRI9_INT39

NVIC_PRI9_INT36 : Interrupt 36 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI9_INT37 : Interrupt 37 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI9_INT38 : Interrupt 38 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI9_INT39 : Interrupt 39 Priority Mask
bits : 29 - 60 (32 bit)


PRI9

Interrupt 36-39 Priority
address_offset : 0x424 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI9 PRI9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI9_INT36 NVIC_PRI9_INT37 NVIC_PRI9_INT38 NVIC_PRI9_INT39

NVIC_PRI9_INT36 : Interrupt 36 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI9_INT37 : Interrupt 37 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI9_INT38 : Interrupt 38 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI9_INT39 : Interrupt 39 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI10

Interrupt 40-43 Priority
address_offset : 0x428 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI10 NVICPRI10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI10_INT40 NVIC_PRI10_INT41 NVIC_PRI10_INT42 NVIC_PRI10_INT43

NVIC_PRI10_INT40 : Interrupt 40 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI10_INT41 : Interrupt 41 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI10_INT42 : Interrupt 42 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI10_INT43 : Interrupt 43 Priority Mask
bits : 29 - 60 (32 bit)


PRI10

Interrupt 40-43 Priority
address_offset : 0x428 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI10 PRI10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI10_INT40 NVIC_PRI10_INT41 NVIC_PRI10_INT42 NVIC_PRI10_INT43

NVIC_PRI10_INT40 : Interrupt 40 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI10_INT41 : Interrupt 41 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI10_INT42 : Interrupt 42 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI10_INT43 : Interrupt 43 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI11

Interrupt 44-47 Priority
address_offset : 0x42C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI11 NVICPRI11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI11_INT44 NVIC_PRI11_INT45 NVIC_PRI11_INT46 NVIC_PRI11_INT47

NVIC_PRI11_INT44 : Interrupt 44 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI11_INT45 : Interrupt 45 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI11_INT46 : Interrupt 46 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI11_INT47 : Interrupt 47 Priority Mask
bits : 29 - 60 (32 bit)


PRI11

Interrupt 44-47 Priority
address_offset : 0x42C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI11 PRI11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI11_INT44 NVIC_PRI11_INT45 NVIC_PRI11_INT46 NVIC_PRI11_INT47

NVIC_PRI11_INT44 : Interrupt 44 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI11_INT45 : Interrupt 45 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI11_INT46 : Interrupt 46 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI11_INT47 : Interrupt 47 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI12

Interrupt 48-51 Priority
address_offset : 0x430 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI12 NVICPRI12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI12_INT48 NVIC_PRI12_INT49 NVIC_PRI12_INT50 NVIC_PRI12_INT51

NVIC_PRI12_INT48 : Interrupt 48 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI12_INT49 : Interrupt 49 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI12_INT50 : Interrupt 50 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI12_INT51 : Interrupt 51 Priority Mask
bits : 29 - 60 (32 bit)


PRI12

Interrupt 48-51 Priority
address_offset : 0x430 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI12 PRI12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI12_INT48 NVIC_PRI12_INT49 NVIC_PRI12_INT50 NVIC_PRI12_INT51

NVIC_PRI12_INT48 : Interrupt 48 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI12_INT49 : Interrupt 49 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI12_INT50 : Interrupt 50 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI12_INT51 : Interrupt 51 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI13

Interrupt 52-53 Priority
address_offset : 0x434 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI13 NVICPRI13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI13_INT52 NVIC_PRI13_INT53 NVIC_PRI13_INT54 NVIC_PRI13_INT55

NVIC_PRI13_INT52 : Interrupt 52 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI13_INT53 : Interrupt 53 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI13_INT54 : Interrupt 54 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI13_INT55 : Interrupt 55 Priority Mask
bits : 29 - 60 (32 bit)


PRI13

Interrupt 52-53 Priority
address_offset : 0x434 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI13 PRI13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI13_INT52 NVIC_PRI13_INT53 NVIC_PRI13_INT54 NVIC_PRI13_INT55

NVIC_PRI13_INT52 : Interrupt 52 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI13_INT53 : Interrupt 53 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI13_INT54 : Interrupt 54 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI13_INT55 : Interrupt 55 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI14

Interrupt 56-59 Priority
address_offset : 0x438 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI14 NVICPRI14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI14_INTA NVIC_PRI14_INTB NVIC_PRI14_INTC NVIC_PRI14_INTD

NVIC_PRI14_INTA : Interrupt 56 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI14_INTB : Interrupt 57 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI14_INTC : Interrupt 58 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI14_INTD : Interrupt 59 Priority Mask
bits : 29 - 60 (32 bit)


PRI14

Interrupt 56-59 Priority
address_offset : 0x438 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI14 PRI14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI14_INTA NVIC_PRI14_INTB NVIC_PRI14_INTC NVIC_PRI14_INTD

NVIC_PRI14_INTA : Interrupt 56 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI14_INTB : Interrupt 57 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI14_INTC : Interrupt 58 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI14_INTD : Interrupt 59 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI15

Interrupt 60-63 Priority
address_offset : 0x43C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI15 NVICPRI15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI15_INTA NVIC_PRI15_INTB NVIC_PRI15_INTC NVIC_PRI15_INTD

NVIC_PRI15_INTA : Interrupt 60 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI15_INTB : Interrupt 61 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI15_INTC : Interrupt 62 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI15_INTD : Interrupt 63 Priority Mask
bits : 29 - 60 (32 bit)


PRI15

Interrupt 60-63 Priority
address_offset : 0x43C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI15 PRI15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI15_INTA NVIC_PRI15_INTB NVIC_PRI15_INTC NVIC_PRI15_INTD

NVIC_PRI15_INTA : Interrupt 60 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI15_INTB : Interrupt 61 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI15_INTC : Interrupt 62 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI15_INTD : Interrupt 63 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI16

Interrupt 64-67 Priority
address_offset : 0x440 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI16 NVICPRI16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI16_INTA NVIC_PRI16_INTB NVIC_PRI16_INTC NVIC_PRI16_INTD

NVIC_PRI16_INTA : Interrupt 64 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI16_INTB : Interrupt 65 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI16_INTC : Interrupt 66 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI16_INTD : Interrupt 67 Priority Mask
bits : 29 - 60 (32 bit)


PRI16

Interrupt 64-67 Priority
address_offset : 0x440 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI16 PRI16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI16_INTA NVIC_PRI16_INTB NVIC_PRI16_INTC NVIC_PRI16_INTD

NVIC_PRI16_INTA : Interrupt 64 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI16_INTB : Interrupt 65 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI16_INTC : Interrupt 66 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI16_INTD : Interrupt 67 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI17

Interrupt 68-71 Priority
address_offset : 0x444 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI17 NVICPRI17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI17_INTA NVIC_PRI17_INTB NVIC_PRI17_INTC NVIC_PRI17_INTD

NVIC_PRI17_INTA : Interrupt 68 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI17_INTB : Interrupt 69 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI17_INTC : Interrupt 70 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI17_INTD : Interrupt 71 Priority Mask
bits : 29 - 60 (32 bit)


PRI17

Interrupt 68-71 Priority
address_offset : 0x444 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI17 PRI17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI17_INTA NVIC_PRI17_INTB NVIC_PRI17_INTC NVIC_PRI17_INTD

NVIC_PRI17_INTA : Interrupt 68 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI17_INTB : Interrupt 69 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI17_INTC : Interrupt 70 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI17_INTD : Interrupt 71 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI18

Interrupt 72-75 Priority
address_offset : 0x448 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI18 NVICPRI18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI18_INTA NVIC_PRI18_INTB NVIC_PRI18_INTC NVIC_PRI18_INTD

NVIC_PRI18_INTA : Interrupt 72 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI18_INTB : Interrupt 73 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI18_INTC : Interrupt 74 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI18_INTD : Interrupt 75 Priority Mask
bits : 29 - 60 (32 bit)


PRI18

Interrupt 72-75 Priority
address_offset : 0x448 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI18 PRI18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI18_INTA NVIC_PRI18_INTB NVIC_PRI18_INTC NVIC_PRI18_INTD

NVIC_PRI18_INTA : Interrupt 72 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI18_INTB : Interrupt 73 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI18_INTC : Interrupt 74 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI18_INTD : Interrupt 75 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI19

Interrupt 76-79 Priority
address_offset : 0x44C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI19 NVICPRI19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI19_INTA NVIC_PRI19_INTB NVIC_PRI19_INTC NVIC_PRI19_INTD

NVIC_PRI19_INTA : Interrupt 76 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI19_INTB : Interrupt 77 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI19_INTC : Interrupt 78 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI19_INTD : Interrupt 79 Priority Mask
bits : 29 - 60 (32 bit)


PRI19

Interrupt 76-79 Priority
address_offset : 0x44C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI19 PRI19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI19_INTA NVIC_PRI19_INTB NVIC_PRI19_INTC NVIC_PRI19_INTD

NVIC_PRI19_INTA : Interrupt 76 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI19_INTB : Interrupt 77 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI19_INTC : Interrupt 78 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI19_INTD : Interrupt 79 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI20

Interrupt 80-83 Priority
address_offset : 0x450 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI20 NVICPRI20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI20_INTA NVIC_PRI20_INTB NVIC_PRI20_INTC NVIC_PRI20_INTD

NVIC_PRI20_INTA : Interrupt 80 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI20_INTB : Interrupt 81 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI20_INTC : Interrupt 82 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI20_INTD : Interrupt 83 Priority Mask
bits : 29 - 60 (32 bit)


PRI20

Interrupt 80-83 Priority
address_offset : 0x450 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI20 PRI20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI20_INTA NVIC_PRI20_INTB NVIC_PRI20_INTC NVIC_PRI20_INTD

NVIC_PRI20_INTA : Interrupt 80 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI20_INTB : Interrupt 81 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI20_INTC : Interrupt 82 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI20_INTD : Interrupt 83 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI21

Interrupt 84-87 Priority
address_offset : 0x454 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI21 NVICPRI21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI21_INTA NVIC_PRI21_INTB NVIC_PRI21_INTC NVIC_PRI21_INTD

NVIC_PRI21_INTA : Interrupt 84 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI21_INTB : Interrupt 85 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI21_INTC : Interrupt 86 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI21_INTD : Interrupt 87 Priority Mask
bits : 29 - 60 (32 bit)


PRI21

Interrupt 84-87 Priority
address_offset : 0x454 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI21 PRI21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI21_INTA NVIC_PRI21_INTB NVIC_PRI21_INTC NVIC_PRI21_INTD

NVIC_PRI21_INTA : Interrupt 84 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI21_INTB : Interrupt 85 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI21_INTC : Interrupt 86 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI21_INTD : Interrupt 87 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI22

Interrupt 88-91 Priority
address_offset : 0x458 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI22 NVICPRI22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI22_INTA NVIC_PRI22_INTB NVIC_PRI22_INTC NVIC_PRI22_INTD

NVIC_PRI22_INTA : Interrupt 88 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI22_INTB : Interrupt 89 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI22_INTC : Interrupt 90 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI22_INTD : Interrupt 91 Priority Mask
bits : 29 - 60 (32 bit)


PRI22

Interrupt 88-91 Priority
address_offset : 0x458 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI22 PRI22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI22_INTA NVIC_PRI22_INTB NVIC_PRI22_INTC NVIC_PRI22_INTD

NVIC_PRI22_INTA : Interrupt 88 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI22_INTB : Interrupt 89 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI22_INTC : Interrupt 90 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI22_INTD : Interrupt 91 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI23

Interrupt 92-95 Priority
address_offset : 0x45C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI23 NVICPRI23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI23_INTA NVIC_PRI23_INTB NVIC_PRI23_INTC NVIC_PRI23_INTD

NVIC_PRI23_INTA : Interrupt 92 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI23_INTB : Interrupt 93 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI23_INTC : Interrupt 94 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI23_INTD : Interrupt 95 Priority Mask
bits : 29 - 60 (32 bit)


PRI23

Interrupt 92-95 Priority
address_offset : 0x45C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI23 PRI23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI23_INTA NVIC_PRI23_INTB NVIC_PRI23_INTC NVIC_PRI23_INTD

NVIC_PRI23_INTA : Interrupt 92 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI23_INTB : Interrupt 93 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI23_INTC : Interrupt 94 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI23_INTD : Interrupt 95 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI24

Interrupt 96-99 Priority
address_offset : 0x460 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI24 NVICPRI24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI24_INTA NVIC_PRI24_INTB NVIC_PRI24_INTC NVIC_PRI24_INTD

NVIC_PRI24_INTA : Interrupt 96 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI24_INTB : Interrupt 97 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI24_INTC : Interrupt 98 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI24_INTD : Interrupt 99 Priority Mask
bits : 29 - 60 (32 bit)


PRI24

Interrupt 96-99 Priority
address_offset : 0x460 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI24 PRI24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI24_INTA NVIC_PRI24_INTB NVIC_PRI24_INTC NVIC_PRI24_INTD

NVIC_PRI24_INTA : Interrupt 96 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI24_INTB : Interrupt 97 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI24_INTC : Interrupt 98 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI24_INTD : Interrupt 99 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI25

Interrupt 100-103 Priority
address_offset : 0x464 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI25 NVICPRI25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI25_INTA NVIC_PRI25_INTB NVIC_PRI25_INTC NVIC_PRI25_INTD

NVIC_PRI25_INTA : Interrupt 100 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI25_INTB : Interrupt 101 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI25_INTC : Interrupt 102 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI25_INTD : Interrupt 103 Priority Mask
bits : 29 - 60 (32 bit)


PRI25

Interrupt 100-103 Priority
address_offset : 0x464 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI25 PRI25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI25_INTA NVIC_PRI25_INTB NVIC_PRI25_INTC NVIC_PRI25_INTD

NVIC_PRI25_INTA : Interrupt 100 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI25_INTB : Interrupt 101 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI25_INTC : Interrupt 102 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI25_INTD : Interrupt 103 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI26

Interrupt 104-107 Priority
address_offset : 0x468 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI26 NVICPRI26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI26_INTA NVIC_PRI26_INTB NVIC_PRI26_INTC NVIC_PRI26_INTD

NVIC_PRI26_INTA : Interrupt 104 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI26_INTB : Interrupt 105 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI26_INTC : Interrupt 106 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI26_INTD : Interrupt 107 Priority Mask
bits : 29 - 60 (32 bit)


PRI26

Interrupt 104-107 Priority
address_offset : 0x468 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI26 PRI26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI26_INTA NVIC_PRI26_INTB NVIC_PRI26_INTC NVIC_PRI26_INTD

NVIC_PRI26_INTA : Interrupt 104 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI26_INTB : Interrupt 105 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI26_INTC : Interrupt 106 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI26_INTD : Interrupt 107 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI27

Interrupt 108-111 Priority
address_offset : 0x46C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI27 NVICPRI27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI27_INTA NVIC_PRI27_INTB NVIC_PRI27_INTC NVIC_PRI27_INTD

NVIC_PRI27_INTA : Interrupt 108 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI27_INTB : Interrupt 109 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI27_INTC : Interrupt 110 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI27_INTD : Interrupt 111 Priority Mask
bits : 29 - 60 (32 bit)


PRI27

Interrupt 108-111 Priority
address_offset : 0x46C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI27 PRI27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI27_INTA NVIC_PRI27_INTB NVIC_PRI27_INTC NVIC_PRI27_INTD

NVIC_PRI27_INTA : Interrupt 108 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI27_INTB : Interrupt 109 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI27_INTC : Interrupt 110 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI27_INTD : Interrupt 111 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI28

Interrupt 112-115 Priority
address_offset : 0x470 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI28 NVICPRI28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI28_INTA NVIC_PRI28_INTB NVIC_PRI28_INTC NVIC_PRI28_INTD

NVIC_PRI28_INTA : Interrupt 112 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI28_INTB : Interrupt 113 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI28_INTC : Interrupt 114 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI28_INTD : Interrupt 115 Priority Mask
bits : 29 - 60 (32 bit)


PRI28

Interrupt 112-115 Priority
address_offset : 0x470 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI28 PRI28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI28_INTA NVIC_PRI28_INTB NVIC_PRI28_INTC NVIC_PRI28_INTD

NVIC_PRI28_INTA : Interrupt 112 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI28_INTB : Interrupt 113 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI28_INTC : Interrupt 114 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI28_INTD : Interrupt 115 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI29

Interrupt 116-119 Priority
address_offset : 0x474 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI29 NVICPRI29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI29_INTA NVIC_PRI29_INTB NVIC_PRI29_INTC NVIC_PRI29_INTD

NVIC_PRI29_INTA : Interrupt 116 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI29_INTB : Interrupt 117 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI29_INTC : Interrupt 118 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI29_INTD : Interrupt 119 Priority Mask
bits : 29 - 60 (32 bit)


PRI29

Interrupt 116-119 Priority
address_offset : 0x474 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI29 PRI29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI29_INTA NVIC_PRI29_INTB NVIC_PRI29_INTC NVIC_PRI29_INTD

NVIC_PRI29_INTA : Interrupt 116 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI29_INTB : Interrupt 117 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI29_INTC : Interrupt 118 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI29_INTD : Interrupt 119 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI30

Interrupt 120-123 Priority
address_offset : 0x478 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI30 NVICPRI30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI30_INTA NVIC_PRI30_INTB NVIC_PRI30_INTC NVIC_PRI30_INTD

NVIC_PRI30_INTA : Interrupt 120 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI30_INTB : Interrupt 121 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI30_INTC : Interrupt 122 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI30_INTD : Interrupt 123 Priority Mask
bits : 29 - 60 (32 bit)


PRI30

Interrupt 120-123 Priority
address_offset : 0x478 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI30 PRI30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI30_INTA NVIC_PRI30_INTB NVIC_PRI30_INTC NVIC_PRI30_INTD

NVIC_PRI30_INTA : Interrupt 120 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI30_INTB : Interrupt 121 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI30_INTC : Interrupt 122 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI30_INTD : Interrupt 123 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI31

Interrupt 124-127 Priority
address_offset : 0x47C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI31 NVICPRI31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI31_INTA NVIC_PRI31_INTB NVIC_PRI31_INTC NVIC_PRI31_INTD

NVIC_PRI31_INTA : Interrupt 124 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI31_INTB : Interrupt 125 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI31_INTC : Interrupt 126 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI31_INTD : Interrupt 127 Priority Mask
bits : 29 - 60 (32 bit)


PRI31

Interrupt 124-127 Priority
address_offset : 0x47C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI31 PRI31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI31_INTA NVIC_PRI31_INTB NVIC_PRI31_INTC NVIC_PRI31_INTD

NVIC_PRI31_INTA : Interrupt 124 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI31_INTB : Interrupt 125 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI31_INTC : Interrupt 126 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI31_INTD : Interrupt 127 Priority Mask
bits : 29 - 60 (32 bit)


NVICPRI32

Interrupt 128-131 Priority
address_offset : 0x480 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICPRI32 NVICPRI32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI32_INTA NVIC_PRI32_INTB NVIC_PRI32_INTC NVIC_PRI32_INTD

NVIC_PRI32_INTA : Interrupt 128 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI32_INTB : Interrupt 129 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI32_INTC : Interrupt 130 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI32_INTD : Interrupt 131 Priority Mask
bits : 29 - 60 (32 bit)


PRI32

Interrupt 128-131 Priority
address_offset : 0x480 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRI32 PRI32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_PRI32_INTA NVIC_PRI32_INTB NVIC_PRI32_INTC NVIC_PRI32_INTD

NVIC_PRI32_INTA : Interrupt 128 Priority Mask
bits : 5 - 12 (8 bit)

NVIC_PRI32_INTB : Interrupt 129 Priority Mask
bits : 13 - 28 (16 bit)

NVIC_PRI32_INTC : Interrupt 130 Priority Mask
bits : 21 - 44 (24 bit)

NVIC_PRI32_INTD : Interrupt 131 Priority Mask
bits : 29 - 60 (32 bit)


NVICACTLR

Auxiliary Control
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICACTLR NVICACTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_ACTLR_DISMCYC NVIC_ACTLR_DISWBUF NVIC_ACTLR_DISFOLD NVIC_ACTLR_DISFPCA NVIC_ACTLR_DISOOFP

NVIC_ACTLR_DISMCYC : Disable Interrupts of Multiple Cycle Instructions
bits : 0 - 0 (1 bit)

NVIC_ACTLR_DISWBUF : Disable Write Buffer
bits : 1 - 2 (2 bit)

NVIC_ACTLR_DISFOLD : Disable IT Folding
bits : 2 - 4 (3 bit)

NVIC_ACTLR_DISFPCA : Disable CONTROL
bits : 8 - 16 (9 bit)

NVIC_ACTLR_DISOOFP : Disable Out-Of-Order Floating Point
bits : 9 - 18 (10 bit)


ACTLR

Auxiliary Control
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACTLR ACTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_ACTLR_DISMCYC NVIC_ACTLR_DISWBUF NVIC_ACTLR_DISFOLD NVIC_ACTLR_DISFPCA NVIC_ACTLR_DISOOFP

NVIC_ACTLR_DISMCYC : Disable Interrupts of Multiple Cycle Instructions
bits : 0 - 0 (1 bit)

NVIC_ACTLR_DISWBUF : Disable Write Buffer
bits : 1 - 2 (2 bit)

NVIC_ACTLR_DISFOLD : Disable IT Folding
bits : 2 - 4 (3 bit)

NVIC_ACTLR_DISFPCA : Disable CONTROL
bits : 8 - 16 (9 bit)

NVIC_ACTLR_DISOOFP : Disable Out-Of-Order Floating Point
bits : 9 - 18 (10 bit)


NVICCPUID

CPU ID Base
address_offset : 0xD00 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICCPUID NVICCPUID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_CPUID_REV NVIC_CPUID_PARTNO NVIC_CPUID_CON NVIC_CPUID_VAR NVIC_CPUID_IMP

NVIC_CPUID_REV : Revision Number
bits : 0 - 3 (4 bit)

NVIC_CPUID_PARTNO : Part Number
bits : 4 - 19 (16 bit)

Enumeration:

0xc24 : NVIC_CPUID_PARTNO_CM4

Cortex-M4 processor

End of enumeration elements list.

NVIC_CPUID_CON : Constant
bits : 16 - 35 (20 bit)

NVIC_CPUID_VAR : Variant Number
bits : 20 - 43 (24 bit)

NVIC_CPUID_IMP : Implementer Code
bits : 24 - 55 (32 bit)

Enumeration:

0x41 : NVIC_CPUID_IMP_ARM

ARM

End of enumeration elements list.


CPUID

CPU ID Base
address_offset : 0xD00 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPUID CPUID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_CPUID_REV NVIC_CPUID_PARTNO NVIC_CPUID_CON NVIC_CPUID_VAR NVIC_CPUID_IMP

NVIC_CPUID_REV : Revision Number
bits : 0 - 3 (4 bit)

NVIC_CPUID_PARTNO : Part Number
bits : 4 - 19 (16 bit)

Enumeration:

0xc24 : NVIC_CPUID_PARTNO_CM4

Cortex-M4 processor

End of enumeration elements list.

NVIC_CPUID_CON : Constant
bits : 16 - 35 (20 bit)

NVIC_CPUID_VAR : Variant Number
bits : 20 - 43 (24 bit)

NVIC_CPUID_IMP : Implementer Code
bits : 24 - 55 (32 bit)

Enumeration:

0x41 : NVIC_CPUID_IMP_ARM

ARM

End of enumeration elements list.


NVICINT_CTRL

Interrupt Control and State
address_offset : 0xD04 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICINT_CTRL NVICINT_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_INT_CTRL_VEC_ACT NVIC_INT_CTRL_RET_BASE NVIC_INT_CTRL_VEC_PEN NVIC_INT_CTRL_ISR_PEND NVIC_INT_CTRL_ISR_PRE NVIC_INT_CTRL_PENDSTCLR NVIC_INT_CTRL_PENDSTSET NVIC_INT_CTRL_UNPEND_SV NVIC_INT_CTRL_PEND_SV NVIC_INT_CTRL_NMI_SET

NVIC_INT_CTRL_VEC_ACT : Interrupt Pending Vector Number
bits : 0 - 7 (8 bit)

NVIC_INT_CTRL_RET_BASE : Return to Base
bits : 11 - 22 (12 bit)

NVIC_INT_CTRL_VEC_PEN : Interrupt Pending Vector Number
bits : 12 - 31 (20 bit)

Enumeration:

0x2 : NVIC_INT_CTRL_VEC_PEN_NMI

NMI

0x3 : NVIC_INT_CTRL_VEC_PEN_HARD

Hard fault

0x4 : NVIC_INT_CTRL_VEC_PEN_MEM

Memory management fault

0x5 : NVIC_INT_CTRL_VEC_PEN_BUS

Bus fault

0x6 : NVIC_INT_CTRL_VEC_PEN_USG

Usage fault

0xb : NVIC_INT_CTRL_VEC_PEN_SVC

SVCall

0xe : NVIC_INT_CTRL_VEC_PEN_PNDSV

PendSV

0xf : NVIC_INT_CTRL_VEC_PEN_TICK

SysTick

End of enumeration elements list.

NVIC_INT_CTRL_ISR_PEND : Interrupt Pending
bits : 22 - 44 (23 bit)

NVIC_INT_CTRL_ISR_PRE : Debug Interrupt Handling
bits : 23 - 46 (24 bit)

NVIC_INT_CTRL_PENDSTCLR : SysTick Clear Pending
bits : 25 - 50 (26 bit)

NVIC_INT_CTRL_PENDSTSET : SysTick Set Pending
bits : 26 - 52 (27 bit)

NVIC_INT_CTRL_UNPEND_SV : PendSV Clear Pending
bits : 27 - 54 (28 bit)

NVIC_INT_CTRL_PEND_SV : PendSV Set Pending
bits : 28 - 56 (29 bit)

NVIC_INT_CTRL_NMI_SET : NMI Set Pending
bits : 31 - 62 (32 bit)


INT_CTRL

Interrupt Control and State
address_offset : 0xD04 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_CTRL INT_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_INT_CTRL_VEC_ACT NVIC_INT_CTRL_RET_BASE NVIC_INT_CTRL_VEC_PEN NVIC_INT_CTRL_ISR_PEND NVIC_INT_CTRL_ISR_PRE NVIC_INT_CTRL_PENDSTCLR NVIC_INT_CTRL_PENDSTSET NVIC_INT_CTRL_UNPEND_SV NVIC_INT_CTRL_PEND_SV NVIC_INT_CTRL_NMI_SET

NVIC_INT_CTRL_VEC_ACT : Interrupt Pending Vector Number
bits : 0 - 7 (8 bit)

NVIC_INT_CTRL_RET_BASE : Return to Base
bits : 11 - 22 (12 bit)

NVIC_INT_CTRL_VEC_PEN : Interrupt Pending Vector Number
bits : 12 - 31 (20 bit)

Enumeration:

0x2 : NVIC_INT_CTRL_VEC_PEN_NMI

NMI

0x3 : NVIC_INT_CTRL_VEC_PEN_HARD

Hard fault

0x4 : NVIC_INT_CTRL_VEC_PEN_MEM

Memory management fault

0x5 : NVIC_INT_CTRL_VEC_PEN_BUS

Bus fault

0x6 : NVIC_INT_CTRL_VEC_PEN_USG

Usage fault

0xb : NVIC_INT_CTRL_VEC_PEN_SVC

SVCall

0xe : NVIC_INT_CTRL_VEC_PEN_PNDSV

PendSV

0xf : NVIC_INT_CTRL_VEC_PEN_TICK

SysTick

End of enumeration elements list.

NVIC_INT_CTRL_ISR_PEND : Interrupt Pending
bits : 22 - 44 (23 bit)

NVIC_INT_CTRL_ISR_PRE : Debug Interrupt Handling
bits : 23 - 46 (24 bit)

NVIC_INT_CTRL_PENDSTCLR : SysTick Clear Pending
bits : 25 - 50 (26 bit)

NVIC_INT_CTRL_PENDSTSET : SysTick Set Pending
bits : 26 - 52 (27 bit)

NVIC_INT_CTRL_UNPEND_SV : PendSV Clear Pending
bits : 27 - 54 (28 bit)

NVIC_INT_CTRL_PEND_SV : PendSV Set Pending
bits : 28 - 56 (29 bit)

NVIC_INT_CTRL_NMI_SET : NMI Set Pending
bits : 31 - 62 (32 bit)


NVICVTABLE

Vector Table Offset
address_offset : 0xD08 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICVTABLE NVICVTABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_VTABLE_OFFSET NVIC_VTABLE_BASE

NVIC_VTABLE_OFFSET : Vector Table Offset
bits : 10 - 38 (29 bit)

NVIC_VTABLE_BASE : Vector Table Base
bits : 29 - 58 (30 bit)


VTABLE

Vector Table Offset
address_offset : 0xD08 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VTABLE VTABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_VTABLE_OFFSET NVIC_VTABLE_BASE

NVIC_VTABLE_OFFSET : Vector Table Offset
bits : 10 - 38 (29 bit)

NVIC_VTABLE_BASE : Vector Table Base
bits : 29 - 58 (30 bit)


NVICAPINT

Application Interrupt and Reset Control
address_offset : 0xD0C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICAPINT NVICAPINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_APINT_VECT_RESET NVIC_APINT_VECT_CLR_ACT NVIC_APINT_SYSRESETREQ NVIC_APINT_PRIGROUP NVIC_APINT_ENDIANESS NVIC_APINT_VECTKEY

NVIC_APINT_VECT_RESET : System Reset
bits : 0 - 0 (1 bit)

NVIC_APINT_VECT_CLR_ACT : Clear Active NMI / Fault
bits : 1 - 2 (2 bit)

NVIC_APINT_SYSRESETREQ : System Reset Request
bits : 2 - 4 (3 bit)

NVIC_APINT_PRIGROUP : Interrupt Priority Grouping
bits : 8 - 18 (11 bit)

Enumeration:

0x0 : NVIC_APINT_PRIGROUP_7_1

Priority group 7.1 split

0x1 : NVIC_APINT_PRIGROUP_6_2

Priority group 6.2 split

0x2 : NVIC_APINT_PRIGROUP_5_3

Priority group 5.3 split

0x3 : NVIC_APINT_PRIGROUP_4_4

Priority group 4.4 split

0x4 : NVIC_APINT_PRIGROUP_3_5

Priority group 3.5 split

0x5 : NVIC_APINT_PRIGROUP_2_6

Priority group 2.6 split

0x6 : NVIC_APINT_PRIGROUP_1_7

Priority group 1.7 split

0x7 : NVIC_APINT_PRIGROUP_0_8

Priority group 0.8 split

End of enumeration elements list.

NVIC_APINT_ENDIANESS : Data Endianess
bits : 15 - 30 (16 bit)

NVIC_APINT_VECTKEY : Register Key
bits : 16 - 47 (32 bit)

Enumeration:

0x5fa : NVIC_APINT_VECTKEY

Vector key

End of enumeration elements list.


APINT

Application Interrupt and Reset Control
address_offset : 0xD0C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APINT APINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_APINT_VECT_RESET NVIC_APINT_VECT_CLR_ACT NVIC_APINT_SYSRESETREQ NVIC_APINT_PRIGROUP NVIC_APINT_ENDIANESS NVIC_APINT_VECTKEY

NVIC_APINT_VECT_RESET : System Reset
bits : 0 - 0 (1 bit)

NVIC_APINT_VECT_CLR_ACT : Clear Active NMI / Fault
bits : 1 - 2 (2 bit)

NVIC_APINT_SYSRESETREQ : System Reset Request
bits : 2 - 4 (3 bit)

NVIC_APINT_PRIGROUP : Interrupt Priority Grouping
bits : 8 - 18 (11 bit)

Enumeration:

0x0 : NVIC_APINT_PRIGROUP_7_1

Priority group 7.1 split

0x1 : NVIC_APINT_PRIGROUP_6_2

Priority group 6.2 split

0x2 : NVIC_APINT_PRIGROUP_5_3

Priority group 5.3 split

0x3 : NVIC_APINT_PRIGROUP_4_4

Priority group 4.4 split

0x4 : NVIC_APINT_PRIGROUP_3_5

Priority group 3.5 split

0x5 : NVIC_APINT_PRIGROUP_2_6

Priority group 2.6 split

0x6 : NVIC_APINT_PRIGROUP_1_7

Priority group 1.7 split

0x7 : NVIC_APINT_PRIGROUP_0_8

Priority group 0.8 split

End of enumeration elements list.

NVIC_APINT_ENDIANESS : Data Endianess
bits : 15 - 30 (16 bit)

NVIC_APINT_VECTKEY : Register Key
bits : 16 - 47 (32 bit)

Enumeration:

0x5fa : NVIC_APINT_VECTKEY

Vector key

End of enumeration elements list.


NVICSYS_CTRL

System Control
address_offset : 0xD10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICSYS_CTRL NVICSYS_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_SYS_CTRL_SLEEPEXIT NVIC_SYS_CTRL_SLEEPDEEP NVIC_SYS_CTRL_SEVONPEND

NVIC_SYS_CTRL_SLEEPEXIT : Sleep on ISR Exit
bits : 1 - 2 (2 bit)

NVIC_SYS_CTRL_SLEEPDEEP : Deep Sleep Enable
bits : 2 - 4 (3 bit)

NVIC_SYS_CTRL_SEVONPEND : Wake Up on Pending
bits : 4 - 8 (5 bit)


SYS_CTRL

System Control
address_offset : 0xD10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CTRL SYS_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_SYS_CTRL_SLEEPEXIT NVIC_SYS_CTRL_SLEEPDEEP NVIC_SYS_CTRL_SEVONPEND

NVIC_SYS_CTRL_SLEEPEXIT : Sleep on ISR Exit
bits : 1 - 2 (2 bit)

NVIC_SYS_CTRL_SLEEPDEEP : Deep Sleep Enable
bits : 2 - 4 (3 bit)

NVIC_SYS_CTRL_SEVONPEND : Wake Up on Pending
bits : 4 - 8 (5 bit)


NVICCFG_CTRL

Configuration and Control
address_offset : 0xD14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICCFG_CTRL NVICCFG_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_CFG_CTRL_BASE_THR NVIC_CFG_CTRL_MAIN_PEND NVIC_CFG_CTRL_UNALIGNED NVIC_CFG_CTRL_DIV0 NVIC_CFG_CTRL_BFHFNMIGN NVIC_CFG_CTRL_STKALIGN

NVIC_CFG_CTRL_BASE_THR : Thread State Control
bits : 0 - 0 (1 bit)

NVIC_CFG_CTRL_MAIN_PEND : Allow Main Interrupt Trigger
bits : 1 - 2 (2 bit)

NVIC_CFG_CTRL_UNALIGNED : Trap on Unaligned Access
bits : 3 - 6 (4 bit)

NVIC_CFG_CTRL_DIV0 : Trap on Divide by 0
bits : 4 - 8 (5 bit)

NVIC_CFG_CTRL_BFHFNMIGN : Ignore Bus Fault in NMI and Fault
bits : 8 - 16 (9 bit)

NVIC_CFG_CTRL_STKALIGN : Stack Alignment on Exception Entry
bits : 9 - 18 (10 bit)


CFG_CTRL

Configuration and Control
address_offset : 0xD14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG_CTRL CFG_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_CFG_CTRL_BASE_THR NVIC_CFG_CTRL_MAIN_PEND NVIC_CFG_CTRL_UNALIGNED NVIC_CFG_CTRL_DIV0 NVIC_CFG_CTRL_BFHFNMIGN NVIC_CFG_CTRL_STKALIGN

NVIC_CFG_CTRL_BASE_THR : Thread State Control
bits : 0 - 0 (1 bit)

NVIC_CFG_CTRL_MAIN_PEND : Allow Main Interrupt Trigger
bits : 1 - 2 (2 bit)

NVIC_CFG_CTRL_UNALIGNED : Trap on Unaligned Access
bits : 3 - 6 (4 bit)

NVIC_CFG_CTRL_DIV0 : Trap on Divide by 0
bits : 4 - 8 (5 bit)

NVIC_CFG_CTRL_BFHFNMIGN : Ignore Bus Fault in NMI and Fault
bits : 8 - 16 (9 bit)

NVIC_CFG_CTRL_STKALIGN : Stack Alignment on Exception Entry
bits : 9 - 18 (10 bit)


NVICSYS_PRI1

System Handler Priority 1
address_offset : 0xD18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICSYS_PRI1 NVICSYS_PRI1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_SYS_PRI1_MEM NVIC_SYS_PRI1_BUS NVIC_SYS_PRI1_USAGE

NVIC_SYS_PRI1_MEM : Memory Management Fault Priority
bits : 5 - 12 (8 bit)

NVIC_SYS_PRI1_BUS : Bus Fault Priority
bits : 13 - 28 (16 bit)

NVIC_SYS_PRI1_USAGE : Usage Fault Priority
bits : 21 - 44 (24 bit)


SYS_PRI1

System Handler Priority 1
address_offset : 0xD18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_PRI1 SYS_PRI1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_SYS_PRI1_MEM NVIC_SYS_PRI1_BUS NVIC_SYS_PRI1_USAGE

NVIC_SYS_PRI1_MEM : Memory Management Fault Priority
bits : 5 - 12 (8 bit)

NVIC_SYS_PRI1_BUS : Bus Fault Priority
bits : 13 - 28 (16 bit)

NVIC_SYS_PRI1_USAGE : Usage Fault Priority
bits : 21 - 44 (24 bit)


NVICSYS_PRI2

System Handler Priority 2
address_offset : 0xD1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICSYS_PRI2 NVICSYS_PRI2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_SYS_PRI2_SVC

NVIC_SYS_PRI2_SVC : SVCall Priority
bits : 29 - 60 (32 bit)


SYS_PRI2

System Handler Priority 2
address_offset : 0xD1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_PRI2 SYS_PRI2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_SYS_PRI2_SVC

NVIC_SYS_PRI2_SVC : SVCall Priority
bits : 29 - 60 (32 bit)


NVICSYS_PRI3

System Handler Priority 3
address_offset : 0xD20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICSYS_PRI3 NVICSYS_PRI3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_SYS_PRI3_DEBUG NVIC_SYS_PRI3_PENDSV NVIC_SYS_PRI3_TICK

NVIC_SYS_PRI3_DEBUG : Debug Priority
bits : 5 - 12 (8 bit)

NVIC_SYS_PRI3_PENDSV : PendSV Priority
bits : 21 - 44 (24 bit)

NVIC_SYS_PRI3_TICK : SysTick Exception Priority
bits : 29 - 60 (32 bit)


SYS_PRI3

System Handler Priority 3
address_offset : 0xD20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_PRI3 SYS_PRI3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_SYS_PRI3_DEBUG NVIC_SYS_PRI3_PENDSV NVIC_SYS_PRI3_TICK

NVIC_SYS_PRI3_DEBUG : Debug Priority
bits : 5 - 12 (8 bit)

NVIC_SYS_PRI3_PENDSV : PendSV Priority
bits : 21 - 44 (24 bit)

NVIC_SYS_PRI3_TICK : SysTick Exception Priority
bits : 29 - 60 (32 bit)


NVICSYS_HND_CTRL

System Handler Control and State
address_offset : 0xD24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICSYS_HND_CTRL NVICSYS_HND_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_SYS_HND_CTRL_MEMA NVIC_SYS_HND_CTRL_BUSA NVIC_SYS_HND_CTRL_USGA NVIC_SYS_HND_CTRL_SVCA NVIC_SYS_HND_CTRL_MON NVIC_SYS_HND_CTRL_PNDSV NVIC_SYS_HND_CTRL_TICK NVIC_SYS_HND_CTRL_USAGEP NVIC_SYS_HND_CTRL_MEMP NVIC_SYS_HND_CTRL_BUSP NVIC_SYS_HND_CTRL_SVC NVIC_SYS_HND_CTRL_MEM NVIC_SYS_HND_CTRL_BUS NVIC_SYS_HND_CTRL_USAGE

NVIC_SYS_HND_CTRL_MEMA : Memory Management Fault Active
bits : 0 - 0 (1 bit)

NVIC_SYS_HND_CTRL_BUSA : Bus Fault Active
bits : 1 - 2 (2 bit)

NVIC_SYS_HND_CTRL_USGA : Usage Fault Active
bits : 3 - 6 (4 bit)

NVIC_SYS_HND_CTRL_SVCA : SVC Call Active
bits : 7 - 14 (8 bit)

NVIC_SYS_HND_CTRL_MON : Debug Monitor Active
bits : 8 - 16 (9 bit)

NVIC_SYS_HND_CTRL_PNDSV : PendSV Exception Active
bits : 10 - 20 (11 bit)

NVIC_SYS_HND_CTRL_TICK : SysTick Exception Active
bits : 11 - 22 (12 bit)

NVIC_SYS_HND_CTRL_USAGEP : Usage Fault Pending
bits : 12 - 24 (13 bit)

NVIC_SYS_HND_CTRL_MEMP : Memory Management Fault Pending
bits : 13 - 26 (14 bit)

NVIC_SYS_HND_CTRL_BUSP : Bus Fault Pending
bits : 14 - 28 (15 bit)

NVIC_SYS_HND_CTRL_SVC : SVC Call Pending
bits : 15 - 30 (16 bit)

NVIC_SYS_HND_CTRL_MEM : Memory Management Fault Enable
bits : 16 - 32 (17 bit)

NVIC_SYS_HND_CTRL_BUS : Bus Fault Enable
bits : 17 - 34 (18 bit)

NVIC_SYS_HND_CTRL_USAGE : Usage Fault Enable
bits : 18 - 36 (19 bit)


SYS_HND_CTRL

System Handler Control and State
address_offset : 0xD24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_HND_CTRL SYS_HND_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_SYS_HND_CTRL_MEMA NVIC_SYS_HND_CTRL_BUSA NVIC_SYS_HND_CTRL_USGA NVIC_SYS_HND_CTRL_SVCA NVIC_SYS_HND_CTRL_MON NVIC_SYS_HND_CTRL_PNDSV NVIC_SYS_HND_CTRL_TICK NVIC_SYS_HND_CTRL_USAGEP NVIC_SYS_HND_CTRL_MEMP NVIC_SYS_HND_CTRL_BUSP NVIC_SYS_HND_CTRL_SVC NVIC_SYS_HND_CTRL_MEM NVIC_SYS_HND_CTRL_BUS NVIC_SYS_HND_CTRL_USAGE

NVIC_SYS_HND_CTRL_MEMA : Memory Management Fault Active
bits : 0 - 0 (1 bit)

NVIC_SYS_HND_CTRL_BUSA : Bus Fault Active
bits : 1 - 2 (2 bit)

NVIC_SYS_HND_CTRL_USGA : Usage Fault Active
bits : 3 - 6 (4 bit)

NVIC_SYS_HND_CTRL_SVCA : SVC Call Active
bits : 7 - 14 (8 bit)

NVIC_SYS_HND_CTRL_MON : Debug Monitor Active
bits : 8 - 16 (9 bit)

NVIC_SYS_HND_CTRL_PNDSV : PendSV Exception Active
bits : 10 - 20 (11 bit)

NVIC_SYS_HND_CTRL_TICK : SysTick Exception Active
bits : 11 - 22 (12 bit)

NVIC_SYS_HND_CTRL_USAGEP : Usage Fault Pending
bits : 12 - 24 (13 bit)

NVIC_SYS_HND_CTRL_MEMP : Memory Management Fault Pending
bits : 13 - 26 (14 bit)

NVIC_SYS_HND_CTRL_BUSP : Bus Fault Pending
bits : 14 - 28 (15 bit)

NVIC_SYS_HND_CTRL_SVC : SVC Call Pending
bits : 15 - 30 (16 bit)

NVIC_SYS_HND_CTRL_MEM : Memory Management Fault Enable
bits : 16 - 32 (17 bit)

NVIC_SYS_HND_CTRL_BUS : Bus Fault Enable
bits : 17 - 34 (18 bit)

NVIC_SYS_HND_CTRL_USAGE : Usage Fault Enable
bits : 18 - 36 (19 bit)


NVICFAULT_STAT

Configurable Fault Status
address_offset : 0xD28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICFAULT_STAT NVICFAULT_STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_FAULT_STAT_IERR NVIC_FAULT_STAT_DERR NVIC_FAULT_STAT_MUSTKE NVIC_FAULT_STAT_MSTKE NVIC_FAULT_STAT_MLSPERR NVIC_FAULT_STAT_MMARV NVIC_FAULT_STAT_IBUS NVIC_FAULT_STAT_PRECISE NVIC_FAULT_STAT_IMPRE NVIC_FAULT_STAT_BUSTKE NVIC_FAULT_STAT_BSTKE NVIC_FAULT_STAT_BLSPERR NVIC_FAULT_STAT_BFARV NVIC_FAULT_STAT_UNDEF NVIC_FAULT_STAT_INVSTAT NVIC_FAULT_STAT_INVPC NVIC_FAULT_STAT_NOCP NVIC_FAULT_STAT_UNALIGN NVIC_FAULT_STAT_DIV0

NVIC_FAULT_STAT_IERR : Instruction Access Violation
bits : 0 - 0 (1 bit)

NVIC_FAULT_STAT_DERR : Data Access Violation
bits : 1 - 2 (2 bit)

NVIC_FAULT_STAT_MUSTKE : Unstack Access Violation
bits : 3 - 6 (4 bit)

NVIC_FAULT_STAT_MSTKE : Stack Access Violation
bits : 4 - 8 (5 bit)

NVIC_FAULT_STAT_MLSPERR : Memory Management Fault on Floating-Point Lazy State Preservation
bits : 5 - 10 (6 bit)

NVIC_FAULT_STAT_MMARV : Memory Management Fault Address Register Valid
bits : 7 - 14 (8 bit)

NVIC_FAULT_STAT_IBUS : Instruction Bus Error
bits : 8 - 16 (9 bit)

NVIC_FAULT_STAT_PRECISE : Precise Data Bus Error
bits : 9 - 18 (10 bit)

NVIC_FAULT_STAT_IMPRE : Imprecise Data Bus Error
bits : 10 - 20 (11 bit)

NVIC_FAULT_STAT_BUSTKE : Unstack Bus Fault
bits : 11 - 22 (12 bit)

NVIC_FAULT_STAT_BSTKE : Stack Bus Fault
bits : 12 - 24 (13 bit)

NVIC_FAULT_STAT_BLSPERR : Bus Fault on Floating-Point Lazy State Preservation
bits : 13 - 26 (14 bit)

NVIC_FAULT_STAT_BFARV : Bus Fault Address Register Valid
bits : 15 - 30 (16 bit)

NVIC_FAULT_STAT_UNDEF : Undefined Instruction Usage Fault
bits : 16 - 32 (17 bit)

NVIC_FAULT_STAT_INVSTAT : Invalid State Usage Fault
bits : 17 - 34 (18 bit)

NVIC_FAULT_STAT_INVPC : Invalid PC Load Usage Fault
bits : 18 - 36 (19 bit)

NVIC_FAULT_STAT_NOCP : No Coprocessor Usage Fault
bits : 19 - 38 (20 bit)

NVIC_FAULT_STAT_UNALIGN : Unaligned Access Usage Fault
bits : 24 - 48 (25 bit)

NVIC_FAULT_STAT_DIV0 : Divide-by-Zero Usage Fault
bits : 25 - 50 (26 bit)


FAULT_STAT

Configurable Fault Status
address_offset : 0xD28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FAULT_STAT FAULT_STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_FAULT_STAT_IERR NVIC_FAULT_STAT_DERR NVIC_FAULT_STAT_MUSTKE NVIC_FAULT_STAT_MSTKE NVIC_FAULT_STAT_MLSPERR NVIC_FAULT_STAT_MMARV NVIC_FAULT_STAT_IBUS NVIC_FAULT_STAT_PRECISE NVIC_FAULT_STAT_IMPRE NVIC_FAULT_STAT_BUSTKE NVIC_FAULT_STAT_BSTKE NVIC_FAULT_STAT_BLSPERR NVIC_FAULT_STAT_BFARV NVIC_FAULT_STAT_UNDEF NVIC_FAULT_STAT_INVSTAT NVIC_FAULT_STAT_INVPC NVIC_FAULT_STAT_NOCP NVIC_FAULT_STAT_UNALIGN NVIC_FAULT_STAT_DIV0

NVIC_FAULT_STAT_IERR : Instruction Access Violation
bits : 0 - 0 (1 bit)

NVIC_FAULT_STAT_DERR : Data Access Violation
bits : 1 - 2 (2 bit)

NVIC_FAULT_STAT_MUSTKE : Unstack Access Violation
bits : 3 - 6 (4 bit)

NVIC_FAULT_STAT_MSTKE : Stack Access Violation
bits : 4 - 8 (5 bit)

NVIC_FAULT_STAT_MLSPERR : Memory Management Fault on Floating-Point Lazy State Preservation
bits : 5 - 10 (6 bit)

NVIC_FAULT_STAT_MMARV : Memory Management Fault Address Register Valid
bits : 7 - 14 (8 bit)

NVIC_FAULT_STAT_IBUS : Instruction Bus Error
bits : 8 - 16 (9 bit)

NVIC_FAULT_STAT_PRECISE : Precise Data Bus Error
bits : 9 - 18 (10 bit)

NVIC_FAULT_STAT_IMPRE : Imprecise Data Bus Error
bits : 10 - 20 (11 bit)

NVIC_FAULT_STAT_BUSTKE : Unstack Bus Fault
bits : 11 - 22 (12 bit)

NVIC_FAULT_STAT_BSTKE : Stack Bus Fault
bits : 12 - 24 (13 bit)

NVIC_FAULT_STAT_BLSPERR : Bus Fault on Floating-Point Lazy State Preservation
bits : 13 - 26 (14 bit)

NVIC_FAULT_STAT_BFARV : Bus Fault Address Register Valid
bits : 15 - 30 (16 bit)

NVIC_FAULT_STAT_UNDEF : Undefined Instruction Usage Fault
bits : 16 - 32 (17 bit)

NVIC_FAULT_STAT_INVSTAT : Invalid State Usage Fault
bits : 17 - 34 (18 bit)

NVIC_FAULT_STAT_INVPC : Invalid PC Load Usage Fault
bits : 18 - 36 (19 bit)

NVIC_FAULT_STAT_NOCP : No Coprocessor Usage Fault
bits : 19 - 38 (20 bit)

NVIC_FAULT_STAT_UNALIGN : Unaligned Access Usage Fault
bits : 24 - 48 (25 bit)

NVIC_FAULT_STAT_DIV0 : Divide-by-Zero Usage Fault
bits : 25 - 50 (26 bit)


NVICHFAULT_STAT

Hard Fault Status
address_offset : 0xD2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICHFAULT_STAT NVICHFAULT_STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_HFAULT_STAT_VECT NVIC_HFAULT_STAT_FORCED NVIC_HFAULT_STAT_DBG

NVIC_HFAULT_STAT_VECT : Vector Table Read Fault
bits : 1 - 2 (2 bit)

NVIC_HFAULT_STAT_FORCED : Forced Hard Fault
bits : 30 - 60 (31 bit)

NVIC_HFAULT_STAT_DBG : Debug Event
bits : 31 - 62 (32 bit)


HFAULT_STAT

Hard Fault Status
address_offset : 0xD2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFAULT_STAT HFAULT_STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_HFAULT_STAT_VECT NVIC_HFAULT_STAT_FORCED NVIC_HFAULT_STAT_DBG

NVIC_HFAULT_STAT_VECT : Vector Table Read Fault
bits : 1 - 2 (2 bit)

NVIC_HFAULT_STAT_FORCED : Forced Hard Fault
bits : 30 - 60 (31 bit)

NVIC_HFAULT_STAT_DBG : Debug Event
bits : 31 - 62 (32 bit)


NVICDEBUG_STAT

Debug Status Register
address_offset : 0xD30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICDEBUG_STAT NVICDEBUG_STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_DEBUG_STAT_HALTED NVIC_DEBUG_STAT_BKPT NVIC_DEBUG_STAT_DWTTRAP NVIC_DEBUG_STAT_VCATCH NVIC_DEBUG_STAT_EXTRNL

NVIC_DEBUG_STAT_HALTED : Halt request
bits : 0 - 0 (1 bit)

NVIC_DEBUG_STAT_BKPT : Breakpoint instruction
bits : 1 - 2 (2 bit)

NVIC_DEBUG_STAT_DWTTRAP : DWT match
bits : 2 - 4 (3 bit)

NVIC_DEBUG_STAT_VCATCH : Vector catch
bits : 3 - 6 (4 bit)

NVIC_DEBUG_STAT_EXTRNL : EDBGRQ asserted
bits : 4 - 8 (5 bit)


DEBUG_STAT

Debug Status Register
address_offset : 0xD30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG_STAT DEBUG_STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_DEBUG_STAT_HALTED NVIC_DEBUG_STAT_BKPT NVIC_DEBUG_STAT_DWTTRAP NVIC_DEBUG_STAT_VCATCH NVIC_DEBUG_STAT_EXTRNL

NVIC_DEBUG_STAT_HALTED : Halt request
bits : 0 - 0 (1 bit)

NVIC_DEBUG_STAT_BKPT : Breakpoint instruction
bits : 1 - 2 (2 bit)

NVIC_DEBUG_STAT_DWTTRAP : DWT match
bits : 2 - 4 (3 bit)

NVIC_DEBUG_STAT_VCATCH : Vector catch
bits : 3 - 6 (4 bit)

NVIC_DEBUG_STAT_EXTRNL : EDBGRQ asserted
bits : 4 - 8 (5 bit)


NVICMM_ADDR

Memory Management Fault Address
address_offset : 0xD34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICMM_ADDR NVICMM_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MM_ADDR

NVIC_MM_ADDR : Fault Address
bits : 0 - 31 (32 bit)


MM_ADDR

Memory Management Fault Address
address_offset : 0xD34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MM_ADDR MM_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MM_ADDR

NVIC_MM_ADDR : Fault Address
bits : 0 - 31 (32 bit)


NVICFAULT_ADDR

Bus Fault Address
address_offset : 0xD38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICFAULT_ADDR NVICFAULT_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_FAULT_ADDR

NVIC_FAULT_ADDR : Fault Address
bits : 0 - 31 (32 bit)


FAULT_ADDR

Bus Fault Address
address_offset : 0xD38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FAULT_ADDR FAULT_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_FAULT_ADDR

NVIC_FAULT_ADDR : Fault Address
bits : 0 - 31 (32 bit)


NVICCPAC

Coprocessor Access Control
address_offset : 0xD88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICCPAC NVICCPAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_CPAC_CP10 NVIC_CPAC_CP11

NVIC_CPAC_CP10 : CP10 Coprocessor Access Privilege
bits : 20 - 41 (22 bit)

Enumeration:

0x0 : NVIC_CPAC_CP10_DIS

Access Denied

0x1 : NVIC_CPAC_CP10_PRIV

Privileged Access Only

0x3 : NVIC_CPAC_CP10_FULL

Full Access

End of enumeration elements list.

NVIC_CPAC_CP11 : CP11 Coprocessor Access Privilege
bits : 22 - 45 (24 bit)

Enumeration:

0x0 : NVIC_CPAC_CP11_DIS

Access Denied

0x1 : NVIC_CPAC_CP11_PRIV

Privileged Access Only

0x3 : NVIC_CPAC_CP11_FULL

Full Access

End of enumeration elements list.


CPAC

Coprocessor Access Control
address_offset : 0xD88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAC CPAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_CPAC_CP10 NVIC_CPAC_CP11

NVIC_CPAC_CP10 : CP10 Coprocessor Access Privilege
bits : 20 - 41 (22 bit)

Enumeration:

0x0 : NVIC_CPAC_CP10_DIS

Access Denied

0x1 : NVIC_CPAC_CP10_PRIV

Privileged Access Only

0x3 : NVIC_CPAC_CP10_FULL

Full Access

End of enumeration elements list.

NVIC_CPAC_CP11 : CP11 Coprocessor Access Privilege
bits : 22 - 45 (24 bit)

Enumeration:

0x0 : NVIC_CPAC_CP11_DIS

Access Denied

0x1 : NVIC_CPAC_CP11_PRIV

Privileged Access Only

0x3 : NVIC_CPAC_CP11_FULL

Full Access

End of enumeration elements list.


NVICMPU_TYPE

MPU Type
address_offset : 0xD90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICMPU_TYPE NVICMPU_TYPE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_TYPE_SEPARATE NVIC_MPU_TYPE_DREGION NVIC_MPU_TYPE_IREGION

NVIC_MPU_TYPE_SEPARATE : Separate or Unified MPU
bits : 0 - 0 (1 bit)

NVIC_MPU_TYPE_DREGION : Number of D Regions
bits : 8 - 23 (16 bit)

NVIC_MPU_TYPE_IREGION : Number of I Regions
bits : 16 - 39 (24 bit)


MPU_TYPE

MPU Type
address_offset : 0xD90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_TYPE MPU_TYPE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_TYPE_SEPARATE NVIC_MPU_TYPE_DREGION NVIC_MPU_TYPE_IREGION

NVIC_MPU_TYPE_SEPARATE : Separate or Unified MPU
bits : 0 - 0 (1 bit)

NVIC_MPU_TYPE_DREGION : Number of D Regions
bits : 8 - 23 (16 bit)

NVIC_MPU_TYPE_IREGION : Number of I Regions
bits : 16 - 39 (24 bit)


NVICMPU_CTRL

MPU Control
address_offset : 0xD94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICMPU_CTRL NVICMPU_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_CTRL_ENABLE NVIC_MPU_CTRL_HFNMIENA NVIC_MPU_CTRL_PRIVDEFEN

NVIC_MPU_CTRL_ENABLE : MPU Enable
bits : 0 - 0 (1 bit)

NVIC_MPU_CTRL_HFNMIENA : MPU Enabled During Faults
bits : 1 - 2 (2 bit)

NVIC_MPU_CTRL_PRIVDEFEN : MPU Default Region
bits : 2 - 4 (3 bit)


MPU_CTRL

MPU Control
address_offset : 0xD94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_CTRL MPU_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_CTRL_ENABLE NVIC_MPU_CTRL_HFNMIENA NVIC_MPU_CTRL_PRIVDEFEN

NVIC_MPU_CTRL_ENABLE : MPU Enable
bits : 0 - 0 (1 bit)

NVIC_MPU_CTRL_HFNMIENA : MPU Enabled During Faults
bits : 1 - 2 (2 bit)

NVIC_MPU_CTRL_PRIVDEFEN : MPU Default Region
bits : 2 - 4 (3 bit)


NVICMPU_NUMBER

MPU Region Number
address_offset : 0xD98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICMPU_NUMBER NVICMPU_NUMBER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_NUMBER

NVIC_MPU_NUMBER : MPU Region to Access
bits : 0 - 2 (3 bit)


MPU_NUMBER

MPU Region Number
address_offset : 0xD98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_NUMBER MPU_NUMBER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_NUMBER

NVIC_MPU_NUMBER : MPU Region to Access
bits : 0 - 2 (3 bit)


NVICMPU_BASE

MPU Region Base Address
address_offset : 0xD9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICMPU_BASE NVICMPU_BASE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_BASE_REGION NVIC_MPU_BASE_VALID NVIC_MPU_BASE_ADDR

NVIC_MPU_BASE_REGION : Region Number
bits : 0 - 2 (3 bit)

NVIC_MPU_BASE_VALID : Region Number Valid
bits : 4 - 8 (5 bit)

NVIC_MPU_BASE_ADDR : Base Address Mask
bits : 5 - 36 (32 bit)


MPU_BASE

MPU Region Base Address
address_offset : 0xD9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_BASE MPU_BASE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_BASE_REGION NVIC_MPU_BASE_VALID NVIC_MPU_BASE_ADDR

NVIC_MPU_BASE_REGION : Region Number
bits : 0 - 2 (3 bit)

NVIC_MPU_BASE_VALID : Region Number Valid
bits : 4 - 8 (5 bit)

NVIC_MPU_BASE_ADDR : Base Address Mask
bits : 5 - 36 (32 bit)


NVICMPU_ATTR

MPU Region Attribute and Size
address_offset : 0xDA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICMPU_ATTR NVICMPU_ATTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_ATTR_ENABLE NVIC_MPU_ATTR_SIZE NVIC_MPU_ATTR_SRD NVIC_MPU_ATTR_BUFFRABLE NVIC_MPU_ATTR_CACHEABLE NVIC_MPU_ATTR_SHAREABLE NVIC_MPU_ATTR_TEX NVIC_MPU_ATTR_AP NVIC_MPU_ATTR_XN

NVIC_MPU_ATTR_ENABLE : Region Enable
bits : 0 - 0 (1 bit)

NVIC_MPU_ATTR_SIZE : Region Size Mask
bits : 1 - 6 (6 bit)

NVIC_MPU_ATTR_SRD : Subregion Disable Bits
bits : 8 - 23 (16 bit)

NVIC_MPU_ATTR_BUFFRABLE : Bufferable
bits : 16 - 32 (17 bit)

NVIC_MPU_ATTR_CACHEABLE : Cacheable
bits : 17 - 34 (18 bit)

NVIC_MPU_ATTR_SHAREABLE : Shareable
bits : 18 - 36 (19 bit)

NVIC_MPU_ATTR_TEX : Type Extension Mask
bits : 19 - 40 (22 bit)

NVIC_MPU_ATTR_AP : Access Privilege
bits : 24 - 50 (27 bit)

NVIC_MPU_ATTR_XN : Instruction Access Disable
bits : 28 - 56 (29 bit)


MPU_ATTR

MPU Region Attribute and Size
address_offset : 0xDA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_ATTR MPU_ATTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_ATTR_ENABLE NVIC_MPU_ATTR_SIZE NVIC_MPU_ATTR_SRD NVIC_MPU_ATTR_BUFFRABLE NVIC_MPU_ATTR_CACHEABLE NVIC_MPU_ATTR_SHAREABLE NVIC_MPU_ATTR_TEX NVIC_MPU_ATTR_AP NVIC_MPU_ATTR_XN

NVIC_MPU_ATTR_ENABLE : Region Enable
bits : 0 - 0 (1 bit)

NVIC_MPU_ATTR_SIZE : Region Size Mask
bits : 1 - 6 (6 bit)

NVIC_MPU_ATTR_SRD : Subregion Disable Bits
bits : 8 - 23 (16 bit)

NVIC_MPU_ATTR_BUFFRABLE : Bufferable
bits : 16 - 32 (17 bit)

NVIC_MPU_ATTR_CACHEABLE : Cacheable
bits : 17 - 34 (18 bit)

NVIC_MPU_ATTR_SHAREABLE : Shareable
bits : 18 - 36 (19 bit)

NVIC_MPU_ATTR_TEX : Type Extension Mask
bits : 19 - 40 (22 bit)

NVIC_MPU_ATTR_AP : Access Privilege
bits : 24 - 50 (27 bit)

NVIC_MPU_ATTR_XN : Instruction Access Disable
bits : 28 - 56 (29 bit)


NVICMPU_BASE1

MPU Region Base Address Alias 1
address_offset : 0xDA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICMPU_BASE1 NVICMPU_BASE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_BASE1_REGION NVIC_MPU_BASE1_VALID NVIC_MPU_BASE1_ADDR

NVIC_MPU_BASE1_REGION : Region Number
bits : 0 - 2 (3 bit)

NVIC_MPU_BASE1_VALID : Region Number Valid
bits : 4 - 8 (5 bit)

NVIC_MPU_BASE1_ADDR : Base Address Mask
bits : 5 - 36 (32 bit)


MPU_BASE1

MPU Region Base Address Alias 1
address_offset : 0xDA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_BASE1 MPU_BASE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_BASE1_REGION NVIC_MPU_BASE1_VALID NVIC_MPU_BASE1_ADDR

NVIC_MPU_BASE1_REGION : Region Number
bits : 0 - 2 (3 bit)

NVIC_MPU_BASE1_VALID : Region Number Valid
bits : 4 - 8 (5 bit)

NVIC_MPU_BASE1_ADDR : Base Address Mask
bits : 5 - 36 (32 bit)


NVICMPU_ATTR1

MPU Region Attribute and Size Alias 1
address_offset : 0xDA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICMPU_ATTR1 NVICMPU_ATTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_ATTR1_ENABLE NVIC_MPU_ATTR1_SIZE NVIC_MPU_ATTR1_SRD NVIC_MPU_ATTR1_BUFFRABLE NVIC_MPU_ATTR1_CACHEABLE NVIC_MPU_ATTR1_SHAREABLE NVIC_MPU_ATTR1_TEX NVIC_MPU_ATTR1_AP NVIC_MPU_ATTR1_XN

NVIC_MPU_ATTR1_ENABLE : Region Enable
bits : 0 - 0 (1 bit)

NVIC_MPU_ATTR1_SIZE : Region Size Mask
bits : 1 - 6 (6 bit)

NVIC_MPU_ATTR1_SRD : Subregion Disable Bits
bits : 8 - 23 (16 bit)

NVIC_MPU_ATTR1_BUFFRABLE : Bufferable
bits : 16 - 32 (17 bit)

NVIC_MPU_ATTR1_CACHEABLE : Cacheable
bits : 17 - 34 (18 bit)

NVIC_MPU_ATTR1_SHAREABLE : Shareable
bits : 18 - 36 (19 bit)

NVIC_MPU_ATTR1_TEX : Type Extension Mask
bits : 19 - 40 (22 bit)

NVIC_MPU_ATTR1_AP : Access Privilege
bits : 24 - 50 (27 bit)

NVIC_MPU_ATTR1_XN : Instruction Access Disable
bits : 28 - 56 (29 bit)


MPU_ATTR1

MPU Region Attribute and Size Alias 1
address_offset : 0xDA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_ATTR1 MPU_ATTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_ATTR1_ENABLE NVIC_MPU_ATTR1_SIZE NVIC_MPU_ATTR1_SRD NVIC_MPU_ATTR1_BUFFRABLE NVIC_MPU_ATTR1_CACHEABLE NVIC_MPU_ATTR1_SHAREABLE NVIC_MPU_ATTR1_TEX NVIC_MPU_ATTR1_AP NVIC_MPU_ATTR1_XN

NVIC_MPU_ATTR1_ENABLE : Region Enable
bits : 0 - 0 (1 bit)

NVIC_MPU_ATTR1_SIZE : Region Size Mask
bits : 1 - 6 (6 bit)

NVIC_MPU_ATTR1_SRD : Subregion Disable Bits
bits : 8 - 23 (16 bit)

NVIC_MPU_ATTR1_BUFFRABLE : Bufferable
bits : 16 - 32 (17 bit)

NVIC_MPU_ATTR1_CACHEABLE : Cacheable
bits : 17 - 34 (18 bit)

NVIC_MPU_ATTR1_SHAREABLE : Shareable
bits : 18 - 36 (19 bit)

NVIC_MPU_ATTR1_TEX : Type Extension Mask
bits : 19 - 40 (22 bit)

NVIC_MPU_ATTR1_AP : Access Privilege
bits : 24 - 50 (27 bit)

NVIC_MPU_ATTR1_XN : Instruction Access Disable
bits : 28 - 56 (29 bit)


NVICMPU_BASE2

MPU Region Base Address Alias 2
address_offset : 0xDAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICMPU_BASE2 NVICMPU_BASE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_BASE2_REGION NVIC_MPU_BASE2_VALID NVIC_MPU_BASE2_ADDR

NVIC_MPU_BASE2_REGION : Region Number
bits : 0 - 2 (3 bit)

NVIC_MPU_BASE2_VALID : Region Number Valid
bits : 4 - 8 (5 bit)

NVIC_MPU_BASE2_ADDR : Base Address Mask
bits : 5 - 36 (32 bit)


MPU_BASE2

MPU Region Base Address Alias 2
address_offset : 0xDAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_BASE2 MPU_BASE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_BASE2_REGION NVIC_MPU_BASE2_VALID NVIC_MPU_BASE2_ADDR

NVIC_MPU_BASE2_REGION : Region Number
bits : 0 - 2 (3 bit)

NVIC_MPU_BASE2_VALID : Region Number Valid
bits : 4 - 8 (5 bit)

NVIC_MPU_BASE2_ADDR : Base Address Mask
bits : 5 - 36 (32 bit)


NVICMPU_ATTR2

MPU Region Attribute and Size Alias 2
address_offset : 0xDB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICMPU_ATTR2 NVICMPU_ATTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_ATTR2_ENABLE NVIC_MPU_ATTR2_SIZE NVIC_MPU_ATTR2_SRD NVIC_MPU_ATTR2_BUFFRABLE NVIC_MPU_ATTR2_CACHEABLE NVIC_MPU_ATTR2_SHAREABLE NVIC_MPU_ATTR2_TEX NVIC_MPU_ATTR2_AP NVIC_MPU_ATTR2_XN

NVIC_MPU_ATTR2_ENABLE : Region Enable
bits : 0 - 0 (1 bit)

NVIC_MPU_ATTR2_SIZE : Region Size Mask
bits : 1 - 6 (6 bit)

NVIC_MPU_ATTR2_SRD : Subregion Disable Bits
bits : 8 - 23 (16 bit)

NVIC_MPU_ATTR2_BUFFRABLE : Bufferable
bits : 16 - 32 (17 bit)

NVIC_MPU_ATTR2_CACHEABLE : Cacheable
bits : 17 - 34 (18 bit)

NVIC_MPU_ATTR2_SHAREABLE : Shareable
bits : 18 - 36 (19 bit)

NVIC_MPU_ATTR2_TEX : Type Extension Mask
bits : 19 - 40 (22 bit)

NVIC_MPU_ATTR2_AP : Access Privilege
bits : 24 - 50 (27 bit)

NVIC_MPU_ATTR2_XN : Instruction Access Disable
bits : 28 - 56 (29 bit)


MPU_ATTR2

MPU Region Attribute and Size Alias 2
address_offset : 0xDB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_ATTR2 MPU_ATTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_ATTR2_ENABLE NVIC_MPU_ATTR2_SIZE NVIC_MPU_ATTR2_SRD NVIC_MPU_ATTR2_BUFFRABLE NVIC_MPU_ATTR2_CACHEABLE NVIC_MPU_ATTR2_SHAREABLE NVIC_MPU_ATTR2_TEX NVIC_MPU_ATTR2_AP NVIC_MPU_ATTR2_XN

NVIC_MPU_ATTR2_ENABLE : Region Enable
bits : 0 - 0 (1 bit)

NVIC_MPU_ATTR2_SIZE : Region Size Mask
bits : 1 - 6 (6 bit)

NVIC_MPU_ATTR2_SRD : Subregion Disable Bits
bits : 8 - 23 (16 bit)

NVIC_MPU_ATTR2_BUFFRABLE : Bufferable
bits : 16 - 32 (17 bit)

NVIC_MPU_ATTR2_CACHEABLE : Cacheable
bits : 17 - 34 (18 bit)

NVIC_MPU_ATTR2_SHAREABLE : Shareable
bits : 18 - 36 (19 bit)

NVIC_MPU_ATTR2_TEX : Type Extension Mask
bits : 19 - 40 (22 bit)

NVIC_MPU_ATTR2_AP : Access Privilege
bits : 24 - 50 (27 bit)

NVIC_MPU_ATTR2_XN : Instruction Access Disable
bits : 28 - 56 (29 bit)


NVICMPU_BASE3

MPU Region Base Address Alias 3
address_offset : 0xDB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICMPU_BASE3 NVICMPU_BASE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_BASE3_REGION NVIC_MPU_BASE3_VALID NVIC_MPU_BASE3_ADDR

NVIC_MPU_BASE3_REGION : Region Number
bits : 0 - 2 (3 bit)

NVIC_MPU_BASE3_VALID : Region Number Valid
bits : 4 - 8 (5 bit)

NVIC_MPU_BASE3_ADDR : Base Address Mask
bits : 5 - 36 (32 bit)


MPU_BASE3

MPU Region Base Address Alias 3
address_offset : 0xDB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_BASE3 MPU_BASE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_BASE3_REGION NVIC_MPU_BASE3_VALID NVIC_MPU_BASE3_ADDR

NVIC_MPU_BASE3_REGION : Region Number
bits : 0 - 2 (3 bit)

NVIC_MPU_BASE3_VALID : Region Number Valid
bits : 4 - 8 (5 bit)

NVIC_MPU_BASE3_ADDR : Base Address Mask
bits : 5 - 36 (32 bit)


NVICMPU_ATTR3

MPU Region Attribute and Size Alias 3
address_offset : 0xDB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICMPU_ATTR3 NVICMPU_ATTR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_ATTR3_ENABLE NVIC_MPU_ATTR3_SIZE NVIC_MPU_ATTR3_SRD NVIC_MPU_ATTR3_BUFFRABLE NVIC_MPU_ATTR3_CACHEABLE NVIC_MPU_ATTR3_SHAREABLE NVIC_MPU_ATTR3_TEX NVIC_MPU_ATTR3_AP NVIC_MPU_ATTR3_XN

NVIC_MPU_ATTR3_ENABLE : Region Enable
bits : 0 - 0 (1 bit)

NVIC_MPU_ATTR3_SIZE : Region Size Mask
bits : 1 - 6 (6 bit)

NVIC_MPU_ATTR3_SRD : Subregion Disable Bits
bits : 8 - 23 (16 bit)

NVIC_MPU_ATTR3_BUFFRABLE : Bufferable
bits : 16 - 32 (17 bit)

NVIC_MPU_ATTR3_CACHEABLE : Cacheable
bits : 17 - 34 (18 bit)

NVIC_MPU_ATTR3_SHAREABLE : Shareable
bits : 18 - 36 (19 bit)

NVIC_MPU_ATTR3_TEX : Type Extension Mask
bits : 19 - 40 (22 bit)

NVIC_MPU_ATTR3_AP : Access Privilege
bits : 24 - 50 (27 bit)

NVIC_MPU_ATTR3_XN : Instruction Access Disable
bits : 28 - 56 (29 bit)


MPU_ATTR3

MPU Region Attribute and Size Alias 3
address_offset : 0xDB8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_ATTR3 MPU_ATTR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_MPU_ATTR3_ENABLE NVIC_MPU_ATTR3_SIZE NVIC_MPU_ATTR3_SRD NVIC_MPU_ATTR3_BUFFRABLE NVIC_MPU_ATTR3_CACHEABLE NVIC_MPU_ATTR3_SHAREABLE NVIC_MPU_ATTR3_TEX NVIC_MPU_ATTR3_AP NVIC_MPU_ATTR3_XN

NVIC_MPU_ATTR3_ENABLE : Region Enable
bits : 0 - 0 (1 bit)

NVIC_MPU_ATTR3_SIZE : Region Size Mask
bits : 1 - 6 (6 bit)

NVIC_MPU_ATTR3_SRD : Subregion Disable Bits
bits : 8 - 23 (16 bit)

NVIC_MPU_ATTR3_BUFFRABLE : Bufferable
bits : 16 - 32 (17 bit)

NVIC_MPU_ATTR3_CACHEABLE : Cacheable
bits : 17 - 34 (18 bit)

NVIC_MPU_ATTR3_SHAREABLE : Shareable
bits : 18 - 36 (19 bit)

NVIC_MPU_ATTR3_TEX : Type Extension Mask
bits : 19 - 40 (22 bit)

NVIC_MPU_ATTR3_AP : Access Privilege
bits : 24 - 50 (27 bit)

NVIC_MPU_ATTR3_XN : Instruction Access Disable
bits : 28 - 56 (29 bit)


NVICDBG_CTRL

Debug Control and Status Reg
address_offset : 0xDF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICDBG_CTRL NVICDBG_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_DBG_CTRL_C_DEBUGEN NVIC_DBG_CTRL_C_HALT NVIC_DBG_CTRL_C_STEP NVIC_DBG_CTRL_C_MASKINT NVIC_DBG_CTRL_C_SNAPSTALL NVIC_DBG_CTRL_S_REGRDY NVIC_DBG_CTRL_S_HALT NVIC_DBG_CTRL_S_SLEEP NVIC_DBG_CTRL_S_LOCKUP NVIC_DBG_CTRL_S_RETIRE_ST NVIC_DBG_CTRL_S_RESET_ST

NVIC_DBG_CTRL_C_DEBUGEN : Enable debug
bits : 0 - 0 (1 bit)

NVIC_DBG_CTRL_C_HALT : Halt the core
bits : 1 - 2 (2 bit)

NVIC_DBG_CTRL_C_STEP : Step the core
bits : 2 - 4 (3 bit)

NVIC_DBG_CTRL_C_MASKINT : Mask interrupts when stepping
bits : 3 - 6 (4 bit)

NVIC_DBG_CTRL_C_SNAPSTALL : Breaks a stalled load/store
bits : 5 - 10 (6 bit)

NVIC_DBG_CTRL_S_REGRDY : Register read/write available
bits : 16 - 32 (17 bit)

NVIC_DBG_CTRL_S_HALT : Core status on halt
bits : 17 - 34 (18 bit)

NVIC_DBG_CTRL_S_SLEEP : Core is sleeping
bits : 18 - 36 (19 bit)

NVIC_DBG_CTRL_S_LOCKUP : Core is locked up
bits : 19 - 38 (20 bit)

NVIC_DBG_CTRL_S_RETIRE_ST : Core has executed insruction since last read
bits : 24 - 48 (25 bit)

NVIC_DBG_CTRL_S_RESET_ST : Core has reset since last read
bits : 25 - 50 (26 bit)


DBG_CTRL

Debug Control and Status Reg
address_offset : 0xDF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBG_CTRL DBG_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_DBG_CTRL_C_DEBUGEN NVIC_DBG_CTRL_C_HALT NVIC_DBG_CTRL_C_STEP NVIC_DBG_CTRL_C_MASKINT NVIC_DBG_CTRL_C_SNAPSTALL NVIC_DBG_CTRL_S_REGRDY NVIC_DBG_CTRL_S_HALT NVIC_DBG_CTRL_S_SLEEP NVIC_DBG_CTRL_S_LOCKUP NVIC_DBG_CTRL_S_RETIRE_ST NVIC_DBG_CTRL_S_RESET_ST

NVIC_DBG_CTRL_C_DEBUGEN : Enable debug
bits : 0 - 0 (1 bit)

NVIC_DBG_CTRL_C_HALT : Halt the core
bits : 1 - 2 (2 bit)

NVIC_DBG_CTRL_C_STEP : Step the core
bits : 2 - 4 (3 bit)

NVIC_DBG_CTRL_C_MASKINT : Mask interrupts when stepping
bits : 3 - 6 (4 bit)

NVIC_DBG_CTRL_C_SNAPSTALL : Breaks a stalled load/store
bits : 5 - 10 (6 bit)

NVIC_DBG_CTRL_S_REGRDY : Register read/write available
bits : 16 - 32 (17 bit)

NVIC_DBG_CTRL_S_HALT : Core status on halt
bits : 17 - 34 (18 bit)

NVIC_DBG_CTRL_S_SLEEP : Core is sleeping
bits : 18 - 36 (19 bit)

NVIC_DBG_CTRL_S_LOCKUP : Core is locked up
bits : 19 - 38 (20 bit)

NVIC_DBG_CTRL_S_RETIRE_ST : Core has executed insruction since last read
bits : 24 - 48 (25 bit)

NVIC_DBG_CTRL_S_RESET_ST : Core has reset since last read
bits : 25 - 50 (26 bit)


NVICDBG_XFER

Debug Core Reg. Transfer Select
address_offset : 0xDF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICDBG_XFER NVICDBG_XFER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_DBG_XFER_REG_SEL NVIC_DBG_XFER_REG_WNR

NVIC_DBG_XFER_REG_SEL : Register
bits : 0 - 4 (5 bit)

Enumeration:

0x0 : NVIC_DBG_XFER_REG_R0

Register R0

0x1 : NVIC_DBG_XFER_REG_R1

Register R1

0x2 : NVIC_DBG_XFER_REG_R2

Register R2

0x3 : NVIC_DBG_XFER_REG_R3

Register R3

0x4 : NVIC_DBG_XFER_REG_R4

Register R4

0x5 : NVIC_DBG_XFER_REG_R5

Register R5

0x6 : NVIC_DBG_XFER_REG_R6

Register R6

0x7 : NVIC_DBG_XFER_REG_R7

Register R7

0x8 : NVIC_DBG_XFER_REG_R8

Register R8

0x9 : NVIC_DBG_XFER_REG_R9

Register R9

0xa : NVIC_DBG_XFER_REG_R10

Register R10

0xb : NVIC_DBG_XFER_REG_R11

Register R11

0xc : NVIC_DBG_XFER_REG_R12

Register R12

0xd : NVIC_DBG_XFER_REG_R13

Register R13

0xe : NVIC_DBG_XFER_REG_R14

Register R14

0xf : NVIC_DBG_XFER_REG_R15

Register R15

0x10 : NVIC_DBG_XFER_REG_FLAGS

xPSR/Flags register

0x11 : NVIC_DBG_XFER_REG_MSP

Main SP

0x12 : NVIC_DBG_XFER_REG_PSP

Process SP

0x13 : NVIC_DBG_XFER_REG_DSP

Deep SP

0x14 : NVIC_DBG_XFER_REG_CFBP

Control/Fault/BasePri/PriMask

End of enumeration elements list.

NVIC_DBG_XFER_REG_WNR : Write or not read
bits : 16 - 32 (17 bit)


DBG_XFER

Debug Core Reg. Transfer Select
address_offset : 0xDF4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBG_XFER DBG_XFER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_DBG_XFER_REG_SEL NVIC_DBG_XFER_REG_WNR

NVIC_DBG_XFER_REG_SEL : Register
bits : 0 - 4 (5 bit)

Enumeration:

0x0 : NVIC_DBG_XFER_REG_R0

Register R0

0x1 : NVIC_DBG_XFER_REG_R1

Register R1

0x2 : NVIC_DBG_XFER_REG_R2

Register R2

0x3 : NVIC_DBG_XFER_REG_R3

Register R3

0x4 : NVIC_DBG_XFER_REG_R4

Register R4

0x5 : NVIC_DBG_XFER_REG_R5

Register R5

0x6 : NVIC_DBG_XFER_REG_R6

Register R6

0x7 : NVIC_DBG_XFER_REG_R7

Register R7

0x8 : NVIC_DBG_XFER_REG_R8

Register R8

0x9 : NVIC_DBG_XFER_REG_R9

Register R9

0xa : NVIC_DBG_XFER_REG_R10

Register R10

0xb : NVIC_DBG_XFER_REG_R11

Register R11

0xc : NVIC_DBG_XFER_REG_R12

Register R12

0xd : NVIC_DBG_XFER_REG_R13

Register R13

0xe : NVIC_DBG_XFER_REG_R14

Register R14

0xf : NVIC_DBG_XFER_REG_R15

Register R15

0x10 : NVIC_DBG_XFER_REG_FLAGS

xPSR/Flags register

0x11 : NVIC_DBG_XFER_REG_MSP

Main SP

0x12 : NVIC_DBG_XFER_REG_PSP

Process SP

0x13 : NVIC_DBG_XFER_REG_DSP

Deep SP

0x14 : NVIC_DBG_XFER_REG_CFBP

Control/Fault/BasePri/PriMask

End of enumeration elements list.

NVIC_DBG_XFER_REG_WNR : Write or not read
bits : 16 - 32 (17 bit)


NVICDBG_DATA

Debug Core Register Data
address_offset : 0xDF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICDBG_DATA NVICDBG_DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_DBG_DATA

NVIC_DBG_DATA : Data temporary cache
bits : 0 - 31 (32 bit)


DBG_DATA

Debug Core Register Data
address_offset : 0xDF8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBG_DATA DBG_DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_DBG_DATA

NVIC_DBG_DATA : Data temporary cache
bits : 0 - 31 (32 bit)


NVICDBG_INT

Debug Reset Interrupt Control
address_offset : 0xDFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICDBG_INT NVICDBG_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_DBG_INT_RSTVCATCH NVIC_DBG_INT_RSTPENDING NVIC_DBG_INT_RSTPENDCLR NVIC_DBG_INT_RESET NVIC_DBG_INT_MMERR NVIC_DBG_INT_NOCPERR NVIC_DBG_INT_CHKERR NVIC_DBG_INT_STATERR NVIC_DBG_INT_BUSERR NVIC_DBG_INT_INTERR NVIC_DBG_INT_HARDERR

NVIC_DBG_INT_RSTVCATCH : Reset vector catch
bits : 0 - 0 (1 bit)

NVIC_DBG_INT_RSTPENDING : Core reset is pending
bits : 1 - 2 (2 bit)

NVIC_DBG_INT_RSTPENDCLR : Clear pending core reset
bits : 2 - 4 (3 bit)

NVIC_DBG_INT_RESET : Core reset status
bits : 3 - 6 (4 bit)

NVIC_DBG_INT_MMERR : Debug trap on mem manage fault
bits : 4 - 8 (5 bit)

NVIC_DBG_INT_NOCPERR : Debug trap on coprocessor error
bits : 5 - 10 (6 bit)

NVIC_DBG_INT_CHKERR : Debug trap on usage fault check
bits : 6 - 12 (7 bit)

NVIC_DBG_INT_STATERR : Debug trap on usage fault state
bits : 7 - 14 (8 bit)

NVIC_DBG_INT_BUSERR : Debug trap on bus error
bits : 8 - 16 (9 bit)

NVIC_DBG_INT_INTERR : Debug trap on interrupt errors
bits : 9 - 18 (10 bit)

NVIC_DBG_INT_HARDERR : Debug trap on hard fault
bits : 10 - 20 (11 bit)


DBG_INT

Debug Reset Interrupt Control
address_offset : 0xDFC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBG_INT DBG_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_DBG_INT_RSTVCATCH NVIC_DBG_INT_RSTPENDING NVIC_DBG_INT_RSTPENDCLR NVIC_DBG_INT_RESET NVIC_DBG_INT_MMERR NVIC_DBG_INT_NOCPERR NVIC_DBG_INT_CHKERR NVIC_DBG_INT_STATERR NVIC_DBG_INT_BUSERR NVIC_DBG_INT_INTERR NVIC_DBG_INT_HARDERR

NVIC_DBG_INT_RSTVCATCH : Reset vector catch
bits : 0 - 0 (1 bit)

NVIC_DBG_INT_RSTPENDING : Core reset is pending
bits : 1 - 2 (2 bit)

NVIC_DBG_INT_RSTPENDCLR : Clear pending core reset
bits : 2 - 4 (3 bit)

NVIC_DBG_INT_RESET : Core reset status
bits : 3 - 6 (4 bit)

NVIC_DBG_INT_MMERR : Debug trap on mem manage fault
bits : 4 - 8 (5 bit)

NVIC_DBG_INT_NOCPERR : Debug trap on coprocessor error
bits : 5 - 10 (6 bit)

NVIC_DBG_INT_CHKERR : Debug trap on usage fault check
bits : 6 - 12 (7 bit)

NVIC_DBG_INT_STATERR : Debug trap on usage fault state
bits : 7 - 14 (8 bit)

NVIC_DBG_INT_BUSERR : Debug trap on bus error
bits : 8 - 16 (9 bit)

NVIC_DBG_INT_INTERR : Debug trap on interrupt errors
bits : 9 - 18 (10 bit)

NVIC_DBG_INT_HARDERR : Debug trap on hard fault
bits : 10 - 20 (11 bit)


NVICSW_TRIG

Software Trigger Interrupt
address_offset : 0xF00 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

NVICSW_TRIG NVICSW_TRIG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_SW_TRIG_INTID

NVIC_SW_TRIG_INTID : Interrupt ID
bits : 0 - 7 (8 bit)
access : write-only


SW_TRIG

Software Trigger Interrupt
address_offset : 0xF00 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SW_TRIG SW_TRIG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_SW_TRIG_INTID

NVIC_SW_TRIG_INTID : Interrupt ID
bits : 0 - 7 (8 bit)
access : write-only


NVICFPCC

Floating-Point Context Control
address_offset : 0xF34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICFPCC NVICFPCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_FPCC_LSPACT NVIC_FPCC_USER NVIC_FPCC_THREAD NVIC_FPCC_HFRDY NVIC_FPCC_MMRDY NVIC_FPCC_BFRDY NVIC_FPCC_MONRDY NVIC_FPCC_LSPEN NVIC_FPCC_ASPEN

NVIC_FPCC_LSPACT : Lazy State Preservation Active
bits : 0 - 0 (1 bit)

NVIC_FPCC_USER : User Privilege Level
bits : 1 - 2 (2 bit)

NVIC_FPCC_THREAD : Thread Mode
bits : 3 - 6 (4 bit)

NVIC_FPCC_HFRDY : Hard Fault Ready
bits : 4 - 8 (5 bit)

NVIC_FPCC_MMRDY : Memory Management Fault Ready
bits : 5 - 10 (6 bit)

NVIC_FPCC_BFRDY : Bus Fault Ready
bits : 6 - 12 (7 bit)

NVIC_FPCC_MONRDY : Monitor Ready
bits : 8 - 16 (9 bit)

NVIC_FPCC_LSPEN : Lazy State Preservation Enable
bits : 30 - 60 (31 bit)

NVIC_FPCC_ASPEN : Automatic State Preservation Enable
bits : 31 - 62 (32 bit)


FPCC

Floating-Point Context Control
address_offset : 0xF34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPCC FPCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_FPCC_LSPACT NVIC_FPCC_USER NVIC_FPCC_THREAD NVIC_FPCC_HFRDY NVIC_FPCC_MMRDY NVIC_FPCC_BFRDY NVIC_FPCC_MONRDY NVIC_FPCC_LSPEN NVIC_FPCC_ASPEN

NVIC_FPCC_LSPACT : Lazy State Preservation Active
bits : 0 - 0 (1 bit)

NVIC_FPCC_USER : User Privilege Level
bits : 1 - 2 (2 bit)

NVIC_FPCC_THREAD : Thread Mode
bits : 3 - 6 (4 bit)

NVIC_FPCC_HFRDY : Hard Fault Ready
bits : 4 - 8 (5 bit)

NVIC_FPCC_MMRDY : Memory Management Fault Ready
bits : 5 - 10 (6 bit)

NVIC_FPCC_BFRDY : Bus Fault Ready
bits : 6 - 12 (7 bit)

NVIC_FPCC_MONRDY : Monitor Ready
bits : 8 - 16 (9 bit)

NVIC_FPCC_LSPEN : Lazy State Preservation Enable
bits : 30 - 60 (31 bit)

NVIC_FPCC_ASPEN : Automatic State Preservation Enable
bits : 31 - 62 (32 bit)


NVICFPCA

Floating-Point Context Address
address_offset : 0xF38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICFPCA NVICFPCA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_FPCA_ADDRESS

NVIC_FPCA_ADDRESS : Address
bits : 3 - 34 (32 bit)


FPCA

Floating-Point Context Address
address_offset : 0xF38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPCA FPCA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_FPCA_ADDRESS

NVIC_FPCA_ADDRESS : Address
bits : 3 - 34 (32 bit)


NVICFPDSC

Floating-Point Default Status Control
address_offset : 0xF3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICFPDSC NVICFPDSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_FPDSC_RMODE NVIC_FPDSC_FZ NVIC_FPDSC_DN NVIC_FPDSC_AHP

NVIC_FPDSC_RMODE : RMODE Bit Default
bits : 22 - 45 (24 bit)

Enumeration:

0x0 : NVIC_FPDSC_RMODE_RN

Round to Nearest (RN) mode

0x1 : NVIC_FPDSC_RMODE_RP

Round towards Plus Infinity (RP) mode

0x2 : NVIC_FPDSC_RMODE_RM

Round towards Minus Infinity (RM) mode

0x3 : NVIC_FPDSC_RMODE_RZ

Round towards Zero (RZ) mode

End of enumeration elements list.

NVIC_FPDSC_FZ : FZ Bit Default
bits : 24 - 48 (25 bit)

NVIC_FPDSC_DN : DN Bit Default
bits : 25 - 50 (26 bit)

NVIC_FPDSC_AHP : AHP Bit Default
bits : 26 - 52 (27 bit)


FPDSC

Floating-Point Default Status Control
address_offset : 0xF3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPDSC FPDSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_FPDSC_RMODE NVIC_FPDSC_FZ NVIC_FPDSC_DN NVIC_FPDSC_AHP

NVIC_FPDSC_RMODE : RMODE Bit Default
bits : 22 - 45 (24 bit)

Enumeration:

0x0 : NVIC_FPDSC_RMODE_RN

Round to Nearest (RN) mode

0x1 : NVIC_FPDSC_RMODE_RP

Round towards Plus Infinity (RP) mode

0x2 : NVIC_FPDSC_RMODE_RM

Round towards Minus Infinity (RM) mode

0x3 : NVIC_FPDSC_RMODE_RZ

Round towards Zero (RZ) mode

End of enumeration elements list.

NVIC_FPDSC_FZ : FZ Bit Default
bits : 24 - 48 (25 bit)

NVIC_FPDSC_DN : DN Bit Default
bits : 25 - 50 (26 bit)

NVIC_FPDSC_AHP : AHP Bit Default
bits : 26 - 52 (27 bit)



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