\n

SSI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SSI0CR0

CR0

SSI0CPSR

CPSR

SSI0IM

IM

SSI0RIS

RIS

SSI0MIS

MIS

SSI0ICR

ICR

SSI0DMACTL

DMACTL

SSI0CR1

CR1

SSI0DR

DR

SSI0SR

SR

SSI0CC

CC


SSI0CR0

SSI Control 0
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSI0CR0 SSI0CR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_CR0_DSS SSI_CR0_FRF SSI_CR0_SPO SSI_CR0_SPH SSI_CR0_SCR

SSI_CR0_DSS : SSI Data Size Select
bits : 0 - 3 (4 bit)

Enumeration:

0x3 : SSI_CR0_DSS_4

4-bit data

0x4 : SSI_CR0_DSS_5

5-bit data

0x5 : SSI_CR0_DSS_6

6-bit data

0x6 : SSI_CR0_DSS_7

7-bit data

0x7 : SSI_CR0_DSS_8

8-bit data

0x8 : SSI_CR0_DSS_9

9-bit data

0x9 : SSI_CR0_DSS_10

10-bit data

0xa : SSI_CR0_DSS_11

11-bit data

0xb : SSI_CR0_DSS_12

12-bit data

0xc : SSI_CR0_DSS_13

13-bit data

0xd : SSI_CR0_DSS_14

14-bit data

0xe : SSI_CR0_DSS_15

15-bit data

0xf : SSI_CR0_DSS_16

16-bit data

End of enumeration elements list.

SSI_CR0_FRF : SSI Frame Format Select
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : SSI_CR0_FRF_MOTO

Freescale SPI Frame Format

0x1 : SSI_CR0_FRF_TI

Texas Instruments Synchronous Serial Frame Format

0x2 : SSI_CR0_FRF_NMW

MICROWIRE Frame Format

End of enumeration elements list.

SSI_CR0_SPO : SSI Serial Clock Polarity
bits : 6 - 12 (7 bit)

SSI_CR0_SPH : SSI Serial Clock Phase
bits : 7 - 14 (8 bit)

SSI_CR0_SCR : SSI Serial Clock Rate
bits : 8 - 23 (16 bit)


CR0

SSI Control 0
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR0 CR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_CR0_DSS SSI_CR0_FRF SSI_CR0_SPO SSI_CR0_SPH SSI_CR0_SCR

SSI_CR0_DSS : SSI Data Size Select
bits : 0 - 3 (4 bit)

Enumeration:

0x3 : SSI_CR0_DSS_4

4-bit data

0x4 : SSI_CR0_DSS_5

5-bit data

0x5 : SSI_CR0_DSS_6

6-bit data

0x6 : SSI_CR0_DSS_7

7-bit data

0x7 : SSI_CR0_DSS_8

8-bit data

0x8 : SSI_CR0_DSS_9

9-bit data

0x9 : SSI_CR0_DSS_10

10-bit data

0xa : SSI_CR0_DSS_11

11-bit data

0xb : SSI_CR0_DSS_12

12-bit data

0xc : SSI_CR0_DSS_13

13-bit data

0xd : SSI_CR0_DSS_14

14-bit data

0xe : SSI_CR0_DSS_15

15-bit data

0xf : SSI_CR0_DSS_16

16-bit data

End of enumeration elements list.

SSI_CR0_FRF : SSI Frame Format Select
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : SSI_CR0_FRF_MOTO

Freescale SPI Frame Format

0x1 : SSI_CR0_FRF_TI

Texas Instruments Synchronous Serial Frame Format

0x2 : SSI_CR0_FRF_NMW

MICROWIRE Frame Format

End of enumeration elements list.

SSI_CR0_SPO : SSI Serial Clock Polarity
bits : 6 - 12 (7 bit)

SSI_CR0_SPH : SSI Serial Clock Phase
bits : 7 - 14 (8 bit)

SSI_CR0_SCR : SSI Serial Clock Rate
bits : 8 - 23 (16 bit)


SSI0CPSR

SSI Clock Prescale
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSI0CPSR SSI0CPSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_CPSR_CPSDVSR

SSI_CPSR_CPSDVSR : SSI Clock Prescale Divisor
bits : 0 - 7 (8 bit)


CPSR

SSI Clock Prescale
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPSR CPSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_CPSR_CPSDVSR

SSI_CPSR_CPSDVSR : SSI Clock Prescale Divisor
bits : 0 - 7 (8 bit)


SSI0IM

SSI Interrupt Mask
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSI0IM SSI0IM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_IM_RORIM SSI_IM_RTIM SSI_IM_RXIM SSI_IM_TXIM

SSI_IM_RORIM : SSI Receive Overrun Interrupt Mask
bits : 0 - 0 (1 bit)

SSI_IM_RTIM : SSI Receive Time-Out Interrupt Mask
bits : 1 - 2 (2 bit)

SSI_IM_RXIM : SSI Receive FIFO Interrupt Mask
bits : 2 - 4 (3 bit)

SSI_IM_TXIM : SSI Transmit FIFO Interrupt Mask
bits : 3 - 6 (4 bit)


IM

SSI Interrupt Mask
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IM IM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_IM_RORIM SSI_IM_RTIM SSI_IM_RXIM SSI_IM_TXIM

SSI_IM_RORIM : SSI Receive Overrun Interrupt Mask
bits : 0 - 0 (1 bit)

SSI_IM_RTIM : SSI Receive Time-Out Interrupt Mask
bits : 1 - 2 (2 bit)

SSI_IM_RXIM : SSI Receive FIFO Interrupt Mask
bits : 2 - 4 (3 bit)

SSI_IM_TXIM : SSI Transmit FIFO Interrupt Mask
bits : 3 - 6 (4 bit)


SSI0RIS

SSI Raw Interrupt Status
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSI0RIS SSI0RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_RIS_RORRIS SSI_RIS_RTRIS SSI_RIS_RXRIS SSI_RIS_TXRIS

SSI_RIS_RORRIS : SSI Receive Overrun Raw Interrupt Status
bits : 0 - 0 (1 bit)

SSI_RIS_RTRIS : SSI Receive Time-Out Raw Interrupt Status
bits : 1 - 2 (2 bit)

SSI_RIS_RXRIS : SSI Receive FIFO Raw Interrupt Status
bits : 2 - 4 (3 bit)

SSI_RIS_TXRIS : SSI Transmit FIFO Raw Interrupt Status
bits : 3 - 6 (4 bit)


RIS

SSI Raw Interrupt Status
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_RIS_RORRIS SSI_RIS_RTRIS SSI_RIS_RXRIS SSI_RIS_TXRIS

SSI_RIS_RORRIS : SSI Receive Overrun Raw Interrupt Status
bits : 0 - 0 (1 bit)

SSI_RIS_RTRIS : SSI Receive Time-Out Raw Interrupt Status
bits : 1 - 2 (2 bit)

SSI_RIS_RXRIS : SSI Receive FIFO Raw Interrupt Status
bits : 2 - 4 (3 bit)

SSI_RIS_TXRIS : SSI Transmit FIFO Raw Interrupt Status
bits : 3 - 6 (4 bit)


SSI0MIS

SSI Masked Interrupt Status
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSI0MIS SSI0MIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_MIS_RORMIS SSI_MIS_RTMIS SSI_MIS_RXMIS SSI_MIS_TXMIS

SSI_MIS_RORMIS : SSI Receive Overrun Masked Interrupt Status
bits : 0 - 0 (1 bit)

SSI_MIS_RTMIS : SSI Receive Time-Out Masked Interrupt Status
bits : 1 - 2 (2 bit)

SSI_MIS_RXMIS : SSI Receive FIFO Masked Interrupt Status
bits : 2 - 4 (3 bit)

SSI_MIS_TXMIS : SSI Transmit FIFO Masked Interrupt Status
bits : 3 - 6 (4 bit)


MIS

SSI Masked Interrupt Status
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIS MIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_MIS_RORMIS SSI_MIS_RTMIS SSI_MIS_RXMIS SSI_MIS_TXMIS

SSI_MIS_RORMIS : SSI Receive Overrun Masked Interrupt Status
bits : 0 - 0 (1 bit)

SSI_MIS_RTMIS : SSI Receive Time-Out Masked Interrupt Status
bits : 1 - 2 (2 bit)

SSI_MIS_RXMIS : SSI Receive FIFO Masked Interrupt Status
bits : 2 - 4 (3 bit)

SSI_MIS_TXMIS : SSI Transmit FIFO Masked Interrupt Status
bits : 3 - 6 (4 bit)


SSI0ICR

SSI Interrupt Clear
address_offset : 0x20 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SSI0ICR SSI0ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_ICR_RORIC SSI_ICR_RTIC

SSI_ICR_RORIC : SSI Receive Overrun Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

SSI_ICR_RTIC : SSI Receive Time-Out Interrupt Clear
bits : 1 - 2 (2 bit)
access : write-only


ICR

SSI Interrupt Clear
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICR ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_ICR_RORIC SSI_ICR_RTIC

SSI_ICR_RORIC : SSI Receive Overrun Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

SSI_ICR_RTIC : SSI Receive Time-Out Interrupt Clear
bits : 1 - 2 (2 bit)
access : write-only


SSI0DMACTL

SSI DMA Control
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSI0DMACTL SSI0DMACTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_DMACTL_RXDMAE SSI_DMACTL_TXDMAE

SSI_DMACTL_RXDMAE : Receive DMA Enable
bits : 0 - 0 (1 bit)

SSI_DMACTL_TXDMAE : Transmit DMA Enable
bits : 1 - 2 (2 bit)


DMACTL

SSI DMA Control
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACTL DMACTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_DMACTL_RXDMAE SSI_DMACTL_TXDMAE

SSI_DMACTL_RXDMAE : Receive DMA Enable
bits : 0 - 0 (1 bit)

SSI_DMACTL_TXDMAE : Transmit DMA Enable
bits : 1 - 2 (2 bit)


SSI0CR1

SSI Control 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSI0CR1 SSI0CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_CR1_LBM SSI_CR1_SSE SSI_CR1_MS SSI_CR1_SOD SSI_CR1_EOT SSI_CR1_SLBY6

SSI_CR1_LBM : SSI Loopback Mode
bits : 0 - 0 (1 bit)

SSI_CR1_SSE : SSI Synchronous Serial Port Enable
bits : 1 - 2 (2 bit)

SSI_CR1_MS : SSI Master/Slave Select
bits : 2 - 4 (3 bit)

SSI_CR1_SOD : SSI Slave Mode Output Disable
bits : 3 - 6 (4 bit)

SSI_CR1_EOT : End of Transmission
bits : 4 - 8 (5 bit)

SSI_CR1_SLBY6 : Slave Bypass Mode
bits : 5 - 10 (6 bit)


CR1

SSI Control 1
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_CR1_LBM SSI_CR1_SSE SSI_CR1_MS SSI_CR1_SOD SSI_CR1_EOT SSI_CR1_SLBY6

SSI_CR1_LBM : SSI Loopback Mode
bits : 0 - 0 (1 bit)

SSI_CR1_SSE : SSI Synchronous Serial Port Enable
bits : 1 - 2 (2 bit)

SSI_CR1_MS : SSI Master/Slave Select
bits : 2 - 4 (3 bit)

SSI_CR1_SOD : SSI Slave Mode Output Disable
bits : 3 - 6 (4 bit)

SSI_CR1_EOT : End of Transmission
bits : 4 - 8 (5 bit)

SSI_CR1_SLBY6 : Slave Bypass Mode
bits : 5 - 10 (6 bit)


SSI0DR

SSI Data
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSI0DR SSI0DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_DR_DATA

SSI_DR_DATA : SSI Receive/Transmit Data
bits : 0 - 15 (16 bit)


DR

SSI Data
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_DR_DATA

SSI_DR_DATA : SSI Receive/Transmit Data
bits : 0 - 15 (16 bit)


SSI0SR

SSI Status
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSI0SR SSI0SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_SR_TFE SSI_SR_TNF SSI_SR_RNE SSI_SR_RFF SSI_SR_BSY

SSI_SR_TFE : SSI Transmit FIFO Empty
bits : 0 - 0 (1 bit)

SSI_SR_TNF : SSI Transmit FIFO Not Full
bits : 1 - 2 (2 bit)

SSI_SR_RNE : SSI Receive FIFO Not Empty
bits : 2 - 4 (3 bit)

SSI_SR_RFF : SSI Receive FIFO Full
bits : 3 - 6 (4 bit)

SSI_SR_BSY : SSI Busy Bit
bits : 4 - 8 (5 bit)


SR

SSI Status
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_SR_TFE SSI_SR_TNF SSI_SR_RNE SSI_SR_RFF SSI_SR_BSY

SSI_SR_TFE : SSI Transmit FIFO Empty
bits : 0 - 0 (1 bit)

SSI_SR_TNF : SSI Transmit FIFO Not Full
bits : 1 - 2 (2 bit)

SSI_SR_RNE : SSI Receive FIFO Not Empty
bits : 2 - 4 (3 bit)

SSI_SR_RFF : SSI Receive FIFO Full
bits : 3 - 6 (4 bit)

SSI_SR_BSY : SSI Busy Bit
bits : 4 - 8 (5 bit)


SSI0CC

SSI Clock Configuration
address_offset : 0xFC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSI0CC SSI0CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_CC_CS

SSI_CC_CS : SSI Baud Clock Source
bits : 0 - 3 (4 bit)

Enumeration:

0x0 : SSI_CC_CS_SYSPLL

Either the system clock (if the PLL bypass is in effect) or the PLL output (default)

0x5 : SSI_CC_CS_PIOSC

PIOSC

End of enumeration elements list.


CC

SSI Clock Configuration
address_offset : 0xFC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_CC_CS

SSI_CC_CS : SSI Baud Clock Source
bits : 0 - 3 (4 bit)

Enumeration:

0x0 : SSI_CC_CS_SYSPLL

Either the system clock (if the PLL bypass is in effect) or the PLL output (default)

0x5 : SSI_CC_CS_PIOSC

PIOSC

End of enumeration elements list.



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