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I2C

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

I2C0MSA

MSA

I2C0MIMR

MIMR

I2C0MRIS

MRIS

I2C0MMIS

MMIS

I2C0MICR

MICR

I2C0MCR

MCR

I2C0MCLKOCNT

MCLKOCNT

I2C0MBMON

MBMON

I2C0MCS

MCS

I2C0MDR

MDR

I2C0SOAR

SOAR

I2C0SCSR

SCSR

I2C0SDR

SDR

I2C0SIMR

SIMR

I2C0SRIS

SRIS

I2C0SMIS

SMIS

I2C0SICR

SICR

I2C0SOAR2

SOAR2

I2C0SACKCTL

SACKCTL

I2C0MTPR

MTPR

I2C0PP

PP


I2C0MSA

I2C Master Slave Address
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MSA I2C0MSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MSA_RS I2C_MSA_SA

I2C_MSA_RS : Receive not send
bits : 0 - 0 (1 bit)

I2C_MSA_SA : I2C Slave Address
bits : 1 - 8 (8 bit)


MSA

I2C Master Slave Address
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSA MSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MSA_RS I2C_MSA_SA

I2C_MSA_RS : Receive not send
bits : 0 - 0 (1 bit)

I2C_MSA_SA : I2C Slave Address
bits : 1 - 8 (8 bit)


I2C0MIMR

I2C Master Interrupt Mask
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MIMR I2C0MIMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MIMR_IM I2C_MIMR_CLKIM

I2C_MIMR_IM : Interrupt Mask
bits : 0 - 0 (1 bit)

I2C_MIMR_CLKIM : Clock Timeout Interrupt Mask
bits : 1 - 2 (2 bit)


MIMR

I2C Master Interrupt Mask
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIMR MIMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MIMR_IM I2C_MIMR_CLKIM

I2C_MIMR_IM : Interrupt Mask
bits : 0 - 0 (1 bit)

I2C_MIMR_CLKIM : Clock Timeout Interrupt Mask
bits : 1 - 2 (2 bit)


I2C0MRIS

I2C Master Raw Interrupt Status
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MRIS I2C0MRIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MRIS_RIS I2C_MRIS_CLKRIS

I2C_MRIS_RIS : Raw Interrupt Status
bits : 0 - 0 (1 bit)

I2C_MRIS_CLKRIS : Clock Timeout Raw Interrupt Status
bits : 1 - 2 (2 bit)


MRIS

I2C Master Raw Interrupt Status
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MRIS MRIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MRIS_RIS I2C_MRIS_CLKRIS

I2C_MRIS_RIS : Raw Interrupt Status
bits : 0 - 0 (1 bit)

I2C_MRIS_CLKRIS : Clock Timeout Raw Interrupt Status
bits : 1 - 2 (2 bit)


I2C0MMIS

I2C Master Masked Interrupt Status
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MMIS I2C0MMIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MMIS_MIS I2C_MMIS_CLKMIS

I2C_MMIS_MIS : Masked Interrupt Status
bits : 0 - 0 (1 bit)

I2C_MMIS_CLKMIS : Clock Timeout Masked Interrupt Status
bits : 1 - 2 (2 bit)


MMIS

I2C Master Masked Interrupt Status
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMIS MMIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MMIS_MIS I2C_MMIS_CLKMIS

I2C_MMIS_MIS : Masked Interrupt Status
bits : 0 - 0 (1 bit)

I2C_MMIS_CLKMIS : Clock Timeout Masked Interrupt Status
bits : 1 - 2 (2 bit)


I2C0MICR

I2C Master Interrupt Clear
address_offset : 0x1C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

I2C0MICR I2C0MICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MICR_IC I2C_MICR_CLKIC

I2C_MICR_IC : Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

I2C_MICR_CLKIC : Clock Timeout Interrupt Clear
bits : 1 - 2 (2 bit)
access : write-only


MICR

I2C Master Interrupt Clear
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MICR MICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MICR_IC I2C_MICR_CLKIC

I2C_MICR_IC : Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

I2C_MICR_CLKIC : Clock Timeout Interrupt Clear
bits : 1 - 2 (2 bit)
access : write-only


I2C0MCR

I2C Master Configuration
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MCR I2C0MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MCR_LPBK I2C_MCR_MFE I2C_MCR_SFE

I2C_MCR_LPBK : I2C Loopback
bits : 0 - 0 (1 bit)

I2C_MCR_MFE : I2C Master Function Enable
bits : 4 - 8 (5 bit)

I2C_MCR_SFE : I2C Slave Function Enable
bits : 5 - 10 (6 bit)


MCR

I2C Master Configuration
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MCR_LPBK I2C_MCR_MFE I2C_MCR_SFE

I2C_MCR_LPBK : I2C Loopback
bits : 0 - 0 (1 bit)

I2C_MCR_MFE : I2C Master Function Enable
bits : 4 - 8 (5 bit)

I2C_MCR_SFE : I2C Slave Function Enable
bits : 5 - 10 (6 bit)


I2C0MCLKOCNT

I2C Master Clock Low Timeout Count
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MCLKOCNT I2C0MCLKOCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MCLKOCNT_CNTL

I2C_MCLKOCNT_CNTL : I2C Master Count
bits : 0 - 7 (8 bit)


MCLKOCNT

I2C Master Clock Low Timeout Count
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCLKOCNT MCLKOCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MCLKOCNT_CNTL

I2C_MCLKOCNT_CNTL : I2C Master Count
bits : 0 - 7 (8 bit)


I2C0MBMON

I2C Master Bus Monitor
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MBMON I2C0MBMON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MBMON_SCL I2C_MBMON_SDA

I2C_MBMON_SCL : I2C SCL Status
bits : 0 - 0 (1 bit)

I2C_MBMON_SDA : I2C SDA Status
bits : 1 - 2 (2 bit)


MBMON

I2C Master Bus Monitor
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MBMON MBMON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MBMON_SCL I2C_MBMON_SDA

I2C_MBMON_SCL : I2C SCL Status
bits : 0 - 0 (1 bit)

I2C_MBMON_SDA : I2C SDA Status
bits : 1 - 2 (2 bit)


I2C0MCS

I2C Master Control/Status
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MCS I2C0MCS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MCS_RUN I2C_MCS_START I2C_MCS_ADRACK I2C_MCS_ACK I2C_MCS_ARBLST I2C_MCS_IDLE I2C_MCS_BUSBSY I2C_MCS_CLKTO

I2C_MCS_RUN : I2C Master Enable
bits : 0 - 0 (1 bit)

I2C_MCS_START : Generate START
bits : 1 - 2 (2 bit)

I2C_MCS_ADRACK : Acknowledge Address
bits : 2 - 4 (3 bit)

I2C_MCS_ACK : Data Acknowledge Enable
bits : 3 - 6 (4 bit)

I2C_MCS_ARBLST : Arbitration Lost
bits : 4 - 8 (5 bit)

I2C_MCS_IDLE : I2C Idle
bits : 5 - 10 (6 bit)

I2C_MCS_BUSBSY : Bus Busy
bits : 6 - 12 (7 bit)

I2C_MCS_CLKTO : Clock Timeout Error
bits : 7 - 14 (8 bit)


MCS

I2C Master Control/Status
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCS MCS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MCS_RUN I2C_MCS_BUSY I2C_MCS_START I2C_MCS_ERROR I2C_MCS_ADRACK I2C_MCS_STOP I2C_MCS_ACK I2C_MCS_DATACK I2C_MCS_ARBLST I2C_MCS_IDLE I2C_MCS_BUSBSY I2C_MCS_CLKTO

I2C_MCS_RUN : I2C Master Enable
bits : 0 - 0 (1 bit)

I2C_MCS_BUSY : I2C Busy
bits : 0 - 0 (1 bit)

I2C_MCS_START : Generate START
bits : 1 - 2 (2 bit)

I2C_MCS_ERROR : Error
bits : 1 - 2 (2 bit)

I2C_MCS_ADRACK : Acknowledge Address
bits : 2 - 4 (3 bit)

I2C_MCS_STOP : Generate STOP
bits : 2 - 4 (3 bit)

I2C_MCS_ACK : Data Acknowledge Enable
bits : 3 - 6 (4 bit)

I2C_MCS_DATACK : Acknowledge Data
bits : 3 - 6 (4 bit)

I2C_MCS_ARBLST : Arbitration Lost
bits : 4 - 8 (5 bit)

I2C_MCS_IDLE : I2C Idle
bits : 5 - 10 (6 bit)

I2C_MCS_BUSBSY : Bus Busy
bits : 6 - 12 (7 bit)

I2C_MCS_CLKTO : Clock Timeout Error
bits : 7 - 14 (8 bit)


I2C0MDR

I2C Master Data
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MDR I2C0MDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MDR_DATA

I2C_MDR_DATA : Data Transferred
bits : 0 - 7 (8 bit)


MDR

I2C Master Data
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDR MDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MDR_DATA

I2C_MDR_DATA : Data Transferred
bits : 0 - 7 (8 bit)


I2C0SOAR

I2C Slave Own Address
address_offset : 0x800 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0SOAR I2C0SOAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SOAR_OAR

I2C_SOAR_OAR : I2C Slave Own Address
bits : 0 - 6 (7 bit)


SOAR

I2C Slave Own Address
address_offset : 0x800 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOAR SOAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SOAR_OAR

I2C_SOAR_OAR : I2C Slave Own Address
bits : 0 - 6 (7 bit)


I2C0SCSR

I2C Slave Control/Status
address_offset : 0x804 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0SCSR I2C0SCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SCSR_RREQ I2C_SCSR_TREQ I2C_SCSR_FBR I2C_SCSR_OAR2SEL

I2C_SCSR_RREQ : Receive Request
bits : 0 - 0 (1 bit)

I2C_SCSR_TREQ : Transmit Request
bits : 1 - 2 (2 bit)

I2C_SCSR_FBR : First Byte Received
bits : 2 - 4 (3 bit)

I2C_SCSR_OAR2SEL : OAR2 Address Matched
bits : 3 - 6 (4 bit)


SCSR

I2C Slave Control/Status
address_offset : 0x804 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCSR SCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SCSR_RREQ I2C_SCSR_DA I2C_SCSR_TREQ I2C_SCSR_FBR I2C_SCSR_OAR2SEL

I2C_SCSR_RREQ : Receive Request
bits : 0 - 0 (1 bit)

I2C_SCSR_DA : Device Active
bits : 0 - 0 (1 bit)

I2C_SCSR_TREQ : Transmit Request
bits : 1 - 2 (2 bit)

I2C_SCSR_FBR : First Byte Received
bits : 2 - 4 (3 bit)

I2C_SCSR_OAR2SEL : OAR2 Address Matched
bits : 3 - 6 (4 bit)


I2C0SDR

I2C Slave Data
address_offset : 0x808 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0SDR I2C0SDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SDR_DATA

I2C_SDR_DATA : Data for Transfer
bits : 0 - 7 (8 bit)


SDR

I2C Slave Data
address_offset : 0x808 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDR SDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SDR_DATA

I2C_SDR_DATA : Data for Transfer
bits : 0 - 7 (8 bit)


I2C0SIMR

I2C Slave Interrupt Mask
address_offset : 0x80C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0SIMR I2C0SIMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SIMR_DATAIM I2C_SIMR_STARTIM I2C_SIMR_STOPIM

I2C_SIMR_DATAIM : Data Interrupt Mask
bits : 0 - 0 (1 bit)

I2C_SIMR_STARTIM : Start Condition Interrupt Mask
bits : 1 - 2 (2 bit)

I2C_SIMR_STOPIM : Stop Condition Interrupt Mask
bits : 2 - 4 (3 bit)


SIMR

I2C Slave Interrupt Mask
address_offset : 0x80C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIMR SIMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SIMR_DATAIM I2C_SIMR_STARTIM I2C_SIMR_STOPIM

I2C_SIMR_DATAIM : Data Interrupt Mask
bits : 0 - 0 (1 bit)

I2C_SIMR_STARTIM : Start Condition Interrupt Mask
bits : 1 - 2 (2 bit)

I2C_SIMR_STOPIM : Stop Condition Interrupt Mask
bits : 2 - 4 (3 bit)


I2C0SRIS

I2C Slave Raw Interrupt Status
address_offset : 0x810 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0SRIS I2C0SRIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SRIS_DATARIS I2C_SRIS_STARTRIS I2C_SRIS_STOPRIS

I2C_SRIS_DATARIS : Data Raw Interrupt Status
bits : 0 - 0 (1 bit)

I2C_SRIS_STARTRIS : Start Condition Raw Interrupt Status
bits : 1 - 2 (2 bit)

I2C_SRIS_STOPRIS : Stop Condition Raw Interrupt Status
bits : 2 - 4 (3 bit)


SRIS

I2C Slave Raw Interrupt Status
address_offset : 0x810 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRIS SRIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SRIS_DATARIS I2C_SRIS_STARTRIS I2C_SRIS_STOPRIS

I2C_SRIS_DATARIS : Data Raw Interrupt Status
bits : 0 - 0 (1 bit)

I2C_SRIS_STARTRIS : Start Condition Raw Interrupt Status
bits : 1 - 2 (2 bit)

I2C_SRIS_STOPRIS : Stop Condition Raw Interrupt Status
bits : 2 - 4 (3 bit)


I2C0SMIS

I2C Slave Masked Interrupt Status
address_offset : 0x814 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0SMIS I2C0SMIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SMIS_DATAMIS I2C_SMIS_STARTMIS I2C_SMIS_STOPMIS

I2C_SMIS_DATAMIS : Data Masked Interrupt Status
bits : 0 - 0 (1 bit)

I2C_SMIS_STARTMIS : Start Condition Masked Interrupt Status
bits : 1 - 2 (2 bit)

I2C_SMIS_STOPMIS : Stop Condition Masked Interrupt Status
bits : 2 - 4 (3 bit)


SMIS

I2C Slave Masked Interrupt Status
address_offset : 0x814 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMIS SMIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SMIS_DATAMIS I2C_SMIS_STARTMIS I2C_SMIS_STOPMIS

I2C_SMIS_DATAMIS : Data Masked Interrupt Status
bits : 0 - 0 (1 bit)

I2C_SMIS_STARTMIS : Start Condition Masked Interrupt Status
bits : 1 - 2 (2 bit)

I2C_SMIS_STOPMIS : Stop Condition Masked Interrupt Status
bits : 2 - 4 (3 bit)


I2C0SICR

I2C Slave Interrupt Clear
address_offset : 0x818 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

I2C0SICR I2C0SICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SICR_DATAIC I2C_SICR_STARTIC I2C_SICR_STOPIC

I2C_SICR_DATAIC : Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

I2C_SICR_STARTIC : Start Condition Interrupt Clear
bits : 1 - 2 (2 bit)
access : write-only

I2C_SICR_STOPIC : Stop Condition Interrupt Clear
bits : 2 - 4 (3 bit)
access : write-only


SICR

I2C Slave Interrupt Clear
address_offset : 0x818 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SICR SICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SICR_DATAIC I2C_SICR_STARTIC I2C_SICR_STOPIC

I2C_SICR_DATAIC : Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

I2C_SICR_STARTIC : Start Condition Interrupt Clear
bits : 1 - 2 (2 bit)
access : write-only

I2C_SICR_STOPIC : Stop Condition Interrupt Clear
bits : 2 - 4 (3 bit)
access : write-only


I2C0SOAR2

I2C Slave Own Address 2
address_offset : 0x81C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0SOAR2 I2C0SOAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SOAR2_OAR2 I2C_SOAR2_OAR2EN

I2C_SOAR2_OAR2 : I2C Slave Own Address 2
bits : 0 - 6 (7 bit)

I2C_SOAR2_OAR2EN : I2C Slave Own Address 2 Enable
bits : 7 - 14 (8 bit)


SOAR2

I2C Slave Own Address 2
address_offset : 0x81C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOAR2 SOAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SOAR2_OAR2 I2C_SOAR2_OAR2EN

I2C_SOAR2_OAR2 : I2C Slave Own Address 2
bits : 0 - 6 (7 bit)

I2C_SOAR2_OAR2EN : I2C Slave Own Address 2 Enable
bits : 7 - 14 (8 bit)


I2C0SACKCTL

I2C ACK Control
address_offset : 0x820 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0SACKCTL I2C0SACKCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SACKCTL_ACKOEN I2C_SACKCTL_ACKOVAL

I2C_SACKCTL_ACKOEN : I2C Slave ACK Override Enable
bits : 0 - 0 (1 bit)

I2C_SACKCTL_ACKOVAL : I2C Slave ACK Override Value
bits : 1 - 2 (2 bit)


SACKCTL

I2C ACK Control
address_offset : 0x820 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SACKCTL SACKCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SACKCTL_ACKOEN I2C_SACKCTL_ACKOVAL

I2C_SACKCTL_ACKOEN : I2C Slave ACK Override Enable
bits : 0 - 0 (1 bit)

I2C_SACKCTL_ACKOVAL : I2C Slave ACK Override Value
bits : 1 - 2 (2 bit)


I2C0MTPR

I2C Master Timer Period
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MTPR I2C0MTPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MTPR_TPR

I2C_MTPR_TPR : SCL Clock Period
bits : 0 - 6 (7 bit)


MTPR

I2C Master Timer Period
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTPR MTPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MTPR_TPR

I2C_MTPR_TPR : SCL Clock Period
bits : 0 - 6 (7 bit)


I2C0PP

I2C Peripheral Properties
address_offset : 0xFC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0PP I2C0PP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_PP_HS

I2C_PP_HS : High-Speed Capable
bits : 0 - 0 (1 bit)


PP

I2C Peripheral Properties
address_offset : 0xFC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PP PP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_PP_HS

I2C_PP_HS : High-Speed Capable
bits : 0 - 0 (1 bit)



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