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CAN

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CAN0CTL

CTL

CAN0INT

INT

CAN0TXRQ1

TXRQ1

CAN0TXRQ2

TXRQ2

CAN0NWDA1

NWDA1

CAN0NWDA2

NWDA2

CAN0TST

TST

CAN0MSG1INT

MSG1INT

CAN0MSG2INT

MSG2INT

CAN0MSG1VAL

MSG1VAL

CAN0MSG2VAL

MSG2VAL

CAN0BRPE

BRPE

CAN0IF1CRQ

IF1CRQ

CAN0IF1CMSK

IF1CMSK

CAN0IF1MSK1

IF1MSK1

CAN0IF1MSK2

IF1MSK2

CAN0IF1ARB1

IF1ARB1

CAN0IF1ARB2

IF1ARB2

CAN0IF1MCTL

IF1MCTL

CAN0IF1DA1

IF1DA1

CAN0STS

STS

CAN0IF1DA2

IF1DA2

CAN0IF1DB1

IF1DB1

CAN0IF1DB2

IF1DB2

CAN0ERR

ERR

CAN0IF2CRQ

IF2CRQ

CAN0IF2CMSK

IF2CMSK

CAN0IF2MSK1

IF2MSK1

CAN0IF2MSK2

IF2MSK2

CAN0IF2ARB1

IF2ARB1

CAN0IF2ARB2

IF2ARB2

CAN0IF2MCTL

IF2MCTL

CAN0IF2DA1

IF2DA1

CAN0IF2DA2

IF2DA2

CAN0IF2DB1

IF2DB1

CAN0IF2DB2

IF2DB2

CAN0BIT

BIT


CAN0CTL

CAN Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0CTL CAN0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_CTL_INIT CAN_CTL_IE CAN_CTL_SIE CAN_CTL_EIE CAN_CTL_DAR CAN_CTL_CCE CAN_CTL_TEST

CAN_CTL_INIT : Initialization
bits : 0 - 0 (1 bit)

CAN_CTL_IE : CAN Interrupt Enable
bits : 1 - 2 (2 bit)

CAN_CTL_SIE : Status Interrupt Enable
bits : 2 - 4 (3 bit)

CAN_CTL_EIE : Error Interrupt Enable
bits : 3 - 6 (4 bit)

CAN_CTL_DAR : Disable Automatic-Retransmission
bits : 5 - 10 (6 bit)

CAN_CTL_CCE : Configuration Change Enable
bits : 6 - 12 (7 bit)

CAN_CTL_TEST : Test Mode Enable
bits : 7 - 14 (8 bit)


CTL

CAN Control
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_CTL_INIT CAN_CTL_IE CAN_CTL_SIE CAN_CTL_EIE CAN_CTL_DAR CAN_CTL_CCE CAN_CTL_TEST

CAN_CTL_INIT : Initialization
bits : 0 - 0 (1 bit)

CAN_CTL_IE : CAN Interrupt Enable
bits : 1 - 2 (2 bit)

CAN_CTL_SIE : Status Interrupt Enable
bits : 2 - 4 (3 bit)

CAN_CTL_EIE : Error Interrupt Enable
bits : 3 - 6 (4 bit)

CAN_CTL_DAR : Disable Automatic-Retransmission
bits : 5 - 10 (6 bit)

CAN_CTL_CCE : Configuration Change Enable
bits : 6 - 12 (7 bit)

CAN_CTL_TEST : Test Mode Enable
bits : 7 - 14 (8 bit)


CAN0INT

CAN Interrupt
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0INT CAN0INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_INT_INTID

CAN_INT_INTID : Interrupt Identifier
bits : 0 - 15 (16 bit)

Enumeration:

0x0 : CAN_INT_INTID_NONE

No interrupt pending

0x8000 : CAN_INT_INTID_STATUS

Status Interrupt

End of enumeration elements list.


INT

CAN Interrupt
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_INT_INTID

CAN_INT_INTID : Interrupt Identifier
bits : 0 - 15 (16 bit)

Enumeration:

0x0 : CAN_INT_INTID_NONE

No interrupt pending

0x8000 : CAN_INT_INTID_STATUS

Status Interrupt

End of enumeration elements list.


CAN0TXRQ1

CAN Transmission Request 1
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0TXRQ1 CAN0TXRQ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_TXRQ1_TXRQST

CAN_TXRQ1_TXRQST : Transmission Request Bits
bits : 0 - 15 (16 bit)


TXRQ1

CAN Transmission Request 1
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXRQ1 TXRQ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_TXRQ1_TXRQST

CAN_TXRQ1_TXRQST : Transmission Request Bits
bits : 0 - 15 (16 bit)


CAN0TXRQ2

CAN Transmission Request 2
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0TXRQ2 CAN0TXRQ2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_TXRQ2_TXRQST

CAN_TXRQ2_TXRQST : Transmission Request Bits
bits : 0 - 15 (16 bit)


TXRQ2

CAN Transmission Request 2
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXRQ2 TXRQ2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_TXRQ2_TXRQST

CAN_TXRQ2_TXRQST : Transmission Request Bits
bits : 0 - 15 (16 bit)


CAN0NWDA1

CAN New Data 1
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0NWDA1 CAN0NWDA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_NWDA1_NEWDAT

CAN_NWDA1_NEWDAT : New Data Bits
bits : 0 - 15 (16 bit)


NWDA1

CAN New Data 1
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NWDA1 NWDA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_NWDA1_NEWDAT

CAN_NWDA1_NEWDAT : New Data Bits
bits : 0 - 15 (16 bit)


CAN0NWDA2

CAN New Data 2
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0NWDA2 CAN0NWDA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_NWDA2_NEWDAT

CAN_NWDA2_NEWDAT : New Data Bits
bits : 0 - 15 (16 bit)


NWDA2

CAN New Data 2
address_offset : 0x124 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NWDA2 NWDA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_NWDA2_NEWDAT

CAN_NWDA2_NEWDAT : New Data Bits
bits : 0 - 15 (16 bit)


CAN0TST

CAN Test
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0TST CAN0TST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_TST_BASIC CAN_TST_SILENT CAN_TST_LBACK CAN_TST_TX CAN_TST_RX

CAN_TST_BASIC : Basic Mode
bits : 2 - 4 (3 bit)

CAN_TST_SILENT : Silent Mode
bits : 3 - 6 (4 bit)

CAN_TST_LBACK : Loopback Mode
bits : 4 - 8 (5 bit)

CAN_TST_TX : Transmit Control
bits : 5 - 11 (7 bit)

Enumeration:

0x0 : CAN_TST_TX_CANCTL

CAN Module Control

0x1 : CAN_TST_TX_SAMPLE

Sample Point

0x2 : CAN_TST_TX_DOMINANT

Driven Low

0x3 : CAN_TST_TX_RECESSIVE

Driven High

End of enumeration elements list.

CAN_TST_RX : Receive Observation
bits : 7 - 14 (8 bit)


TST

CAN Test
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TST TST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_TST_BASIC CAN_TST_SILENT CAN_TST_LBACK CAN_TST_TX CAN_TST_RX

CAN_TST_BASIC : Basic Mode
bits : 2 - 4 (3 bit)

CAN_TST_SILENT : Silent Mode
bits : 3 - 6 (4 bit)

CAN_TST_LBACK : Loopback Mode
bits : 4 - 8 (5 bit)

CAN_TST_TX : Transmit Control
bits : 5 - 11 (7 bit)

Enumeration:

0x0 : CAN_TST_TX_CANCTL

CAN Module Control

0x1 : CAN_TST_TX_SAMPLE

Sample Point

0x2 : CAN_TST_TX_DOMINANT

Driven Low

0x3 : CAN_TST_TX_RECESSIVE

Driven High

End of enumeration elements list.

CAN_TST_RX : Receive Observation
bits : 7 - 14 (8 bit)


CAN0MSG1INT

CAN Message 1 Interrupt Pending
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0MSG1INT CAN0MSG1INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_MSG1INT_INTPND

CAN_MSG1INT_INTPND : Interrupt Pending Bits
bits : 0 - 15 (16 bit)


MSG1INT

CAN Message 1 Interrupt Pending
address_offset : 0x140 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSG1INT MSG1INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_MSG1INT_INTPND

CAN_MSG1INT_INTPND : Interrupt Pending Bits
bits : 0 - 15 (16 bit)


CAN0MSG2INT

CAN Message 2 Interrupt Pending
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0MSG2INT CAN0MSG2INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_MSG2INT_INTPND

CAN_MSG2INT_INTPND : Interrupt Pending Bits
bits : 0 - 15 (16 bit)


MSG2INT

CAN Message 2 Interrupt Pending
address_offset : 0x144 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSG2INT MSG2INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_MSG2INT_INTPND

CAN_MSG2INT_INTPND : Interrupt Pending Bits
bits : 0 - 15 (16 bit)


CAN0MSG1VAL

CAN Message 1 Valid
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0MSG1VAL CAN0MSG1VAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_MSG1VAL_MSGVAL

CAN_MSG1VAL_MSGVAL : Message Valid Bits
bits : 0 - 15 (16 bit)


MSG1VAL

CAN Message 1 Valid
address_offset : 0x160 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSG1VAL MSG1VAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_MSG1VAL_MSGVAL

CAN_MSG1VAL_MSGVAL : Message Valid Bits
bits : 0 - 15 (16 bit)


CAN0MSG2VAL

CAN Message 2 Valid
address_offset : 0x164 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0MSG2VAL CAN0MSG2VAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_MSG2VAL_MSGVAL

CAN_MSG2VAL_MSGVAL : Message Valid Bits
bits : 0 - 15 (16 bit)


MSG2VAL

CAN Message 2 Valid
address_offset : 0x164 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSG2VAL MSG2VAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_MSG2VAL_MSGVAL

CAN_MSG2VAL_MSGVAL : Message Valid Bits
bits : 0 - 15 (16 bit)


CAN0BRPE

CAN Baud Rate Prescaler Extension
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0BRPE CAN0BRPE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_BRPE_BRPE

CAN_BRPE_BRPE : Baud Rate Prescaler Extension
bits : 0 - 3 (4 bit)


BRPE

CAN Baud Rate Prescaler Extension
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRPE BRPE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_BRPE_BRPE

CAN_BRPE_BRPE : Baud Rate Prescaler Extension
bits : 0 - 3 (4 bit)


CAN0IF1CRQ

CAN IF1 Command Request
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF1CRQ CAN0IF1CRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1CRQ_MNUM CAN_IF1CRQ_BUSY

CAN_IF1CRQ_MNUM : Message Number
bits : 0 - 5 (6 bit)

CAN_IF1CRQ_BUSY : Busy Flag
bits : 15 - 30 (16 bit)


IF1CRQ

CAN IF1 Command Request
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1CRQ IF1CRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1CRQ_MNUM CAN_IF1CRQ_BUSY

CAN_IF1CRQ_MNUM : Message Number
bits : 0 - 5 (6 bit)

CAN_IF1CRQ_BUSY : Busy Flag
bits : 15 - 30 (16 bit)


CAN0IF1CMSK

CAN IF1 Command Mask
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF1CMSK CAN0IF1CMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1CMSK_DATAB CAN_IF1CMSK_DATAA CAN_IF1CMSK_NEWDAT CAN_IF1CMSK_CLRINTPND CAN_IF1CMSK_CONTROL CAN_IF1CMSK_ARB CAN_IF1CMSK_MASK CAN_IF1CMSK_WRNRD

CAN_IF1CMSK_DATAB : Access Data Byte 4 to 7
bits : 0 - 0 (1 bit)

CAN_IF1CMSK_DATAA : Access Data Byte 0 to 3
bits : 1 - 2 (2 bit)

CAN_IF1CMSK_NEWDAT : Access New Data
bits : 2 - 4 (3 bit)

CAN_IF1CMSK_CLRINTPND : Clear Interrupt Pending Bit
bits : 3 - 6 (4 bit)

CAN_IF1CMSK_CONTROL : Access Control Bits
bits : 4 - 8 (5 bit)

CAN_IF1CMSK_ARB : Access Arbitration Bits
bits : 5 - 10 (6 bit)

CAN_IF1CMSK_MASK : Access Mask Bits
bits : 6 - 12 (7 bit)

CAN_IF1CMSK_WRNRD : Write, Not Read
bits : 7 - 14 (8 bit)


IF1CMSK

CAN IF1 Command Mask
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1CMSK IF1CMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1CMSK_DATAB CAN_IF1CMSK_DATAA CAN_IF1CMSK_NEWDAT CAN_IF1CMSK_TXRQST CAN_IF1CMSK_CLRINTPND CAN_IF1CMSK_CONTROL CAN_IF1CMSK_ARB CAN_IF1CMSK_MASK CAN_IF1CMSK_WRNRD

CAN_IF1CMSK_DATAB : Access Data Byte 4 to 7
bits : 0 - 0 (1 bit)

CAN_IF1CMSK_DATAA : Access Data Byte 0 to 3
bits : 1 - 2 (2 bit)

CAN_IF1CMSK_NEWDAT : Access New Data
bits : 2 - 4 (3 bit)

CAN_IF1CMSK_TXRQST : Access Transmission Request
bits : 2 - 4 (3 bit)

CAN_IF1CMSK_CLRINTPND : Clear Interrupt Pending Bit
bits : 3 - 6 (4 bit)

CAN_IF1CMSK_CONTROL : Access Control Bits
bits : 4 - 8 (5 bit)

CAN_IF1CMSK_ARB : Access Arbitration Bits
bits : 5 - 10 (6 bit)

CAN_IF1CMSK_MASK : Access Mask Bits
bits : 6 - 12 (7 bit)

CAN_IF1CMSK_WRNRD : Write, Not Read
bits : 7 - 14 (8 bit)


CAN0IF1MSK1

CAN IF1 Mask 1
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF1MSK1 CAN0IF1MSK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1MSK1_IDMSK

CAN_IF1MSK1_IDMSK : Identifier Mask
bits : 0 - 15 (16 bit)


IF1MSK1

CAN IF1 Mask 1
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1MSK1 IF1MSK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1MSK1_IDMSK

CAN_IF1MSK1_IDMSK : Identifier Mask
bits : 0 - 15 (16 bit)


CAN0IF1MSK2

CAN IF1 Mask 2
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF1MSK2 CAN0IF1MSK2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1MSK2_IDMSK CAN_IF1MSK2_MDIR CAN_IF1MSK2_MXTD

CAN_IF1MSK2_IDMSK : Identifier Mask
bits : 0 - 12 (13 bit)

CAN_IF1MSK2_MDIR : Mask Message Direction
bits : 14 - 28 (15 bit)

CAN_IF1MSK2_MXTD : Mask Extended Identifier
bits : 15 - 30 (16 bit)


IF1MSK2

CAN IF1 Mask 2
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1MSK2 IF1MSK2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1MSK2_IDMSK CAN_IF1MSK2_MDIR CAN_IF1MSK2_MXTD

CAN_IF1MSK2_IDMSK : Identifier Mask
bits : 0 - 12 (13 bit)

CAN_IF1MSK2_MDIR : Mask Message Direction
bits : 14 - 28 (15 bit)

CAN_IF1MSK2_MXTD : Mask Extended Identifier
bits : 15 - 30 (16 bit)


CAN0IF1ARB1

CAN IF1 Arbitration 1
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF1ARB1 CAN0IF1ARB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1ARB1_ID

CAN_IF1ARB1_ID : Message Identifier
bits : 0 - 15 (16 bit)


IF1ARB1

CAN IF1 Arbitration 1
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1ARB1 IF1ARB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1ARB1_ID

CAN_IF1ARB1_ID : Message Identifier
bits : 0 - 15 (16 bit)


CAN0IF1ARB2

CAN IF1 Arbitration 2
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF1ARB2 CAN0IF1ARB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1ARB2_ID CAN_IF1ARB2_DIR CAN_IF1ARB2_XTD CAN_IF1ARB2_MSGVAL

CAN_IF1ARB2_ID : Message Identifier
bits : 0 - 12 (13 bit)

CAN_IF1ARB2_DIR : Message Direction
bits : 13 - 26 (14 bit)

CAN_IF1ARB2_XTD : Extended Identifier
bits : 14 - 28 (15 bit)

CAN_IF1ARB2_MSGVAL : Message Valid
bits : 15 - 30 (16 bit)


IF1ARB2

CAN IF1 Arbitration 2
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1ARB2 IF1ARB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1ARB2_ID CAN_IF1ARB2_DIR CAN_IF1ARB2_XTD CAN_IF1ARB2_MSGVAL

CAN_IF1ARB2_ID : Message Identifier
bits : 0 - 12 (13 bit)

CAN_IF1ARB2_DIR : Message Direction
bits : 13 - 26 (14 bit)

CAN_IF1ARB2_XTD : Extended Identifier
bits : 14 - 28 (15 bit)

CAN_IF1ARB2_MSGVAL : Message Valid
bits : 15 - 30 (16 bit)


CAN0IF1MCTL

CAN IF1 Message Control
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF1MCTL CAN0IF1MCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1MCTL_DLC CAN_IF1MCTL_EOB CAN_IF1MCTL_TXRQST CAN_IF1MCTL_RMTEN CAN_IF1MCTL_RXIE CAN_IF1MCTL_TXIE CAN_IF1MCTL_UMASK CAN_IF1MCTL_INTPND CAN_IF1MCTL_MSGLST CAN_IF1MCTL_NEWDAT

CAN_IF1MCTL_DLC : Data Length Code
bits : 0 - 3 (4 bit)

CAN_IF1MCTL_EOB : End of Buffer
bits : 7 - 14 (8 bit)

CAN_IF1MCTL_TXRQST : Transmit Request
bits : 8 - 16 (9 bit)

CAN_IF1MCTL_RMTEN : Remote Enable
bits : 9 - 18 (10 bit)

CAN_IF1MCTL_RXIE : Receive Interrupt Enable
bits : 10 - 20 (11 bit)

CAN_IF1MCTL_TXIE : Transmit Interrupt Enable
bits : 11 - 22 (12 bit)

CAN_IF1MCTL_UMASK : Use Acceptance Mask
bits : 12 - 24 (13 bit)

CAN_IF1MCTL_INTPND : Interrupt Pending
bits : 13 - 26 (14 bit)

CAN_IF1MCTL_MSGLST : Message Lost
bits : 14 - 28 (15 bit)

CAN_IF1MCTL_NEWDAT : New Data
bits : 15 - 30 (16 bit)


IF1MCTL

CAN IF1 Message Control
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1MCTL IF1MCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1MCTL_DLC CAN_IF1MCTL_EOB CAN_IF1MCTL_TXRQST CAN_IF1MCTL_RMTEN CAN_IF1MCTL_RXIE CAN_IF1MCTL_TXIE CAN_IF1MCTL_UMASK CAN_IF1MCTL_INTPND CAN_IF1MCTL_MSGLST CAN_IF1MCTL_NEWDAT

CAN_IF1MCTL_DLC : Data Length Code
bits : 0 - 3 (4 bit)

CAN_IF1MCTL_EOB : End of Buffer
bits : 7 - 14 (8 bit)

CAN_IF1MCTL_TXRQST : Transmit Request
bits : 8 - 16 (9 bit)

CAN_IF1MCTL_RMTEN : Remote Enable
bits : 9 - 18 (10 bit)

CAN_IF1MCTL_RXIE : Receive Interrupt Enable
bits : 10 - 20 (11 bit)

CAN_IF1MCTL_TXIE : Transmit Interrupt Enable
bits : 11 - 22 (12 bit)

CAN_IF1MCTL_UMASK : Use Acceptance Mask
bits : 12 - 24 (13 bit)

CAN_IF1MCTL_INTPND : Interrupt Pending
bits : 13 - 26 (14 bit)

CAN_IF1MCTL_MSGLST : Message Lost
bits : 14 - 28 (15 bit)

CAN_IF1MCTL_NEWDAT : New Data
bits : 15 - 30 (16 bit)


CAN0IF1DA1

CAN IF1 Data A1
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF1DA1 CAN0IF1DA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1DA1_DATA

CAN_IF1DA1_DATA : Data
bits : 0 - 15 (16 bit)


IF1DA1

CAN IF1 Data A1
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1DA1 IF1DA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1DA1_DATA

CAN_IF1DA1_DATA : Data
bits : 0 - 15 (16 bit)


CAN0STS

CAN Status
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0STS CAN0STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_STS_LEC CAN_STS_TXOK CAN_STS_RXOK CAN_STS_EPASS CAN_STS_EWARN CAN_STS_BOFF

CAN_STS_LEC : Last Error Code
bits : 0 - 2 (3 bit)

Enumeration:

0x0 : CAN_STS_LEC_NONE

No Error

0x1 : CAN_STS_LEC_STUFF

Stuff Error

0x2 : CAN_STS_LEC_FORM

Format Error

0x3 : CAN_STS_LEC_ACK

ACK Error

0x4 : CAN_STS_LEC_BIT1

Bit 1 Error

0x5 : CAN_STS_LEC_BIT0

Bit 0 Error

0x6 : CAN_STS_LEC_CRC

CRC Error

0x7 : CAN_STS_LEC_NOEVENT

No Event

End of enumeration elements list.

CAN_STS_TXOK : Transmitted a Message Successfully
bits : 3 - 6 (4 bit)

CAN_STS_RXOK : Received a Message Successfully
bits : 4 - 8 (5 bit)

CAN_STS_EPASS : Error Passive
bits : 5 - 10 (6 bit)

CAN_STS_EWARN : Warning Status
bits : 6 - 12 (7 bit)

CAN_STS_BOFF : Bus-Off Status
bits : 7 - 14 (8 bit)


STS

CAN Status
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STS STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_STS_LEC CAN_STS_TXOK CAN_STS_RXOK CAN_STS_EPASS CAN_STS_EWARN CAN_STS_BOFF

CAN_STS_LEC : Last Error Code
bits : 0 - 2 (3 bit)

Enumeration:

0x0 : CAN_STS_LEC_NONE

No Error

0x1 : CAN_STS_LEC_STUFF

Stuff Error

0x2 : CAN_STS_LEC_FORM

Format Error

0x3 : CAN_STS_LEC_ACK

ACK Error

0x4 : CAN_STS_LEC_BIT1

Bit 1 Error

0x5 : CAN_STS_LEC_BIT0

Bit 0 Error

0x6 : CAN_STS_LEC_CRC

CRC Error

0x7 : CAN_STS_LEC_NOEVENT

No Event

End of enumeration elements list.

CAN_STS_TXOK : Transmitted a Message Successfully
bits : 3 - 6 (4 bit)

CAN_STS_RXOK : Received a Message Successfully
bits : 4 - 8 (5 bit)

CAN_STS_EPASS : Error Passive
bits : 5 - 10 (6 bit)

CAN_STS_EWARN : Warning Status
bits : 6 - 12 (7 bit)

CAN_STS_BOFF : Bus-Off Status
bits : 7 - 14 (8 bit)


CAN0IF1DA2

CAN IF1 Data A2
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF1DA2 CAN0IF1DA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1DA2_DATA

CAN_IF1DA2_DATA : Data
bits : 0 - 15 (16 bit)


IF1DA2

CAN IF1 Data A2
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1DA2 IF1DA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1DA2_DATA

CAN_IF1DA2_DATA : Data
bits : 0 - 15 (16 bit)


CAN0IF1DB1

CAN IF1 Data B1
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF1DB1 CAN0IF1DB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1DB1_DATA

CAN_IF1DB1_DATA : Data
bits : 0 - 15 (16 bit)


IF1DB1

CAN IF1 Data B1
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1DB1 IF1DB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1DB1_DATA

CAN_IF1DB1_DATA : Data
bits : 0 - 15 (16 bit)


CAN0IF1DB2

CAN IF1 Data B2
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF1DB2 CAN0IF1DB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1DB2_DATA

CAN_IF1DB2_DATA : Data
bits : 0 - 15 (16 bit)


IF1DB2

CAN IF1 Data B2
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1DB2 IF1DB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF1DB2_DATA

CAN_IF1DB2_DATA : Data
bits : 0 - 15 (16 bit)


CAN0ERR

CAN Error Counter
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0ERR CAN0ERR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_ERR_TEC CAN_ERR_REC CAN_ERR_RP

CAN_ERR_TEC : Transmit Error Counter
bits : 0 - 7 (8 bit)

CAN_ERR_REC : Receive Error Counter
bits : 8 - 22 (15 bit)

CAN_ERR_RP : Received Error Passive
bits : 15 - 30 (16 bit)


ERR

CAN Error Counter
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERR ERR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_ERR_TEC CAN_ERR_REC CAN_ERR_RP

CAN_ERR_TEC : Transmit Error Counter
bits : 0 - 7 (8 bit)

CAN_ERR_REC : Receive Error Counter
bits : 8 - 22 (15 bit)

CAN_ERR_RP : Received Error Passive
bits : 15 - 30 (16 bit)


CAN0IF2CRQ

CAN IF2 Command Request
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF2CRQ CAN0IF2CRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2CRQ_MNUM CAN_IF2CRQ_BUSY

CAN_IF2CRQ_MNUM : Message Number
bits : 0 - 5 (6 bit)

CAN_IF2CRQ_BUSY : Busy Flag
bits : 15 - 30 (16 bit)


IF2CRQ

CAN IF2 Command Request
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2CRQ IF2CRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2CRQ_MNUM CAN_IF2CRQ_BUSY

CAN_IF2CRQ_MNUM : Message Number
bits : 0 - 5 (6 bit)

CAN_IF2CRQ_BUSY : Busy Flag
bits : 15 - 30 (16 bit)


CAN0IF2CMSK

CAN IF2 Command Mask
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF2CMSK CAN0IF2CMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2CMSK_DATAB CAN_IF2CMSK_DATAA CAN_IF2CMSK_NEWDAT CAN_IF2CMSK_CLRINTPND CAN_IF2CMSK_CONTROL CAN_IF2CMSK_ARB CAN_IF2CMSK_MASK CAN_IF2CMSK_WRNRD

CAN_IF2CMSK_DATAB : Access Data Byte 4 to 7
bits : 0 - 0 (1 bit)

CAN_IF2CMSK_DATAA : Access Data Byte 0 to 3
bits : 1 - 2 (2 bit)

CAN_IF2CMSK_NEWDAT : Access New Data
bits : 2 - 4 (3 bit)

CAN_IF2CMSK_CLRINTPND : Clear Interrupt Pending Bit
bits : 3 - 6 (4 bit)

CAN_IF2CMSK_CONTROL : Access Control Bits
bits : 4 - 8 (5 bit)

CAN_IF2CMSK_ARB : Access Arbitration Bits
bits : 5 - 10 (6 bit)

CAN_IF2CMSK_MASK : Access Mask Bits
bits : 6 - 12 (7 bit)

CAN_IF2CMSK_WRNRD : Write, Not Read
bits : 7 - 14 (8 bit)


IF2CMSK

CAN IF2 Command Mask
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2CMSK IF2CMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2CMSK_DATAB CAN_IF2CMSK_DATAA CAN_IF2CMSK_NEWDAT CAN_IF2CMSK_TXRQST CAN_IF2CMSK_CLRINTPND CAN_IF2CMSK_CONTROL CAN_IF2CMSK_ARB CAN_IF2CMSK_MASK CAN_IF2CMSK_WRNRD

CAN_IF2CMSK_DATAB : Access Data Byte 4 to 7
bits : 0 - 0 (1 bit)

CAN_IF2CMSK_DATAA : Access Data Byte 0 to 3
bits : 1 - 2 (2 bit)

CAN_IF2CMSK_NEWDAT : Access New Data
bits : 2 - 4 (3 bit)

CAN_IF2CMSK_TXRQST : Access Transmission Request
bits : 2 - 4 (3 bit)

CAN_IF2CMSK_CLRINTPND : Clear Interrupt Pending Bit
bits : 3 - 6 (4 bit)

CAN_IF2CMSK_CONTROL : Access Control Bits
bits : 4 - 8 (5 bit)

CAN_IF2CMSK_ARB : Access Arbitration Bits
bits : 5 - 10 (6 bit)

CAN_IF2CMSK_MASK : Access Mask Bits
bits : 6 - 12 (7 bit)

CAN_IF2CMSK_WRNRD : Write, Not Read
bits : 7 - 14 (8 bit)


CAN0IF2MSK1

CAN IF2 Mask 1
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF2MSK1 CAN0IF2MSK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2MSK1_IDMSK

CAN_IF2MSK1_IDMSK : Identifier Mask
bits : 0 - 15 (16 bit)


IF2MSK1

CAN IF2 Mask 1
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2MSK1 IF2MSK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2MSK1_IDMSK

CAN_IF2MSK1_IDMSK : Identifier Mask
bits : 0 - 15 (16 bit)


CAN0IF2MSK2

CAN IF2 Mask 2
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF2MSK2 CAN0IF2MSK2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2MSK2_IDMSK CAN_IF2MSK2_MDIR CAN_IF2MSK2_MXTD

CAN_IF2MSK2_IDMSK : Identifier Mask
bits : 0 - 12 (13 bit)

CAN_IF2MSK2_MDIR : Mask Message Direction
bits : 14 - 28 (15 bit)

CAN_IF2MSK2_MXTD : Mask Extended Identifier
bits : 15 - 30 (16 bit)


IF2MSK2

CAN IF2 Mask 2
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2MSK2 IF2MSK2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2MSK2_IDMSK CAN_IF2MSK2_MDIR CAN_IF2MSK2_MXTD

CAN_IF2MSK2_IDMSK : Identifier Mask
bits : 0 - 12 (13 bit)

CAN_IF2MSK2_MDIR : Mask Message Direction
bits : 14 - 28 (15 bit)

CAN_IF2MSK2_MXTD : Mask Extended Identifier
bits : 15 - 30 (16 bit)


CAN0IF2ARB1

CAN IF2 Arbitration 1
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF2ARB1 CAN0IF2ARB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2ARB1_ID

CAN_IF2ARB1_ID : Message Identifier
bits : 0 - 15 (16 bit)


IF2ARB1

CAN IF2 Arbitration 1
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2ARB1 IF2ARB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2ARB1_ID

CAN_IF2ARB1_ID : Message Identifier
bits : 0 - 15 (16 bit)


CAN0IF2ARB2

CAN IF2 Arbitration 2
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF2ARB2 CAN0IF2ARB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2ARB2_ID CAN_IF2ARB2_DIR CAN_IF2ARB2_XTD CAN_IF2ARB2_MSGVAL

CAN_IF2ARB2_ID : Message Identifier
bits : 0 - 12 (13 bit)

CAN_IF2ARB2_DIR : Message Direction
bits : 13 - 26 (14 bit)

CAN_IF2ARB2_XTD : Extended Identifier
bits : 14 - 28 (15 bit)

CAN_IF2ARB2_MSGVAL : Message Valid
bits : 15 - 30 (16 bit)


IF2ARB2

CAN IF2 Arbitration 2
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2ARB2 IF2ARB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2ARB2_ID CAN_IF2ARB2_DIR CAN_IF2ARB2_XTD CAN_IF2ARB2_MSGVAL

CAN_IF2ARB2_ID : Message Identifier
bits : 0 - 12 (13 bit)

CAN_IF2ARB2_DIR : Message Direction
bits : 13 - 26 (14 bit)

CAN_IF2ARB2_XTD : Extended Identifier
bits : 14 - 28 (15 bit)

CAN_IF2ARB2_MSGVAL : Message Valid
bits : 15 - 30 (16 bit)


CAN0IF2MCTL

CAN IF2 Message Control
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF2MCTL CAN0IF2MCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2MCTL_DLC CAN_IF2MCTL_EOB CAN_IF2MCTL_TXRQST CAN_IF2MCTL_RMTEN CAN_IF2MCTL_RXIE CAN_IF2MCTL_TXIE CAN_IF2MCTL_UMASK CAN_IF2MCTL_INTPND CAN_IF2MCTL_MSGLST CAN_IF2MCTL_NEWDAT

CAN_IF2MCTL_DLC : Data Length Code
bits : 0 - 3 (4 bit)

CAN_IF2MCTL_EOB : End of Buffer
bits : 7 - 14 (8 bit)

CAN_IF2MCTL_TXRQST : Transmit Request
bits : 8 - 16 (9 bit)

CAN_IF2MCTL_RMTEN : Remote Enable
bits : 9 - 18 (10 bit)

CAN_IF2MCTL_RXIE : Receive Interrupt Enable
bits : 10 - 20 (11 bit)

CAN_IF2MCTL_TXIE : Transmit Interrupt Enable
bits : 11 - 22 (12 bit)

CAN_IF2MCTL_UMASK : Use Acceptance Mask
bits : 12 - 24 (13 bit)

CAN_IF2MCTL_INTPND : Interrupt Pending
bits : 13 - 26 (14 bit)

CAN_IF2MCTL_MSGLST : Message Lost
bits : 14 - 28 (15 bit)

CAN_IF2MCTL_NEWDAT : New Data
bits : 15 - 30 (16 bit)


IF2MCTL

CAN IF2 Message Control
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2MCTL IF2MCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2MCTL_DLC CAN_IF2MCTL_EOB CAN_IF2MCTL_TXRQST CAN_IF2MCTL_RMTEN CAN_IF2MCTL_RXIE CAN_IF2MCTL_TXIE CAN_IF2MCTL_UMASK CAN_IF2MCTL_INTPND CAN_IF2MCTL_MSGLST CAN_IF2MCTL_NEWDAT

CAN_IF2MCTL_DLC : Data Length Code
bits : 0 - 3 (4 bit)

CAN_IF2MCTL_EOB : End of Buffer
bits : 7 - 14 (8 bit)

CAN_IF2MCTL_TXRQST : Transmit Request
bits : 8 - 16 (9 bit)

CAN_IF2MCTL_RMTEN : Remote Enable
bits : 9 - 18 (10 bit)

CAN_IF2MCTL_RXIE : Receive Interrupt Enable
bits : 10 - 20 (11 bit)

CAN_IF2MCTL_TXIE : Transmit Interrupt Enable
bits : 11 - 22 (12 bit)

CAN_IF2MCTL_UMASK : Use Acceptance Mask
bits : 12 - 24 (13 bit)

CAN_IF2MCTL_INTPND : Interrupt Pending
bits : 13 - 26 (14 bit)

CAN_IF2MCTL_MSGLST : Message Lost
bits : 14 - 28 (15 bit)

CAN_IF2MCTL_NEWDAT : New Data
bits : 15 - 30 (16 bit)


CAN0IF2DA1

CAN IF2 Data A1
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF2DA1 CAN0IF2DA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2DA1_DATA

CAN_IF2DA1_DATA : Data
bits : 0 - 15 (16 bit)


IF2DA1

CAN IF2 Data A1
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2DA1 IF2DA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2DA1_DATA

CAN_IF2DA1_DATA : Data
bits : 0 - 15 (16 bit)


CAN0IF2DA2

CAN IF2 Data A2
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF2DA2 CAN0IF2DA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2DA2_DATA

CAN_IF2DA2_DATA : Data
bits : 0 - 15 (16 bit)


IF2DA2

CAN IF2 Data A2
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2DA2 IF2DA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2DA2_DATA

CAN_IF2DA2_DATA : Data
bits : 0 - 15 (16 bit)


CAN0IF2DB1

CAN IF2 Data B1
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF2DB1 CAN0IF2DB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2DB1_DATA

CAN_IF2DB1_DATA : Data
bits : 0 - 15 (16 bit)


IF2DB1

CAN IF2 Data B1
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2DB1 IF2DB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2DB1_DATA

CAN_IF2DB1_DATA : Data
bits : 0 - 15 (16 bit)


CAN0IF2DB2

CAN IF2 Data B2
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0IF2DB2 CAN0IF2DB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2DB2_DATA

CAN_IF2DB2_DATA : Data
bits : 0 - 15 (16 bit)


IF2DB2

CAN IF2 Data B2
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF2DB2 IF2DB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_IF2DB2_DATA

CAN_IF2DB2_DATA : Data
bits : 0 - 15 (16 bit)


CAN0BIT

CAN Bit Timing
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN0BIT CAN0BIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_BIT_BRP CAN_BIT_SJW CAN_BIT_TSEG1 CAN_BIT_TSEG2

CAN_BIT_BRP : Baud Rate Prescaler
bits : 0 - 5 (6 bit)

CAN_BIT_SJW : (Re)Synchronization Jump Width
bits : 6 - 13 (8 bit)

CAN_BIT_TSEG1 : Time Segment Before Sample Point
bits : 8 - 19 (12 bit)

CAN_BIT_TSEG2 : Time Segment after Sample Point
bits : 12 - 26 (15 bit)


BIT

CAN Bit Timing
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BIT BIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_BIT_BRP CAN_BIT_SJW CAN_BIT_TSEG1 CAN_BIT_TSEG2

CAN_BIT_BRP : Baud Rate Prescaler
bits : 0 - 5 (6 bit)

CAN_BIT_SJW : (Re)Synchronization Jump Width
bits : 6 - 13 (8 bit)

CAN_BIT_TSEG1 : Time Segment Before Sample Point
bits : 8 - 19 (12 bit)

CAN_BIT_TSEG2 : Time Segment after Sample Point
bits : 12 - 26 (15 bit)



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