Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
PWM Master Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_CTL_GLOBALSYNC0 : Update PWM Generator 0
bits : 0 - 0 (1 bit)
PWM_CTL_GLOBALSYNC1 : Update PWM Generator 1
bits : 1 - 2 (2 bit)
PWM_CTL_GLOBALSYNC2 : Update PWM Generator 2
bits : 2 - 4 (3 bit)
PWM_CTL_GLOBALSYNC3 : Update PWM Generator 3
bits : 3 - 6 (4 bit)
PWM Master Control
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_CTL_GLOBALSYNC0 : Update PWM Generator 0
bits : 0 - 0 (1 bit)
PWM_CTL_GLOBALSYNC1 : Update PWM Generator 1
bits : 1 - 2 (2 bit)
PWM_CTL_GLOBALSYNC2 : Update PWM Generator 2
bits : 2 - 4 (3 bit)
PWM_CTL_GLOBALSYNC3 : Update PWM Generator 3
bits : 3 - 6 (4 bit)
PWM Output Fault
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_FAULT_FAULT0 : PWM0 Fault
bits : 0 - 0 (1 bit)
PWM_FAULT_FAULT1 : PWM1 Fault
bits : 1 - 2 (2 bit)
PWM_FAULT_FAULT2 : PWM2 Fault
bits : 2 - 4 (3 bit)
PWM_FAULT_FAULT3 : PWM3 Fault
bits : 3 - 6 (4 bit)
PWM_FAULT_FAULT4 : PWM4 Fault
bits : 4 - 8 (5 bit)
PWM_FAULT_FAULT5 : PWM5 Fault
bits : 5 - 10 (6 bit)
PWM_FAULT_FAULT6 : PWM6 Fault
bits : 6 - 12 (7 bit)
PWM_FAULT_FAULT7 : PWM7 Fault
bits : 7 - 14 (8 bit)
PWM Output Fault
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_FAULT_FAULT0 : PWM0 Fault
bits : 0 - 0 (1 bit)
PWM_FAULT_FAULT1 : PWM1 Fault
bits : 1 - 2 (2 bit)
PWM_FAULT_FAULT2 : PWM2 Fault
bits : 2 - 4 (3 bit)
PWM_FAULT_FAULT3 : PWM3 Fault
bits : 3 - 6 (4 bit)
PWM_FAULT_FAULT4 : PWM4 Fault
bits : 4 - 8 (5 bit)
PWM_FAULT_FAULT5 : PWM5 Fault
bits : 5 - 10 (6 bit)
PWM_FAULT_FAULT6 : PWM6 Fault
bits : 6 - 12 (7 bit)
PWM_FAULT_FAULT7 : PWM7 Fault
bits : 7 - 14 (8 bit)
PWM3 Control
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Control
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Interrupt and Trigger Enable
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Interrupt and Trigger Enable
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Raw Interrupt Status
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Raw Interrupt Status
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Interrupt Status and Clear
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Interrupt Status and Clear
address_offset : 0x10C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Load
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Load
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Counter
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Counter
address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Compare A
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Compare A
address_offset : 0x118 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Compare B
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Compare B
address_offset : 0x11C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Generator A Control
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Generator A Control
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Generator B Control
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Generator B Control
address_offset : 0x124 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Dead-Band Control
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Dead-Band Control
address_offset : 0x128 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Dead-Band Rising-Edge Delay
address_offset : 0x12C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Dead-Band Rising-Edge Delay
address_offset : 0x12C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Dead-Band Falling-Edge-Delay
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Dead-Band Falling-Edge-Delay
address_offset : 0x130 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Fault Source 0
address_offset : 0x134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Fault Source 0
address_offset : 0x134 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Fault Source 1
address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Fault Source 1
address_offset : 0x138 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Minimum Fault Period
address_offset : 0x13C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Minimum Fault Period
address_offset : 0x13C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Interrupt Enable
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_INTEN_INTPWM0 : PWM0 Interrupt Enable
bits : 0 - 0 (1 bit)
PWM_INTEN_INTPWM1 : PWM1 Interrupt Enable
bits : 1 - 2 (2 bit)
PWM_INTEN_INTPWM2 : PWM2 Interrupt Enable
bits : 2 - 4 (3 bit)
PWM_INTEN_INTPWM3 : PWM3 Interrupt Enable
bits : 3 - 6 (4 bit)
PWM_INTEN_INTFAULT0 : Interrupt Fault 0
bits : 16 - 32 (17 bit)
PWM_INTEN_INTFAULT1 : Interrupt Fault 1
bits : 17 - 34 (18 bit)
PWM_INTEN_INTFAULT2 : Interrupt Fault 2
bits : 18 - 36 (19 bit)
PWM_INTEN_INTFAULT3 : Interrupt Fault 3
bits : 19 - 38 (20 bit)
PWM Interrupt Enable
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_INTEN_INTPWM0 : PWM0 Interrupt Enable
bits : 0 - 0 (1 bit)
PWM_INTEN_INTPWM1 : PWM1 Interrupt Enable
bits : 1 - 2 (2 bit)
PWM_INTEN_INTPWM2 : PWM2 Interrupt Enable
bits : 2 - 4 (3 bit)
PWM_INTEN_INTPWM3 : PWM3 Interrupt Enable
bits : 3 - 6 (4 bit)
PWM_INTEN_INTFAULT0 : Interrupt Fault 0
bits : 16 - 32 (17 bit)
PWM_INTEN_INTFAULT1 : Interrupt Fault 1
bits : 17 - 34 (18 bit)
PWM_INTEN_INTFAULT2 : Interrupt Fault 2
bits : 18 - 36 (19 bit)
PWM_INTEN_INTFAULT3 : Interrupt Fault 3
bits : 19 - 38 (20 bit)
PWM Raw Interrupt Status
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_RIS_INTPWM0 : PWM0 Interrupt Asserted
bits : 0 - 0 (1 bit)
PWM_RIS_INTPWM1 : PWM1 Interrupt Asserted
bits : 1 - 2 (2 bit)
PWM_RIS_INTPWM2 : PWM2 Interrupt Asserted
bits : 2 - 4 (3 bit)
PWM_RIS_INTPWM3 : PWM3 Interrupt Asserted
bits : 3 - 6 (4 bit)
PWM_RIS_INTFAULT0 : Interrupt Fault PWM 0
bits : 16 - 32 (17 bit)
PWM_RIS_INTFAULT1 : Interrupt Fault PWM 1
bits : 17 - 34 (18 bit)
PWM_RIS_INTFAULT2 : Interrupt Fault PWM 2
bits : 18 - 36 (19 bit)
PWM_RIS_INTFAULT3 : Interrupt Fault PWM 3
bits : 19 - 38 (20 bit)
PWM Raw Interrupt Status
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_RIS_INTPWM0 : PWM0 Interrupt Asserted
bits : 0 - 0 (1 bit)
PWM_RIS_INTPWM1 : PWM1 Interrupt Asserted
bits : 1 - 2 (2 bit)
PWM_RIS_INTPWM2 : PWM2 Interrupt Asserted
bits : 2 - 4 (3 bit)
PWM_RIS_INTPWM3 : PWM3 Interrupt Asserted
bits : 3 - 6 (4 bit)
PWM_RIS_INTFAULT0 : Interrupt Fault PWM 0
bits : 16 - 32 (17 bit)
PWM_RIS_INTFAULT1 : Interrupt Fault PWM 1
bits : 17 - 34 (18 bit)
PWM_RIS_INTFAULT2 : Interrupt Fault PWM 2
bits : 18 - 36 (19 bit)
PWM_RIS_INTFAULT3 : Interrupt Fault PWM 3
bits : 19 - 38 (20 bit)
PWM Interrupt Status and Clear
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_ISC_INTPWM0 : PWM0 Interrupt Status
bits : 0 - 0 (1 bit)
PWM_ISC_INTPWM1 : PWM1 Interrupt Status
bits : 1 - 2 (2 bit)
PWM_ISC_INTPWM2 : PWM2 Interrupt Status
bits : 2 - 4 (3 bit)
PWM_ISC_INTPWM3 : PWM3 Interrupt Status
bits : 3 - 6 (4 bit)
PWM_ISC_INTFAULT0 : FAULT0 Interrupt Asserted
bits : 16 - 32 (17 bit)
PWM_ISC_INTFAULT1 : FAULT1 Interrupt Asserted
bits : 17 - 34 (18 bit)
PWM_ISC_INTFAULT2 : FAULT2 Interrupt Asserted
bits : 18 - 36 (19 bit)
PWM_ISC_INTFAULT3 : FAULT3 Interrupt Asserted
bits : 19 - 38 (20 bit)
PWM Interrupt Status and Clear
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_ISC_INTPWM0 : PWM0 Interrupt Status
bits : 0 - 0 (1 bit)
PWM_ISC_INTPWM1 : PWM1 Interrupt Status
bits : 1 - 2 (2 bit)
PWM_ISC_INTPWM2 : PWM2 Interrupt Status
bits : 2 - 4 (3 bit)
PWM_ISC_INTPWM3 : PWM3 Interrupt Status
bits : 3 - 6 (4 bit)
PWM_ISC_INTFAULT0 : FAULT0 Interrupt Asserted
bits : 16 - 32 (17 bit)
PWM_ISC_INTFAULT1 : FAULT1 Interrupt Asserted
bits : 17 - 34 (18 bit)
PWM_ISC_INTFAULT2 : FAULT2 Interrupt Asserted
bits : 18 - 36 (19 bit)
PWM_ISC_INTFAULT3 : FAULT3 Interrupt Asserted
bits : 19 - 38 (20 bit)
PWM Status
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_STATUS_FAULT0 : Generator 0 Fault Status
bits : 0 - 0 (1 bit)
PWM_STATUS_FAULT1 : Generator 1 Fault Status
bits : 1 - 2 (2 bit)
PWM_STATUS_FAULT2 : Generator 2 Fault Status
bits : 2 - 4 (3 bit)
PWM_STATUS_FAULT3 : Generator 3 Fault Status
bits : 3 - 6 (4 bit)
PWM Status
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_STATUS_FAULT0 : Generator 0 Fault Status
bits : 0 - 0 (1 bit)
PWM_STATUS_FAULT1 : Generator 1 Fault Status
bits : 1 - 2 (2 bit)
PWM_STATUS_FAULT2 : Generator 2 Fault Status
bits : 2 - 4 (3 bit)
PWM_STATUS_FAULT3 : Generator 3 Fault Status
bits : 3 - 6 (4 bit)
PWM Fault Condition Value
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_FAULTVAL_PWM0 : PWM0 Fault Value
bits : 0 - 0 (1 bit)
PWM_FAULTVAL_PWM1 : PWM1 Fault Value
bits : 1 - 2 (2 bit)
PWM_FAULTVAL_PWM2 : PWM2 Fault Value
bits : 2 - 4 (3 bit)
PWM_FAULTVAL_PWM3 : PWM3 Fault Value
bits : 3 - 6 (4 bit)
PWM_FAULTVAL_PWM4 : PWM4 Fault Value
bits : 4 - 8 (5 bit)
PWM_FAULTVAL_PWM5 : PWM5 Fault Value
bits : 5 - 10 (6 bit)
PWM_FAULTVAL_PWM6 : PWM6 Fault Value
bits : 6 - 12 (7 bit)
PWM_FAULTVAL_PWM7 : PWM7 Fault Value
bits : 7 - 14 (8 bit)
PWM Fault Condition Value
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_FAULTVAL_PWM0 : PWM0 Fault Value
bits : 0 - 0 (1 bit)
PWM_FAULTVAL_PWM1 : PWM1 Fault Value
bits : 1 - 2 (2 bit)
PWM_FAULTVAL_PWM2 : PWM2 Fault Value
bits : 2 - 4 (3 bit)
PWM_FAULTVAL_PWM3 : PWM3 Fault Value
bits : 3 - 6 (4 bit)
PWM_FAULTVAL_PWM4 : PWM4 Fault Value
bits : 4 - 8 (5 bit)
PWM_FAULTVAL_PWM5 : PWM5 Fault Value
bits : 5 - 10 (6 bit)
PWM_FAULTVAL_PWM6 : PWM6 Fault Value
bits : 6 - 12 (7 bit)
PWM_FAULTVAL_PWM7 : PWM7 Fault Value
bits : 7 - 14 (8 bit)
PWM Enable Update
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_ENUPD_ENUPD0 : PWM0 Enable Update Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : PWM_ENUPD_ENUPD0_IMM
Immediate
0x2 : PWM_ENUPD_ENUPD0_LSYNC
Locally Synchronized
0x3 : PWM_ENUPD_ENUPD0_GSYNC
Globally Synchronized
End of enumeration elements list.
PWM_ENUPD_ENUPD1 : PWM1 Enable Update Mode
bits : 2 - 5 (4 bit)
Enumeration:
0x0 : PWM_ENUPD_ENUPD1_IMM
Immediate
0x2 : PWM_ENUPD_ENUPD1_LSYNC
Locally Synchronized
0x3 : PWM_ENUPD_ENUPD1_GSYNC
Globally Synchronized
End of enumeration elements list.
PWM_ENUPD_ENUPD2 : PWM2 Enable Update Mode
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : PWM_ENUPD_ENUPD2_IMM
Immediate
0x2 : PWM_ENUPD_ENUPD2_LSYNC
Locally Synchronized
0x3 : PWM_ENUPD_ENUPD2_GSYNC
Globally Synchronized
End of enumeration elements list.
PWM_ENUPD_ENUPD3 : PWM3 Enable Update Mode
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : PWM_ENUPD_ENUPD3_IMM
Immediate
0x2 : PWM_ENUPD_ENUPD3_LSYNC
Locally Synchronized
0x3 : PWM_ENUPD_ENUPD3_GSYNC
Globally Synchronized
End of enumeration elements list.
PWM_ENUPD_ENUPD4 : PWM4 Enable Update Mode
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : PWM_ENUPD_ENUPD4_IMM
Immediate
0x2 : PWM_ENUPD_ENUPD4_LSYNC
Locally Synchronized
0x3 : PWM_ENUPD_ENUPD4_GSYNC
Globally Synchronized
End of enumeration elements list.
PWM_ENUPD_ENUPD5 : PWM5 Enable Update Mode
bits : 10 - 21 (12 bit)
Enumeration:
0x0 : PWM_ENUPD_ENUPD5_IMM
Immediate
0x2 : PWM_ENUPD_ENUPD5_LSYNC
Locally Synchronized
0x3 : PWM_ENUPD_ENUPD5_GSYNC
Globally Synchronized
End of enumeration elements list.
PWM_ENUPD_ENUPD6 : PWM6 Enable Update Mode
bits : 12 - 25 (14 bit)
Enumeration:
0x0 : PWM_ENUPD_ENUPD6_IMM
Immediate
0x2 : PWM_ENUPD_ENUPD6_LSYNC
Locally Synchronized
0x3 : PWM_ENUPD_ENUPD6_GSYNC
Globally Synchronized
End of enumeration elements list.
PWM_ENUPD_ENUPD7 : PWM7 Enable Update Mode
bits : 14 - 29 (16 bit)
Enumeration:
0x0 : PWM_ENUPD_ENUPD7_IMM
Immediate
0x2 : PWM_ENUPD_ENUPD7_LSYNC
Locally Synchronized
0x3 : PWM_ENUPD_ENUPD7_GSYNC
Globally Synchronized
End of enumeration elements list.
PWM Enable Update
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_ENUPD_ENUPD0 : PWM0 Enable Update Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : PWM_ENUPD_ENUPD0_IMM
Immediate
0x2 : PWM_ENUPD_ENUPD0_LSYNC
Locally Synchronized
0x3 : PWM_ENUPD_ENUPD0_GSYNC
Globally Synchronized
End of enumeration elements list.
PWM_ENUPD_ENUPD1 : PWM1 Enable Update Mode
bits : 2 - 5 (4 bit)
Enumeration:
0x0 : PWM_ENUPD_ENUPD1_IMM
Immediate
0x2 : PWM_ENUPD_ENUPD1_LSYNC
Locally Synchronized
0x3 : PWM_ENUPD_ENUPD1_GSYNC
Globally Synchronized
End of enumeration elements list.
PWM_ENUPD_ENUPD2 : PWM2 Enable Update Mode
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : PWM_ENUPD_ENUPD2_IMM
Immediate
0x2 : PWM_ENUPD_ENUPD2_LSYNC
Locally Synchronized
0x3 : PWM_ENUPD_ENUPD2_GSYNC
Globally Synchronized
End of enumeration elements list.
PWM_ENUPD_ENUPD3 : PWM3 Enable Update Mode
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : PWM_ENUPD_ENUPD3_IMM
Immediate
0x2 : PWM_ENUPD_ENUPD3_LSYNC
Locally Synchronized
0x3 : PWM_ENUPD_ENUPD3_GSYNC
Globally Synchronized
End of enumeration elements list.
PWM_ENUPD_ENUPD4 : PWM4 Enable Update Mode
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : PWM_ENUPD_ENUPD4_IMM
Immediate
0x2 : PWM_ENUPD_ENUPD4_LSYNC
Locally Synchronized
0x3 : PWM_ENUPD_ENUPD4_GSYNC
Globally Synchronized
End of enumeration elements list.
PWM_ENUPD_ENUPD5 : PWM5 Enable Update Mode
bits : 10 - 21 (12 bit)
Enumeration:
0x0 : PWM_ENUPD_ENUPD5_IMM
Immediate
0x2 : PWM_ENUPD_ENUPD5_LSYNC
Locally Synchronized
0x3 : PWM_ENUPD_ENUPD5_GSYNC
Globally Synchronized
End of enumeration elements list.
PWM_ENUPD_ENUPD6 : PWM6 Enable Update Mode
bits : 12 - 25 (14 bit)
Enumeration:
0x0 : PWM_ENUPD_ENUPD6_IMM
Immediate
0x2 : PWM_ENUPD_ENUPD6_LSYNC
Locally Synchronized
0x3 : PWM_ENUPD_ENUPD6_GSYNC
Globally Synchronized
End of enumeration elements list.
PWM_ENUPD_ENUPD7 : PWM7 Enable Update Mode
bits : 14 - 29 (16 bit)
Enumeration:
0x0 : PWM_ENUPD_ENUPD7_IMM
Immediate
0x2 : PWM_ENUPD_ENUPD7_LSYNC
Locally Synchronized
0x3 : PWM_ENUPD_ENUPD7_GSYNC
Globally Synchronized
End of enumeration elements list.
PWM Time Base Sync
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_SYNC_SYNC0 : Reset Generator 0 Counter
bits : 0 - 0 (1 bit)
PWM_SYNC_SYNC1 : Reset Generator 1 Counter
bits : 1 - 2 (2 bit)
PWM_SYNC_SYNC2 : Reset Generator 2 Counter
bits : 2 - 4 (3 bit)
PWM_SYNC_SYNC3 : Reset Generator 3 Counter
bits : 3 - 6 (4 bit)
PWM Time Base Sync
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_SYNC_SYNC0 : Reset Generator 0 Counter
bits : 0 - 0 (1 bit)
PWM_SYNC_SYNC1 : Reset Generator 1 Counter
bits : 1 - 2 (2 bit)
PWM_SYNC_SYNC2 : Reset Generator 2 Counter
bits : 2 - 4 (3 bit)
PWM_SYNC_SYNC3 : Reset Generator 3 Counter
bits : 3 - 6 (4 bit)
PWM0 Control
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_CTL_ENABLE : PWM Block Enable
bits : 0 - 0 (1 bit)
PWM_X_CTL_MODE : Counter Mode
bits : 1 - 2 (2 bit)
PWM_X_CTL_DEBUG : Debug Mode
bits : 2 - 4 (3 bit)
PWM_X_CTL_LOADUPD : Load Register Update Mode
bits : 3 - 6 (4 bit)
PWM_X_CTL_CMPAUPD : Comparator A Update Mode
bits : 4 - 8 (5 bit)
PWM_X_CTL_CMPBUPD : Comparator B Update Mode
bits : 5 - 10 (6 bit)
PWM_X_CTL_GENAUPD : PWMnGENA Update Mode
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : PWM_X_CTL_GENAUPD_I
Immediate
0x2 : PWM_X_CTL_GENAUPD_LS
Locally Synchronized
0x3 : PWM_X_CTL_GENAUPD_GS
Globally Synchronized
End of enumeration elements list.
PWM_X_CTL_GENBUPD : PWMnGENB Update Mode
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : PWM_X_CTL_GENBUPD_I
Immediate
0x2 : PWM_X_CTL_GENBUPD_LS
Locally Synchronized
0x3 : PWM_X_CTL_GENBUPD_GS
Globally Synchronized
End of enumeration elements list.
PWM_X_CTL_DBCTLUPD : PWMnDBCTL Update Mode
bits : 10 - 21 (12 bit)
Enumeration:
0x0 : PWM_X_CTL_DBCTLUPD_I
Immediate
0x2 : PWM_X_CTL_DBCTLUPD_LS
Locally Synchronized
0x3 : PWM_X_CTL_DBCTLUPD_GS
Globally Synchronized
End of enumeration elements list.
PWM_X_CTL_DBRISEUPD : PWMnDBRISE Update Mode
bits : 12 - 25 (14 bit)
Enumeration:
0x0 : PWM_X_CTL_DBRISEUPD_I
Immediate
0x2 : PWM_X_CTL_DBRISEUPD_LS
Locally Synchronized
0x3 : PWM_X_CTL_DBRISEUPD_GS
Globally Synchronized
End of enumeration elements list.
PWM_X_CTL_DBFALLUPD : PWMnDBFALL Update Mode
bits : 14 - 29 (16 bit)
Enumeration:
0x0 : PWM_X_CTL_DBFALLUPD_I
Immediate
0x2 : PWM_X_CTL_DBFALLUPD_LS
Locally Synchronized
0x3 : PWM_X_CTL_DBFALLUPD_GS
Globally Synchronized
End of enumeration elements list.
PWM_X_CTL_FLTSRC : Fault Condition Source
bits : 16 - 32 (17 bit)
PWM_X_CTL_MINFLTPER : Minimum Fault Period
bits : 17 - 34 (18 bit)
PWM_X_CTL_LATCH : Latch Fault Input
bits : 18 - 36 (19 bit)
PWM0 Control
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_CTL_ENABLE : PWM Block Enable
bits : 0 - 0 (1 bit)
PWM_X_CTL_MODE : Counter Mode
bits : 1 - 2 (2 bit)
PWM_X_CTL_DEBUG : Debug Mode
bits : 2 - 4 (3 bit)
PWM_X_CTL_LOADUPD : Load Register Update Mode
bits : 3 - 6 (4 bit)
PWM_X_CTL_CMPAUPD : Comparator A Update Mode
bits : 4 - 8 (5 bit)
PWM_X_CTL_CMPBUPD : Comparator B Update Mode
bits : 5 - 10 (6 bit)
PWM_X_CTL_GENAUPD : PWMnGENA Update Mode
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : PWM_X_CTL_GENAUPD_I
Immediate
0x2 : PWM_X_CTL_GENAUPD_LS
Locally Synchronized
0x3 : PWM_X_CTL_GENAUPD_GS
Globally Synchronized
End of enumeration elements list.
PWM_X_CTL_GENBUPD : PWMnGENB Update Mode
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : PWM_X_CTL_GENBUPD_I
Immediate
0x2 : PWM_X_CTL_GENBUPD_LS
Locally Synchronized
0x3 : PWM_X_CTL_GENBUPD_GS
Globally Synchronized
End of enumeration elements list.
PWM_X_CTL_DBCTLUPD : PWMnDBCTL Update Mode
bits : 10 - 21 (12 bit)
Enumeration:
0x0 : PWM_X_CTL_DBCTLUPD_I
Immediate
0x2 : PWM_X_CTL_DBCTLUPD_LS
Locally Synchronized
0x3 : PWM_X_CTL_DBCTLUPD_GS
Globally Synchronized
End of enumeration elements list.
PWM_X_CTL_DBRISEUPD : PWMnDBRISE Update Mode
bits : 12 - 25 (14 bit)
Enumeration:
0x0 : PWM_X_CTL_DBRISEUPD_I
Immediate
0x2 : PWM_X_CTL_DBRISEUPD_LS
Locally Synchronized
0x3 : PWM_X_CTL_DBRISEUPD_GS
Globally Synchronized
End of enumeration elements list.
PWM_X_CTL_DBFALLUPD : PWMnDBFALL Update Mode
bits : 14 - 29 (16 bit)
Enumeration:
0x0 : PWM_X_CTL_DBFALLUPD_I
Immediate
0x2 : PWM_X_CTL_DBFALLUPD_LS
Locally Synchronized
0x3 : PWM_X_CTL_DBFALLUPD_GS
Globally Synchronized
End of enumeration elements list.
PWM_X_CTL_FLTSRC : Fault Condition Source
bits : 16 - 32 (17 bit)
PWM_X_CTL_MINFLTPER : Minimum Fault Period
bits : 17 - 34 (18 bit)
PWM_X_CTL_LATCH : Latch Fault Input
bits : 18 - 36 (19 bit)
PWM0 Interrupt and Trigger Enable
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_INTEN_INTCNTZERO : Interrupt for Counter=0
bits : 0 - 0 (1 bit)
PWM_X_INTEN_INTCNTLOAD : Interrupt for Counter=PWMnLOAD
bits : 1 - 2 (2 bit)
PWM_X_INTEN_INTCMPAU : Interrupt for Counter=PWMnCMPA Up
bits : 2 - 4 (3 bit)
PWM_X_INTEN_INTCMPAD : Interrupt for Counter=PWMnCMPA Down
bits : 3 - 6 (4 bit)
PWM_X_INTEN_INTCMPBU : Interrupt for Counter=PWMnCMPB Up
bits : 4 - 8 (5 bit)
PWM_X_INTEN_INTCMPBD : Interrupt for Counter=PWMnCMPB Down
bits : 5 - 10 (6 bit)
PWM_X_INTEN_TRCNTZERO : Trigger for Counter=0
bits : 8 - 16 (9 bit)
PWM_X_INTEN_TRCNTLOAD : Trigger for Counter=PWMnLOAD
bits : 9 - 18 (10 bit)
PWM_X_INTEN_TRCMPAU : Trigger for Counter=PWMnCMPA Up
bits : 10 - 20 (11 bit)
PWM_X_INTEN_TRCMPAD : Trigger for Counter=PWMnCMPA Down
bits : 11 - 22 (12 bit)
PWM_X_INTEN_TRCMPBU : Trigger for Counter=PWMnCMPB Up
bits : 12 - 24 (13 bit)
PWM_X_INTEN_TRCMPBD : Trigger for Counter=PWMnCMPB Down
bits : 13 - 26 (14 bit)
PWM0 Interrupt and Trigger Enable
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_INTEN_INTCNTZERO : Interrupt for Counter=0
bits : 0 - 0 (1 bit)
PWM_X_INTEN_INTCNTLOAD : Interrupt for Counter=PWMnLOAD
bits : 1 - 2 (2 bit)
PWM_X_INTEN_INTCMPAU : Interrupt for Counter=PWMnCMPA Up
bits : 2 - 4 (3 bit)
PWM_X_INTEN_INTCMPAD : Interrupt for Counter=PWMnCMPA Down
bits : 3 - 6 (4 bit)
PWM_X_INTEN_INTCMPBU : Interrupt for Counter=PWMnCMPB Up
bits : 4 - 8 (5 bit)
PWM_X_INTEN_INTCMPBD : Interrupt for Counter=PWMnCMPB Down
bits : 5 - 10 (6 bit)
PWM_X_INTEN_TRCNTZERO : Trigger for Counter=0
bits : 8 - 16 (9 bit)
PWM_X_INTEN_TRCNTLOAD : Trigger for Counter=PWMnLOAD
bits : 9 - 18 (10 bit)
PWM_X_INTEN_TRCMPAU : Trigger for Counter=PWMnCMPA Up
bits : 10 - 20 (11 bit)
PWM_X_INTEN_TRCMPAD : Trigger for Counter=PWMnCMPA Down
bits : 11 - 22 (12 bit)
PWM_X_INTEN_TRCMPBU : Trigger for Counter=PWMnCMPB Up
bits : 12 - 24 (13 bit)
PWM_X_INTEN_TRCMPBD : Trigger for Counter=PWMnCMPB Down
bits : 13 - 26 (14 bit)
PWM0 Raw Interrupt Status
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_RIS_INTCNTZERO : Counter=0 Interrupt Status
bits : 0 - 0 (1 bit)
PWM_X_RIS_INTCNTLOAD : Counter=Load Interrupt Status
bits : 1 - 2 (2 bit)
PWM_X_RIS_INTCMPAU : Comparator A Up Interrupt Status
bits : 2 - 4 (3 bit)
PWM_X_RIS_INTCMPAD : Comparator A Down Interrupt Status
bits : 3 - 6 (4 bit)
PWM_X_RIS_INTCMPBU : Comparator B Up Interrupt Status
bits : 4 - 8 (5 bit)
PWM_X_RIS_INTCMPBD : Comparator B Down Interrupt Status
bits : 5 - 10 (6 bit)
PWM0 Raw Interrupt Status
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_RIS_INTCNTZERO : Counter=0 Interrupt Status
bits : 0 - 0 (1 bit)
PWM_X_RIS_INTCNTLOAD : Counter=Load Interrupt Status
bits : 1 - 2 (2 bit)
PWM_X_RIS_INTCMPAU : Comparator A Up Interrupt Status
bits : 2 - 4 (3 bit)
PWM_X_RIS_INTCMPAD : Comparator A Down Interrupt Status
bits : 3 - 6 (4 bit)
PWM_X_RIS_INTCMPBU : Comparator B Up Interrupt Status
bits : 4 - 8 (5 bit)
PWM_X_RIS_INTCMPBD : Comparator B Down Interrupt Status
bits : 5 - 10 (6 bit)
PWM0 Interrupt Status and Clear
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_ISC_INTCNTZERO : Counter=0 Interrupt
bits : 0 - 0 (1 bit)
PWM_X_ISC_INTCNTLOAD : Counter=Load Interrupt
bits : 1 - 2 (2 bit)
PWM_X_ISC_INTCMPAU : Comparator A Up Interrupt
bits : 2 - 4 (3 bit)
PWM_X_ISC_INTCMPAD : Comparator A Down Interrupt
bits : 3 - 6 (4 bit)
PWM_X_ISC_INTCMPBU : Comparator B Up Interrupt
bits : 4 - 8 (5 bit)
PWM_X_ISC_INTCMPBD : Comparator B Down Interrupt
bits : 5 - 10 (6 bit)
PWM0 Interrupt Status and Clear
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_ISC_INTCNTZERO : Counter=0 Interrupt
bits : 0 - 0 (1 bit)
PWM_X_ISC_INTCNTLOAD : Counter=Load Interrupt
bits : 1 - 2 (2 bit)
PWM_X_ISC_INTCMPAU : Comparator A Up Interrupt
bits : 2 - 4 (3 bit)
PWM_X_ISC_INTCMPAD : Comparator A Down Interrupt
bits : 3 - 6 (4 bit)
PWM_X_ISC_INTCMPBU : Comparator B Up Interrupt
bits : 4 - 8 (5 bit)
PWM_X_ISC_INTCMPBD : Comparator B Down Interrupt
bits : 5 - 10 (6 bit)
PWM0 Load
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_LOAD : Counter Load Value
bits : 0 - 15 (16 bit)
PWM0 Load
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_LOAD : Counter Load Value
bits : 0 - 15 (16 bit)
PWM0 Counter
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_COUNT : Counter Value
bits : 0 - 15 (16 bit)
PWM0 Counter
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_COUNT : Counter Value
bits : 0 - 15 (16 bit)
PWM0 Compare A
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_CMPA : Comparator A Value
bits : 0 - 15 (16 bit)
PWM0 Compare A
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_CMPA : Comparator A Value
bits : 0 - 15 (16 bit)
PWM0 Compare B
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_CMPB : Comparator B Value
bits : 0 - 15 (16 bit)
PWM0 Compare B
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_CMPB : Comparator B Value
bits : 0 - 15 (16 bit)
PWM0 Generator A Control
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_GENA_ACTZERO : Action for Counter=0
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTZERO_NONE
Do nothing
0x1 : PWM_X_GENA_ACTZERO_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTZERO_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTZERO_ONE
Drive pwmA High
End of enumeration elements list.
PWM_X_GENA_ACTLOAD : Action for Counter=LOAD
bits : 2 - 5 (4 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTLOAD_NONE
Do nothing
0x1 : PWM_X_GENA_ACTLOAD_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTLOAD_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTLOAD_ONE
Drive pwmA High
End of enumeration elements list.
PWM_X_GENA_ACTCMPAU : Action for Comparator A Up
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTCMPAU_NONE
Do nothing
0x1 : PWM_X_GENA_ACTCMPAU_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTCMPAU_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTCMPAU_ONE
Drive pwmA High
End of enumeration elements list.
PWM_X_GENA_ACTCMPAD : Action for Comparator A Down
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTCMPAD_NONE
Do nothing
0x1 : PWM_X_GENA_ACTCMPAD_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTCMPAD_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTCMPAD_ONE
Drive pwmA High
End of enumeration elements list.
PWM_X_GENA_ACTCMPBU : Action for Comparator B Up
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTCMPBU_NONE
Do nothing
0x1 : PWM_X_GENA_ACTCMPBU_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTCMPBU_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTCMPBU_ONE
Drive pwmA High
End of enumeration elements list.
PWM_X_GENA_ACTCMPBD : Action for Comparator B Down
bits : 10 - 21 (12 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTCMPBD_NONE
Do nothing
0x1 : PWM_X_GENA_ACTCMPBD_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTCMPBD_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTCMPBD_ONE
Drive pwmA High
End of enumeration elements list.
PWM0 Generator A Control
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_GENA_ACTZERO : Action for Counter=0
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTZERO_NONE
Do nothing
0x1 : PWM_X_GENA_ACTZERO_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTZERO_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTZERO_ONE
Drive pwmA High
End of enumeration elements list.
PWM_X_GENA_ACTLOAD : Action for Counter=LOAD
bits : 2 - 5 (4 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTLOAD_NONE
Do nothing
0x1 : PWM_X_GENA_ACTLOAD_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTLOAD_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTLOAD_ONE
Drive pwmA High
End of enumeration elements list.
PWM_X_GENA_ACTCMPAU : Action for Comparator A Up
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTCMPAU_NONE
Do nothing
0x1 : PWM_X_GENA_ACTCMPAU_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTCMPAU_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTCMPAU_ONE
Drive pwmA High
End of enumeration elements list.
PWM_X_GENA_ACTCMPAD : Action for Comparator A Down
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTCMPAD_NONE
Do nothing
0x1 : PWM_X_GENA_ACTCMPAD_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTCMPAD_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTCMPAD_ONE
Drive pwmA High
End of enumeration elements list.
PWM_X_GENA_ACTCMPBU : Action for Comparator B Up
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTCMPBU_NONE
Do nothing
0x1 : PWM_X_GENA_ACTCMPBU_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTCMPBU_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTCMPBU_ONE
Drive pwmA High
End of enumeration elements list.
PWM_X_GENA_ACTCMPBD : Action for Comparator B Down
bits : 10 - 21 (12 bit)
Enumeration:
0x0 : PWM_X_GENA_ACTCMPBD_NONE
Do nothing
0x1 : PWM_X_GENA_ACTCMPBD_INV
Invert pwmA
0x2 : PWM_X_GENA_ACTCMPBD_ZERO
Drive pwmA Low
0x3 : PWM_X_GENA_ACTCMPBD_ONE
Drive pwmA High
End of enumeration elements list.
PWM0 Generator B Control
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_GENB_ACTZERO : Action for Counter=0
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTZERO_NONE
Do nothing
0x1 : PWM_X_GENB_ACTZERO_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTZERO_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTZERO_ONE
Drive pwmB High
End of enumeration elements list.
PWM_X_GENB_ACTLOAD : Action for Counter=LOAD
bits : 2 - 5 (4 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTLOAD_NONE
Do nothing
0x1 : PWM_X_GENB_ACTLOAD_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTLOAD_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTLOAD_ONE
Drive pwmB High
End of enumeration elements list.
PWM_X_GENB_ACTCMPAU : Action for Comparator A Up
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTCMPAU_NONE
Do nothing
0x1 : PWM_X_GENB_ACTCMPAU_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTCMPAU_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTCMPAU_ONE
Drive pwmB High
End of enumeration elements list.
PWM_X_GENB_ACTCMPAD : Action for Comparator A Down
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTCMPAD_NONE
Do nothing
0x1 : PWM_X_GENB_ACTCMPAD_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTCMPAD_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTCMPAD_ONE
Drive pwmB High
End of enumeration elements list.
PWM_X_GENB_ACTCMPBU : Action for Comparator B Up
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTCMPBU_NONE
Do nothing
0x1 : PWM_X_GENB_ACTCMPBU_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTCMPBU_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTCMPBU_ONE
Drive pwmB High
End of enumeration elements list.
PWM_X_GENB_ACTCMPBD : Action for Comparator B Down
bits : 10 - 21 (12 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTCMPBD_NONE
Do nothing
0x1 : PWM_X_GENB_ACTCMPBD_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTCMPBD_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTCMPBD_ONE
Drive pwmB High
End of enumeration elements list.
PWM0 Generator B Control
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_GENB_ACTZERO : Action for Counter=0
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTZERO_NONE
Do nothing
0x1 : PWM_X_GENB_ACTZERO_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTZERO_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTZERO_ONE
Drive pwmB High
End of enumeration elements list.
PWM_X_GENB_ACTLOAD : Action for Counter=LOAD
bits : 2 - 5 (4 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTLOAD_NONE
Do nothing
0x1 : PWM_X_GENB_ACTLOAD_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTLOAD_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTLOAD_ONE
Drive pwmB High
End of enumeration elements list.
PWM_X_GENB_ACTCMPAU : Action for Comparator A Up
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTCMPAU_NONE
Do nothing
0x1 : PWM_X_GENB_ACTCMPAU_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTCMPAU_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTCMPAU_ONE
Drive pwmB High
End of enumeration elements list.
PWM_X_GENB_ACTCMPAD : Action for Comparator A Down
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTCMPAD_NONE
Do nothing
0x1 : PWM_X_GENB_ACTCMPAD_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTCMPAD_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTCMPAD_ONE
Drive pwmB High
End of enumeration elements list.
PWM_X_GENB_ACTCMPBU : Action for Comparator B Up
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTCMPBU_NONE
Do nothing
0x1 : PWM_X_GENB_ACTCMPBU_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTCMPBU_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTCMPBU_ONE
Drive pwmB High
End of enumeration elements list.
PWM_X_GENB_ACTCMPBD : Action for Comparator B Down
bits : 10 - 21 (12 bit)
Enumeration:
0x0 : PWM_X_GENB_ACTCMPBD_NONE
Do nothing
0x1 : PWM_X_GENB_ACTCMPBD_INV
Invert pwmB
0x2 : PWM_X_GENB_ACTCMPBD_ZERO
Drive pwmB Low
0x3 : PWM_X_GENB_ACTCMPBD_ONE
Drive pwmB High
End of enumeration elements list.
PWM0 Dead-Band Control
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_DBCTL_ENABLE : Dead-Band Generator Enable
bits : 0 - 0 (1 bit)
PWM0 Dead-Band Control
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_DBCTL_ENABLE : Dead-Band Generator Enable
bits : 0 - 0 (1 bit)
PWM0 Dead-Band Rising-Edge Delay
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_DBRISE_DELAY : Dead-Band Rise Delay
bits : 0 - 11 (12 bit)
PWM0 Dead-Band Rising-Edge Delay
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_DBRISE_DELAY : Dead-Band Rise Delay
bits : 0 - 11 (12 bit)
PWM0 Dead-Band Falling-Edge-Delay
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_DBFALL_DELAY : Dead-Band Fall Delay
bits : 0 - 11 (12 bit)
PWM0 Dead-Band Falling-Edge-Delay
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_DBFALL_DELAY : Dead-Band Fall Delay
bits : 0 - 11 (12 bit)
PWM0 Fault Source 0
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_FLTSRC0_FAULT0 : Fault0 Input
bits : 0 - 0 (1 bit)
PWM_X_FLTSRC0_FAULT1 : Fault1 Input
bits : 1 - 2 (2 bit)
PWM_X_FLTSRC0_FAULT2 : Fault2 Input
bits : 2 - 4 (3 bit)
PWM_X_FLTSRC0_FAULT3 : Fault3 Input
bits : 3 - 6 (4 bit)
PWM0 Fault Source 0
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_FLTSRC0_FAULT0 : Fault0 Input
bits : 0 - 0 (1 bit)
PWM_X_FLTSRC0_FAULT1 : Fault1 Input
bits : 1 - 2 (2 bit)
PWM_X_FLTSRC0_FAULT2 : Fault2 Input
bits : 2 - 4 (3 bit)
PWM_X_FLTSRC0_FAULT3 : Fault3 Input
bits : 3 - 6 (4 bit)
PWM0 Fault Source 1
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_FLTSRC1_DCMP0 : Digital Comparator 0
bits : 0 - 0 (1 bit)
PWM_X_FLTSRC1_DCMP1 : Digital Comparator 1
bits : 1 - 2 (2 bit)
PWM_X_FLTSRC1_DCMP2 : Digital Comparator 2
bits : 2 - 4 (3 bit)
PWM_X_FLTSRC1_DCMP3 : Digital Comparator 3
bits : 3 - 6 (4 bit)
PWM_X_FLTSRC1_DCMP4 : Digital Comparator 4
bits : 4 - 8 (5 bit)
PWM_X_FLTSRC1_DCMP5 : Digital Comparator 5
bits : 5 - 10 (6 bit)
PWM_X_FLTSRC1_DCMP6 : Digital Comparator 6
bits : 6 - 12 (7 bit)
PWM_X_FLTSRC1_DCMP7 : Digital Comparator 7
bits : 7 - 14 (8 bit)
PWM0 Fault Source 1
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_FLTSRC1_DCMP0 : Digital Comparator 0
bits : 0 - 0 (1 bit)
PWM_X_FLTSRC1_DCMP1 : Digital Comparator 1
bits : 1 - 2 (2 bit)
PWM_X_FLTSRC1_DCMP2 : Digital Comparator 2
bits : 2 - 4 (3 bit)
PWM_X_FLTSRC1_DCMP3 : Digital Comparator 3
bits : 3 - 6 (4 bit)
PWM_X_FLTSRC1_DCMP4 : Digital Comparator 4
bits : 4 - 8 (5 bit)
PWM_X_FLTSRC1_DCMP5 : Digital Comparator 5
bits : 5 - 10 (6 bit)
PWM_X_FLTSRC1_DCMP6 : Digital Comparator 6
bits : 6 - 12 (7 bit)
PWM_X_FLTSRC1_DCMP7 : Digital Comparator 7
bits : 7 - 14 (8 bit)
PWM0 Minimum Fault Period
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_MINFLTPER : Minimum Fault Period
bits : 0 - 15 (16 bit)
PWM0 Minimum Fault Period
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_MINFLTPER : Minimum Fault Period
bits : 0 - 15 (16 bit)
PWM Output Enable
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_ENABLE_PWM0EN : PWM0 Output Enable
bits : 0 - 0 (1 bit)
PWM_ENABLE_PWM1EN : PWM1 Output Enable
bits : 1 - 2 (2 bit)
PWM_ENABLE_PWM2EN : PWM2 Output Enable
bits : 2 - 4 (3 bit)
PWM_ENABLE_PWM3EN : PWM3 Output Enable
bits : 3 - 6 (4 bit)
PWM_ENABLE_PWM4EN : PWM4 Output Enable
bits : 4 - 8 (5 bit)
PWM_ENABLE_PWM5EN : PWM5 Output Enable
bits : 5 - 10 (6 bit)
PWM_ENABLE_PWM6EN : PWM6 Output Enable
bits : 6 - 12 (7 bit)
PWM_ENABLE_PWM7EN : PWM7 Output Enable
bits : 7 - 14 (8 bit)
PWM Output Enable
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_ENABLE_PWM0EN : PWM0 Output Enable
bits : 0 - 0 (1 bit)
PWM_ENABLE_PWM1EN : PWM1 Output Enable
bits : 1 - 2 (2 bit)
PWM_ENABLE_PWM2EN : PWM2 Output Enable
bits : 2 - 4 (3 bit)
PWM_ENABLE_PWM3EN : PWM3 Output Enable
bits : 3 - 6 (4 bit)
PWM_ENABLE_PWM4EN : PWM4 Output Enable
bits : 4 - 8 (5 bit)
PWM_ENABLE_PWM5EN : PWM5 Output Enable
bits : 5 - 10 (6 bit)
PWM_ENABLE_PWM6EN : PWM6 Output Enable
bits : 6 - 12 (7 bit)
PWM_ENABLE_PWM7EN : PWM7 Output Enable
bits : 7 - 14 (8 bit)
PWM1 Control
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Control
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM0 Fault Pin Logic Sense
address_offset : 0x800 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_FLTSEN_FAULT0 : Fault0 Sense
bits : 0 - 0 (1 bit)
PWM_X_FLTSEN_FAULT1 : Fault1 Sense
bits : 1 - 2 (2 bit)
PWM_X_FLTSEN_FAULT2 : Fault2 Sense
bits : 2 - 4 (3 bit)
PWM_X_FLTSEN_FAULT3 : Fault3 Sense
bits : 3 - 6 (4 bit)
PWM0 Fault Pin Logic Sense
address_offset : 0x800 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_X_FLTSEN_FAULT0 : Fault0 Sense
bits : 0 - 0 (1 bit)
PWM_X_FLTSEN_FAULT1 : Fault1 Sense
bits : 1 - 2 (2 bit)
PWM_X_FLTSEN_FAULT2 : Fault2 Sense
bits : 2 - 4 (3 bit)
PWM_X_FLTSEN_FAULT3 : Fault3 Sense
bits : 3 - 6 (4 bit)
PWM0 Fault Status 0
address_offset : 0x804 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM_X_FLTSTAT0_FAULT0 : Fault Input 0
bits : 0 - 0 (1 bit)
access : read-only
PWM_X_FLTSTAT0_FAULT1 : Fault Input 1
bits : 1 - 2 (2 bit)
access : read-only
PWM_X_FLTSTAT0_FAULT2 : Fault Input 2
bits : 2 - 4 (3 bit)
access : read-only
PWM_X_FLTSTAT0_FAULT3 : Fault Input 3
bits : 3 - 6 (4 bit)
access : read-only
PWM0 Fault Status 0
address_offset : 0x804 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM_X_FLTSTAT0_FAULT0 : Fault Input 0
bits : 0 - 0 (1 bit)
access : read-only
PWM_X_FLTSTAT0_FAULT1 : Fault Input 1
bits : 1 - 2 (2 bit)
access : read-only
PWM_X_FLTSTAT0_FAULT2 : Fault Input 2
bits : 2 - 4 (3 bit)
access : read-only
PWM_X_FLTSTAT0_FAULT3 : Fault Input 3
bits : 3 - 6 (4 bit)
access : read-only
PWM0 Fault Status 1
address_offset : 0x808 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM_X_FLTSTAT1_DCMP0 : Digital Comparator 0 Trigger
bits : 0 - 0 (1 bit)
access : read-only
PWM_X_FLTSTAT1_DCMP1 : Digital Comparator 1 Trigger
bits : 1 - 2 (2 bit)
access : read-only
PWM_X_FLTSTAT1_DCMP2 : Digital Comparator 2 Trigger
bits : 2 - 4 (3 bit)
access : read-only
PWM_X_FLTSTAT1_DCMP3 : Digital Comparator 3 Trigger
bits : 3 - 6 (4 bit)
access : read-only
PWM_X_FLTSTAT1_DCMP4 : Digital Comparator 4 Trigger
bits : 4 - 8 (5 bit)
access : read-only
PWM_X_FLTSTAT1_DCMP5 : Digital Comparator 5 Trigger
bits : 5 - 10 (6 bit)
access : read-only
PWM_X_FLTSTAT1_DCMP6 : Digital Comparator 6 Trigger
bits : 6 - 12 (7 bit)
access : read-only
PWM_X_FLTSTAT1_DCMP7 : Digital Comparator 7 Trigger
bits : 7 - 14 (8 bit)
access : read-only
PWM0 Fault Status 1
address_offset : 0x808 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM_X_FLTSTAT1_DCMP0 : Digital Comparator 0 Trigger
bits : 0 - 0 (1 bit)
access : read-only
PWM_X_FLTSTAT1_DCMP1 : Digital Comparator 1 Trigger
bits : 1 - 2 (2 bit)
access : read-only
PWM_X_FLTSTAT1_DCMP2 : Digital Comparator 2 Trigger
bits : 2 - 4 (3 bit)
access : read-only
PWM_X_FLTSTAT1_DCMP3 : Digital Comparator 3 Trigger
bits : 3 - 6 (4 bit)
access : read-only
PWM_X_FLTSTAT1_DCMP4 : Digital Comparator 4 Trigger
bits : 4 - 8 (5 bit)
access : read-only
PWM_X_FLTSTAT1_DCMP5 : Digital Comparator 5 Trigger
bits : 5 - 10 (6 bit)
access : read-only
PWM_X_FLTSTAT1_DCMP6 : Digital Comparator 6 Trigger
bits : 6 - 12 (7 bit)
access : read-only
PWM_X_FLTSTAT1_DCMP7 : Digital Comparator 7 Trigger
bits : 7 - 14 (8 bit)
access : read-only
PWM1 Interrupt and Trigger Enable
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Interrupt and Trigger Enable
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Raw Interrupt Status
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Raw Interrupt Status
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Fault Pin Logic Sense
address_offset : 0x880 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Fault Pin Logic Sense
address_offset : 0x880 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Fault Status 0
address_offset : 0x884 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM1 Fault Status 0
address_offset : 0x884 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM1 Fault Status 1
address_offset : 0x888 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM1 Fault Status 1
address_offset : 0x888 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM1 Interrupt Status and Clear
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Interrupt Status and Clear
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Load
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Load
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Fault Pin Logic Sense
address_offset : 0x900 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Fault Pin Logic Sense
address_offset : 0x900 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Fault Status 0
address_offset : 0x904 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM2 Fault Status 0
address_offset : 0x904 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM2 Fault Status 1
address_offset : 0x908 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM2 Fault Status 1
address_offset : 0x908 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM1 Counter
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Counter
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Compare A
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Compare A
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Fault Pin Logic Sense
address_offset : 0x980 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Fault Pin Logic Sense
address_offset : 0x980 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM3 Fault Status 0
address_offset : 0x984 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM3 Fault Status 0
address_offset : 0x984 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM3 Fault Status 1
address_offset : 0x988 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM3 Fault Status 1
address_offset : 0x988 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM1 Compare B
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Compare B
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Generator A Control
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Generator A Control
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Generator B Control
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Generator B Control
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Dead-Band Control
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Dead-Band Control
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Dead-Band Rising-Edge Delay
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Dead-Band Rising-Edge Delay
address_offset : 0xAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Dead-Band Falling-Edge-Delay
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Dead-Band Falling-Edge-Delay
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Fault Source 0
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Fault Source 0
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Fault Source 1
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Fault Source 1
address_offset : 0xB8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Minimum Fault Period
address_offset : 0xBC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM1 Minimum Fault Period
address_offset : 0xBC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Output Inversion
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_INVERT_PWM0INV : Invert PWM0 Signal
bits : 0 - 0 (1 bit)
PWM_INVERT_PWM1INV : Invert PWM1 Signal
bits : 1 - 2 (2 bit)
PWM_INVERT_PWM2INV : Invert PWM2 Signal
bits : 2 - 4 (3 bit)
PWM_INVERT_PWM3INV : Invert PWM3 Signal
bits : 3 - 6 (4 bit)
PWM_INVERT_PWM4INV : Invert PWM4 Signal
bits : 4 - 8 (5 bit)
PWM_INVERT_PWM5INV : Invert PWM5 Signal
bits : 5 - 10 (6 bit)
PWM_INVERT_PWM6INV : Invert PWM6 Signal
bits : 6 - 12 (7 bit)
PWM_INVERT_PWM7INV : Invert PWM7 Signal
bits : 7 - 14 (8 bit)
PWM Output Inversion
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_INVERT_PWM0INV : Invert PWM0 Signal
bits : 0 - 0 (1 bit)
PWM_INVERT_PWM1INV : Invert PWM1 Signal
bits : 1 - 2 (2 bit)
PWM_INVERT_PWM2INV : Invert PWM2 Signal
bits : 2 - 4 (3 bit)
PWM_INVERT_PWM3INV : Invert PWM3 Signal
bits : 3 - 6 (4 bit)
PWM_INVERT_PWM4INV : Invert PWM4 Signal
bits : 4 - 8 (5 bit)
PWM_INVERT_PWM5INV : Invert PWM5 Signal
bits : 5 - 10 (6 bit)
PWM_INVERT_PWM6INV : Invert PWM6 Signal
bits : 6 - 12 (7 bit)
PWM_INVERT_PWM7INV : Invert PWM7 Signal
bits : 7 - 14 (8 bit)
PWM2 Control
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Control
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Interrupt and Trigger Enable
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Interrupt and Trigger Enable
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Raw Interrupt Status
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Raw Interrupt Status
address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Interrupt Status and Clear
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Interrupt Status and Clear
address_offset : 0xCC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Load
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Load
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Counter
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Counter
address_offset : 0xD4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Compare A
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Compare A
address_offset : 0xD8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Compare B
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Compare B
address_offset : 0xDC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Generator A Control
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Generator A Control
address_offset : 0xE0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Generator B Control
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Generator B Control
address_offset : 0xE4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Dead-Band Control
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Dead-Band Control
address_offset : 0xE8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Dead-Band Rising-Edge Delay
address_offset : 0xEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Dead-Band Rising-Edge Delay
address_offset : 0xEC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Dead-Band Falling-Edge-Delay
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Dead-Band Falling-Edge-Delay
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Fault Source 0
address_offset : 0xF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Fault Source 0
address_offset : 0xF4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Fault Source 1
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Fault Source 1
address_offset : 0xF8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Minimum Fault Period
address_offset : 0xFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM2 Minimum Fault Period
address_offset : 0xFC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Peripheral Properties
address_offset : 0xFC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_PP_GCNT : Generators
bits : 0 - 3 (4 bit)
PWM_PP_FCNT : Fault Inputs
bits : 4 - 11 (8 bit)
PWM_PP_ESYNC : Extended Synchronization
bits : 8 - 16 (9 bit)
PWM_PP_EFAULT : Extended Fault
bits : 9 - 18 (10 bit)
PWM_PP_ONE : One-Shot Mode
bits : 10 - 20 (11 bit)
PWM Peripheral Properties
address_offset : 0xFC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_PP_GCNT : Generators
bits : 0 - 3 (4 bit)
PWM_PP_FCNT : Fault Inputs
bits : 4 - 11 (8 bit)
PWM_PP_ESYNC : Extended Synchronization
bits : 8 - 16 (9 bit)
PWM_PP_EFAULT : Extended Fault
bits : 9 - 18 (10 bit)
PWM_PP_ONE : One-Shot Mode
bits : 10 - 20 (11 bit)
PWM Peripheral Configuration
address_offset : 0xFC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_PC_PWMDIV : PWM Clock Divisor
bits : 0 - 7 (8 bit)
Enumeration:
0x0 : PWM_PC_PWMDIV_2
/2
0x1 : PWM_PC_PWMDIV_4
/4
0x2 : PWM_PC_PWMDIV_8
/8
0x3 : PWM_PC_PWMDIV_16
/16
0x4 : PWM_PC_PWMDIV_32
/32
0x7 : PWM_PC_PWMDIV_64
/64 (default)
End of enumeration elements list.
PWM_PC_USEOPWMDIV : Enable PWM Clock Divisor
bits : 8 - 16 (9 bit)
PWM Peripheral Configuration
address_offset : 0xFC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_PC_PWMDIV : PWM Clock Divisor
bits : 0 - 7 (8 bit)
Enumeration:
0x0 : PWM_PC_PWMDIV_2
/2
0x1 : PWM_PC_PWMDIV_4
/4
0x2 : PWM_PC_PWMDIV_8
/8
0x3 : PWM_PC_PWMDIV_16
/16
0x4 : PWM_PC_PWMDIV_32
/32
0x7 : PWM_PC_PWMDIV_64
/64 (default)
End of enumeration elements list.
PWM_PC_USEOPWMDIV : Enable PWM Clock Divisor
bits : 8 - 16 (9 bit)
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