\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
GPIO Data
address_offset : 0x3FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Data
address_offset : 0x3FC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Direction
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Direction
address_offset : 0x400 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Interrupt Sense
address_offset : 0x404 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Interrupt Sense
address_offset : 0x404 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Interrupt Both Edges
address_offset : 0x408 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Interrupt Both Edges
address_offset : 0x408 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Interrupt Event
address_offset : 0x40C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Interrupt Event
address_offset : 0x40C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Interrupt Mask
address_offset : 0x410 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_IM_GPIO : GPIO Interrupt Mask Enable
bits : 0 - 7 (8 bit)
GPIO_IM_DMAIME : GPIO uDMA Done Interrupt Mask Enable
bits : 8 - 16 (9 bit)
GPIO Interrupt Mask
address_offset : 0x410 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_IM_GPIO : GPIO Interrupt Mask Enable
bits : 0 - 7 (8 bit)
GPIO_IM_DMAIME : GPIO uDMA Done Interrupt Mask Enable
bits : 8 - 16 (9 bit)
GPIO Raw Interrupt Status
address_offset : 0x414 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_RIS_GPIO : GPIO Interrupt Raw Status
bits : 0 - 7 (8 bit)
GPIO_RIS_DMARIS : GPIO uDMA Done Interrupt Raw Status
bits : 8 - 16 (9 bit)
GPIO Raw Interrupt Status
address_offset : 0x414 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_RIS_GPIO : GPIO Interrupt Raw Status
bits : 0 - 7 (8 bit)
GPIO_RIS_DMARIS : GPIO uDMA Done Interrupt Raw Status
bits : 8 - 16 (9 bit)
GPIO Masked Interrupt Status
address_offset : 0x418 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_MIS_GPIO : GPIO Masked Interrupt Status
bits : 0 - 7 (8 bit)
GPIO_MIS_DMAMIS : GPIO uDMA Done Masked Interrupt Status
bits : 8 - 16 (9 bit)
GPIO Masked Interrupt Status
address_offset : 0x418 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_MIS_GPIO : GPIO Masked Interrupt Status
bits : 0 - 7 (8 bit)
GPIO_MIS_DMAMIS : GPIO uDMA Done Masked Interrupt Status
bits : 8 - 16 (9 bit)
GPIO Interrupt Clear
address_offset : 0x41C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
GPIO_ICR_GPIO : GPIO Interrupt Clear
bits : 0 - 7 (8 bit)
access : write-only
GPIO_ICR_DMAIC : GPIO uDMA Interrupt Clear
bits : 8 - 16 (9 bit)
access : write-only
GPIO Interrupt Clear
address_offset : 0x41C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
GPIO_ICR_GPIO : GPIO Interrupt Clear
bits : 0 - 7 (8 bit)
access : write-only
GPIO_ICR_DMAIC : GPIO uDMA Interrupt Clear
bits : 8 - 16 (9 bit)
access : write-only
GPIO Alternate Function Select
address_offset : 0x420 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Alternate Function Select
address_offset : 0x420 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO 2-mA Drive Select
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO 2-mA Drive Select
address_offset : 0x500 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO 4-mA Drive Select
address_offset : 0x504 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO 4-mA Drive Select
address_offset : 0x504 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO 8-mA Drive Select
address_offset : 0x508 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO 8-mA Drive Select
address_offset : 0x508 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Open Drain Select
address_offset : 0x50C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Open Drain Select
address_offset : 0x50C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Pull-Up Select
address_offset : 0x510 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Pull-Up Select
address_offset : 0x510 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Pull-Down Select
address_offset : 0x514 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Pull-Down Select
address_offset : 0x514 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Slew Rate Control Select
address_offset : 0x518 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Slew Rate Control Select
address_offset : 0x518 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Digital Enable
address_offset : 0x51C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Digital Enable
address_offset : 0x51C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Lock
address_offset : 0x520 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_LOCK : GPIO Lock
bits : 0 - 31 (32 bit)
Enumeration:
0x0 : GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x1 : GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x4c4f434b : GPIO_LOCK_KEY
Unlocks the GPIO_CR register
End of enumeration elements list.
GPIO Lock
address_offset : 0x520 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_LOCK : GPIO Lock
bits : 0 - 31 (32 bit)
Enumeration:
0x0 : GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x1 : GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x4c4f434b : GPIO_LOCK_KEY
Unlocks the GPIO_CR register
End of enumeration elements list.
GPIO Commit
address_offset : 0x524 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GPIO Commit
address_offset : 0x524 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GPIO Analog Mode Select
address_offset : 0x528 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Analog Mode Select
address_offset : 0x528 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port Control
address_offset : 0x52C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port Control
address_offset : 0x52C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO ADC Control
address_offset : 0x530 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO ADC Control
address_offset : 0x530 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO DMA Control
address_offset : 0x534 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO DMA Control
address_offset : 0x534 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Select Interrupt
address_offset : 0x538 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_SI_SUM : Summary Interrupt
bits : 0 - 0 (1 bit)
GPIO Select Interrupt
address_offset : 0x538 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_SI_SUM : Summary Interrupt
bits : 0 - 0 (1 bit)
GPIO 12-mA Drive Select
address_offset : 0x53C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_DR12R_DRV12 : Output Pad 12-mA Drive Enable
bits : 0 - 7 (8 bit)
Enumeration:
0x1 : GPIO_DR12R_DRV12_12MA
The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3
End of enumeration elements list.
GPIO 12-mA Drive Select
address_offset : 0x53C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_DR12R_DRV12 : Output Pad 12-mA Drive Enable
bits : 0 - 7 (8 bit)
Enumeration:
0x1 : GPIO_DR12R_DRV12_12MA
The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3
End of enumeration elements list.
GPIO Wake Pin Enable
address_offset : 0x540 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_WAKEPEN_WAKEP4 : P[4] Wake Enable
bits : 4 - 8 (5 bit)
GPIO Wake Pin Enable
address_offset : 0x540 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_WAKEPEN_WAKEP4 : P[4] Wake Enable
bits : 4 - 8 (5 bit)
GPIO Wake Level
address_offset : 0x544 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_WAKELVL_WAKELVL4 : P[4] Wake Level
bits : 4 - 8 (5 bit)
GPIO Wake Level
address_offset : 0x544 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_WAKELVL_WAKELVL4 : P[4] Wake Level
bits : 4 - 8 (5 bit)
GPIO Wake Status
address_offset : 0x548 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_WAKESTAT_STAT4 : P[4] Wake Status
bits : 4 - 8 (5 bit)
GPIO Wake Status
address_offset : 0x548 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_WAKESTAT_STAT4 : P[4] Wake Status
bits : 4 - 8 (5 bit)
GPIO Peripheral Property
address_offset : 0xFC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_PP_EDE : Extended Drive Enable
bits : 0 - 0 (1 bit)
GPIO Peripheral Property
address_offset : 0xFC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_PP_EDE : Extended Drive Enable
bits : 0 - 0 (1 bit)
GPIO Peripheral Configuration
address_offset : 0xFC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_PC_EDM0 : Extended Drive Mode Bit 0
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : GPIO_PC_EDM0_DISABLE
Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal
0x1 : GPIO_PC_EDM0_6MA
An additional 6 mA option is provided
0x3 : GPIO_PC_EDM0_PLUS2MA
A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA
End of enumeration elements list.
GPIO_PC_EDM1 : Extended Drive Mode Bit 1
bits : 2 - 5 (4 bit)
GPIO_PC_EDM2 : Extended Drive Mode Bit 2
bits : 4 - 9 (6 bit)
GPIO_PC_EDM3 : Extended Drive Mode Bit 3
bits : 6 - 13 (8 bit)
GPIO_PC_EDM4 : Extended Drive Mode Bit 4
bits : 8 - 17 (10 bit)
GPIO_PC_EDM5 : Extended Drive Mode Bit 5
bits : 10 - 21 (12 bit)
GPIO_PC_EDM6 : Extended Drive Mode Bit 6
bits : 12 - 25 (14 bit)
GPIO_PC_EDM7 : Extended Drive Mode Bit 7
bits : 14 - 29 (16 bit)
GPIO Peripheral Configuration
address_offset : 0xFC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_PC_EDM0 : Extended Drive Mode Bit 0
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : GPIO_PC_EDM0_DISABLE
Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal
0x1 : GPIO_PC_EDM0_6MA
An additional 6 mA option is provided
0x3 : GPIO_PC_EDM0_PLUS2MA
A 2 mA driver is always enabled setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA
End of enumeration elements list.
GPIO_PC_EDM1 : Extended Drive Mode Bit 1
bits : 2 - 5 (4 bit)
GPIO_PC_EDM2 : Extended Drive Mode Bit 2
bits : 4 - 9 (6 bit)
GPIO_PC_EDM3 : Extended Drive Mode Bit 3
bits : 6 - 13 (8 bit)
GPIO_PC_EDM4 : Extended Drive Mode Bit 4
bits : 8 - 17 (10 bit)
GPIO_PC_EDM5 : Extended Drive Mode Bit 5
bits : 10 - 21 (12 bit)
GPIO_PC_EDM6 : Extended Drive Mode Bit 6
bits : 12 - 25 (14 bit)
GPIO_PC_EDM7 : Extended Drive Mode Bit 7
bits : 14 - 29 (16 bit)
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