\n

GPIO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

GPIOA_AHBDATA

DATA

GPIOA_AHBDIR

DIR

GPIOA_AHBIS

IS

GPIOA_AHBIBE

IBE

GPIOA_AHBIEV

IEV

GPIOA_AHBIM

IM

GPIOA_AHBRIS

RIS

GPIOA_AHBMIS

MIS

GPIOA_AHBICR

ICR

GPIOA_AHBAFSEL

AFSEL

GPIOA_AHBDR2R

DR2R

GPIOA_AHBDR4R

DR4R

GPIOA_AHBDR8R

DR8R

GPIOA_AHBODR

ODR

GPIOA_AHBPUR

PUR

GPIOA_AHBPDR

PDR

GPIOA_AHBSLR

SLR

GPIOA_AHBDEN

DEN

GPIOA_AHBLOCK

LOCK

GPIOA_AHBCR

CR

GPIOA_AHBAMSEL

AMSEL

GPIOA_AHBPCTL

PCTL

GPIOA_AHBADCCTL

ADCCTL

GPIOA_AHBDMACTL

DMACTL

GPIOA_AHBSI

SI

GPIOA_AHBDR12R

DR12R

GPIOA_AHBWAKEPEN

WAKEPEN

GPIOA_AHBWAKELVL

WAKELVL

GPIOA_AHBWAKESTAT

WAKESTAT

GPIOA_AHBPP

PP

GPIOA_AHBPC

PC


GPIOA_AHBDATA

GPIO Data
address_offset : 0x3FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBDATA GPIOA_AHBDATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DATA

GPIO Data
address_offset : 0x3FC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOA_AHBDIR

GPIO Direction
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBDIR GPIOA_AHBDIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DIR

GPIO Direction
address_offset : 0x400 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIR DIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOA_AHBIS

GPIO Interrupt Sense
address_offset : 0x404 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBIS GPIOA_AHBIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IS

GPIO Interrupt Sense
address_offset : 0x404 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IS IS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOA_AHBIBE

GPIO Interrupt Both Edges
address_offset : 0x408 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBIBE GPIOA_AHBIBE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IBE

GPIO Interrupt Both Edges
address_offset : 0x408 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IBE IBE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOA_AHBIEV

GPIO Interrupt Event
address_offset : 0x40C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBIEV GPIOA_AHBIEV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IEV

GPIO Interrupt Event
address_offset : 0x40C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEV IEV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOA_AHBIM

GPIO Interrupt Mask
address_offset : 0x410 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBIM GPIOA_AHBIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_IM_GPIO GPIO_IM_DMAIME

GPIO_IM_GPIO : GPIO Interrupt Mask Enable
bits : 0 - 7 (8 bit)

GPIO_IM_DMAIME : GPIO uDMA Done Interrupt Mask Enable
bits : 8 - 16 (9 bit)


IM

GPIO Interrupt Mask
address_offset : 0x410 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IM IM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_IM_GPIO GPIO_IM_DMAIME

GPIO_IM_GPIO : GPIO Interrupt Mask Enable
bits : 0 - 7 (8 bit)

GPIO_IM_DMAIME : GPIO uDMA Done Interrupt Mask Enable
bits : 8 - 16 (9 bit)


GPIOA_AHBRIS

GPIO Raw Interrupt Status
address_offset : 0x414 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBRIS GPIOA_AHBRIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_RIS_GPIO GPIO_RIS_DMARIS

GPIO_RIS_GPIO : GPIO Interrupt Raw Status
bits : 0 - 7 (8 bit)

GPIO_RIS_DMARIS : GPIO uDMA Done Interrupt Raw Status
bits : 8 - 16 (9 bit)


RIS

GPIO Raw Interrupt Status
address_offset : 0x414 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_RIS_GPIO GPIO_RIS_DMARIS

GPIO_RIS_GPIO : GPIO Interrupt Raw Status
bits : 0 - 7 (8 bit)

GPIO_RIS_DMARIS : GPIO uDMA Done Interrupt Raw Status
bits : 8 - 16 (9 bit)


GPIOA_AHBMIS

GPIO Masked Interrupt Status
address_offset : 0x418 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBMIS GPIOA_AHBMIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_MIS_GPIO GPIO_MIS_DMAMIS

GPIO_MIS_GPIO : GPIO Masked Interrupt Status
bits : 0 - 7 (8 bit)

GPIO_MIS_DMAMIS : GPIO uDMA Done Masked Interrupt Status
bits : 8 - 16 (9 bit)


MIS

GPIO Masked Interrupt Status
address_offset : 0x418 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIS MIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_MIS_GPIO GPIO_MIS_DMAMIS

GPIO_MIS_GPIO : GPIO Masked Interrupt Status
bits : 0 - 7 (8 bit)

GPIO_MIS_DMAMIS : GPIO uDMA Done Masked Interrupt Status
bits : 8 - 16 (9 bit)


GPIOA_AHBICR

GPIO Interrupt Clear
address_offset : 0x41C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBICR GPIOA_AHBICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_ICR_GPIO GPIO_ICR_DMAIC

GPIO_ICR_GPIO : GPIO Interrupt Clear
bits : 0 - 7 (8 bit)
access : write-only

GPIO_ICR_DMAIC : GPIO uDMA Interrupt Clear
bits : 8 - 16 (9 bit)
access : write-only


ICR

GPIO Interrupt Clear
address_offset : 0x41C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICR ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_ICR_GPIO GPIO_ICR_DMAIC

GPIO_ICR_GPIO : GPIO Interrupt Clear
bits : 0 - 7 (8 bit)
access : write-only

GPIO_ICR_DMAIC : GPIO uDMA Interrupt Clear
bits : 8 - 16 (9 bit)
access : write-only


GPIOA_AHBAFSEL

GPIO Alternate Function Select
address_offset : 0x420 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBAFSEL GPIOA_AHBAFSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AFSEL

GPIO Alternate Function Select
address_offset : 0x420 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AFSEL AFSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOA_AHBDR2R

GPIO 2-mA Drive Select
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBDR2R GPIOA_AHBDR2R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DR2R

GPIO 2-mA Drive Select
address_offset : 0x500 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR2R DR2R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOA_AHBDR4R

GPIO 4-mA Drive Select
address_offset : 0x504 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBDR4R GPIOA_AHBDR4R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DR4R

GPIO 4-mA Drive Select
address_offset : 0x504 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR4R DR4R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOA_AHBDR8R

GPIO 8-mA Drive Select
address_offset : 0x508 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBDR8R GPIOA_AHBDR8R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DR8R

GPIO 8-mA Drive Select
address_offset : 0x508 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR8R DR8R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOA_AHBODR

GPIO Open Drain Select
address_offset : 0x50C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBODR GPIOA_AHBODR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ODR

GPIO Open Drain Select
address_offset : 0x50C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ODR ODR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOA_AHBPUR

GPIO Pull-Up Select
address_offset : 0x510 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBPUR GPIOA_AHBPUR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PUR

GPIO Pull-Up Select
address_offset : 0x510 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUR PUR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOA_AHBPDR

GPIO Pull-Down Select
address_offset : 0x514 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBPDR GPIOA_AHBPDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDR

GPIO Pull-Down Select
address_offset : 0x514 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDR PDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOA_AHBSLR

GPIO Slew Rate Control Select
address_offset : 0x518 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBSLR GPIOA_AHBSLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SLR

GPIO Slew Rate Control Select
address_offset : 0x518 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLR SLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOA_AHBDEN

GPIO Digital Enable
address_offset : 0x51C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBDEN GPIOA_AHBDEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DEN

GPIO Digital Enable
address_offset : 0x51C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEN DEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOA_AHBLOCK

GPIO Lock
address_offset : 0x520 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBLOCK GPIOA_AHBLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_LOCK

GPIO_LOCK : GPIO Lock
bits : 0 - 31 (32 bit)

Enumeration:

0x0 : GPIO_LOCK_UNLOCKED

The GPIOCR register is unlocked and may be modified

0x1 : GPIO_LOCK_LOCKED

The GPIOCR register is locked and may not be modified

0x4c4f434b : GPIO_LOCK_KEY

Unlocks the GPIO_CR register

End of enumeration elements list.


LOCK

GPIO Lock
address_offset : 0x520 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_LOCK

GPIO_LOCK : GPIO Lock
bits : 0 - 31 (32 bit)

Enumeration:

0x0 : GPIO_LOCK_UNLOCKED

The GPIOCR register is unlocked and may be modified

0x1 : GPIO_LOCK_LOCKED

The GPIOCR register is locked and may not be modified

0x4c4f434b : GPIO_LOCK_KEY

Unlocks the GPIO_CR register

End of enumeration elements list.


GPIOA_AHBCR

GPIO Commit
address_offset : 0x524 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBCR GPIOA_AHBCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CR

GPIO Commit
address_offset : 0x524 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CR CR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOA_AHBAMSEL

GPIO Analog Mode Select
address_offset : 0x528 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBAMSEL GPIOA_AHBAMSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AMSEL

GPIO Analog Mode Select
address_offset : 0x528 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMSEL AMSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOA_AHBPCTL

GPIO Port Control
address_offset : 0x52C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBPCTL GPIOA_AHBPCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PCTL

GPIO Port Control
address_offset : 0x52C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCTL PCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOA_AHBADCCTL

GPIO ADC Control
address_offset : 0x530 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBADCCTL GPIOA_AHBADCCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCCTL

GPIO ADC Control
address_offset : 0x530 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCCTL ADCCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOA_AHBDMACTL

GPIO DMA Control
address_offset : 0x534 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBDMACTL GPIOA_AHBDMACTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMACTL

GPIO DMA Control
address_offset : 0x534 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACTL DMACTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOA_AHBSI

GPIO Select Interrupt
address_offset : 0x538 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBSI GPIOA_AHBSI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_SI_SUM

GPIO_SI_SUM : Summary Interrupt
bits : 0 - 0 (1 bit)


SI

GPIO Select Interrupt
address_offset : 0x538 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SI SI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_SI_SUM

GPIO_SI_SUM : Summary Interrupt
bits : 0 - 0 (1 bit)


GPIOA_AHBDR12R

GPIO 12-mA Drive Select
address_offset : 0x53C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBDR12R GPIOA_AHBDR12R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_DR12R_DRV12

GPIO_DR12R_DRV12 : Output Pad 12-mA Drive Enable
bits : 0 - 7 (8 bit)

Enumeration:

0x1 : GPIO_DR12R_DRV12_12MA

The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3

End of enumeration elements list.


DR12R

GPIO 12-mA Drive Select
address_offset : 0x53C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR12R DR12R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_DR12R_DRV12

GPIO_DR12R_DRV12 : Output Pad 12-mA Drive Enable
bits : 0 - 7 (8 bit)

Enumeration:

0x1 : GPIO_DR12R_DRV12_12MA

The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3

End of enumeration elements list.


GPIOA_AHBWAKEPEN

GPIO Wake Pin Enable
address_offset : 0x540 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBWAKEPEN GPIOA_AHBWAKEPEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_WAKEPEN_WAKEP4

GPIO_WAKEPEN_WAKEP4 : P[4] Wake Enable
bits : 4 - 8 (5 bit)


WAKEPEN

GPIO Wake Pin Enable
address_offset : 0x540 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAKEPEN WAKEPEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_WAKEPEN_WAKEP4

GPIO_WAKEPEN_WAKEP4 : P[4] Wake Enable
bits : 4 - 8 (5 bit)


GPIOA_AHBWAKELVL

GPIO Wake Level
address_offset : 0x544 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBWAKELVL GPIOA_AHBWAKELVL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_WAKELVL_WAKELVL4

GPIO_WAKELVL_WAKELVL4 : P[4] Wake Level
bits : 4 - 8 (5 bit)


WAKELVL

GPIO Wake Level
address_offset : 0x544 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAKELVL WAKELVL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_WAKELVL_WAKELVL4

GPIO_WAKELVL_WAKELVL4 : P[4] Wake Level
bits : 4 - 8 (5 bit)


GPIOA_AHBWAKESTAT

GPIO Wake Status
address_offset : 0x548 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBWAKESTAT GPIOA_AHBWAKESTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_WAKESTAT_STAT4

GPIO_WAKESTAT_STAT4 : P[4] Wake Status
bits : 4 - 8 (5 bit)


WAKESTAT

GPIO Wake Status
address_offset : 0x548 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAKESTAT WAKESTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_WAKESTAT_STAT4

GPIO_WAKESTAT_STAT4 : P[4] Wake Status
bits : 4 - 8 (5 bit)


GPIOA_AHBPP

GPIO Peripheral Property
address_offset : 0xFC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBPP GPIOA_AHBPP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_PP_EDE

GPIO_PP_EDE : Extended Drive Enable
bits : 0 - 0 (1 bit)


PP

GPIO Peripheral Property
address_offset : 0xFC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PP PP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_PP_EDE

GPIO_PP_EDE : Extended Drive Enable
bits : 0 - 0 (1 bit)


GPIOA_AHBPC

GPIO Peripheral Configuration
address_offset : 0xFC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_AHBPC GPIOA_AHBPC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_PC_EDM0 GPIO_PC_EDM1 GPIO_PC_EDM2 GPIO_PC_EDM3 GPIO_PC_EDM4 GPIO_PC_EDM5 GPIO_PC_EDM6 GPIO_PC_EDM7

GPIO_PC_EDM0 : Extended Drive Mode Bit 0
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : GPIO_PC_EDM0_DISABLE

Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal

0x1 : GPIO_PC_EDM0_6MA

An additional 6 mA option is provided

0x3 : GPIO_PC_EDM0_PLUS2MA

A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA

End of enumeration elements list.

GPIO_PC_EDM1 : Extended Drive Mode Bit 1
bits : 2 - 5 (4 bit)

GPIO_PC_EDM2 : Extended Drive Mode Bit 2
bits : 4 - 9 (6 bit)

GPIO_PC_EDM3 : Extended Drive Mode Bit 3
bits : 6 - 13 (8 bit)

GPIO_PC_EDM4 : Extended Drive Mode Bit 4
bits : 8 - 17 (10 bit)

GPIO_PC_EDM5 : Extended Drive Mode Bit 5
bits : 10 - 21 (12 bit)

GPIO_PC_EDM6 : Extended Drive Mode Bit 6
bits : 12 - 25 (14 bit)

GPIO_PC_EDM7 : Extended Drive Mode Bit 7
bits : 14 - 29 (16 bit)


PC

GPIO Peripheral Configuration
address_offset : 0xFC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC PC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_PC_EDM0 GPIO_PC_EDM1 GPIO_PC_EDM2 GPIO_PC_EDM3 GPIO_PC_EDM4 GPIO_PC_EDM5 GPIO_PC_EDM6 GPIO_PC_EDM7

GPIO_PC_EDM0 : Extended Drive Mode Bit 0
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : GPIO_PC_EDM0_DISABLE

Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal

0x1 : GPIO_PC_EDM0_6MA

An additional 6 mA option is provided

0x3 : GPIO_PC_EDM0_PLUS2MA

A 2 mA driver is always enabled setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA

End of enumeration elements list.

GPIO_PC_EDM1 : Extended Drive Mode Bit 1
bits : 2 - 5 (4 bit)

GPIO_PC_EDM2 : Extended Drive Mode Bit 2
bits : 4 - 9 (6 bit)

GPIO_PC_EDM3 : Extended Drive Mode Bit 3
bits : 6 - 13 (8 bit)

GPIO_PC_EDM4 : Extended Drive Mode Bit 4
bits : 8 - 17 (10 bit)

GPIO_PC_EDM5 : Extended Drive Mode Bit 5
bits : 10 - 21 (12 bit)

GPIO_PC_EDM6 : Extended Drive Mode Bit 6
bits : 12 - 25 (14 bit)

GPIO_PC_EDM7 : Extended Drive Mode Bit 7
bits : 14 - 29 (16 bit)



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