Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Ethernet MAC Configuration
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_CFG_PRELEN : Preamble Length for Transmit Frames
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EMAC_CFG_PRELEN_7
7 bytes of preamble
0x1 : EMAC_CFG_PRELEN_5
5 bytes of preamble
0x2 : EMAC_CFG_PRELEN_3
3 bytes of preamble
End of enumeration elements list.
EMAC_CFG_RE : Receiver Enable
bits : 2 - 4 (3 bit)
EMAC_CFG_TE : Transmitter Enable
bits : 3 - 6 (4 bit)
EMAC_CFG_DC : Deferral Check
bits : 4 - 8 (5 bit)
EMAC_CFG_BL : Back-Off Limit
bits : 5 - 11 (7 bit)
Enumeration:
0x0 : EMAC_CFG_BL_1024
k = min (n,10)
0x1 : EMAC_CFG_BL_256
k = min (n,8)
0x2 : EMAC_CFG_BL_8
k = min (n,4)
0x3 : EMAC_CFG_BL_2
k = min (n,1)
End of enumeration elements list.
EMAC_CFG_ACS : Automatic Pad or CRC Stripping
bits : 7 - 14 (8 bit)
EMAC_CFG_DR : Disable Retry
bits : 9 - 18 (10 bit)
EMAC_CFG_IPC : Checksum Offload
bits : 10 - 20 (11 bit)
EMAC_CFG_DUPM : Duplex Mode
bits : 11 - 22 (12 bit)
EMAC_CFG_LOOPBM : Loopback Mode
bits : 12 - 24 (13 bit)
EMAC_CFG_DRO : Disable Receive Own
bits : 13 - 26 (14 bit)
EMAC_CFG_FES : Speed
bits : 14 - 28 (15 bit)
EMAC_CFG_PS : Port Select
bits : 15 - 30 (16 bit)
EMAC_CFG_DISCRS : Disable Carrier Sense During Transmission
bits : 16 - 32 (17 bit)
EMAC_CFG_IFG : Inter-Frame Gap (IFG)
bits : 17 - 36 (20 bit)
Enumeration:
0x0 : EMAC_CFG_IFG_96
96 bit times
0x1 : EMAC_CFG_IFG_88
88 bit times
0x2 : EMAC_CFG_IFG_80
80 bit times
0x3 : EMAC_CFG_IFG_72
72 bit times
0x4 : EMAC_CFG_IFG_64
64 bit times
0x5 : EMAC_CFG_IFG_56
56 bit times
0x6 : EMAC_CFG_IFG_48
48 bit times
0x7 : EMAC_CFG_IFG_40
40 bit times
End of enumeration elements list.
EMAC_CFG_JFEN : Jumbo Frame Enable
bits : 20 - 40 (21 bit)
EMAC_CFG_JD : Jabber Disable
bits : 22 - 44 (23 bit)
EMAC_CFG_WDDIS : Watchdog Disable
bits : 23 - 46 (24 bit)
EMAC_CFG_CST : CRC Stripping for Type Frames
bits : 25 - 50 (26 bit)
EMAC_CFG_TWOKPEN : IEEE 802
bits : 27 - 54 (28 bit)
Ethernet MAC Configuration
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_CFG_PRELEN : Preamble Length for Transmit Frames
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EMAC_CFG_PRELEN_7
7 bytes of preamble
0x1 : EMAC_CFG_PRELEN_5
5 bytes of preamble
0x2 : EMAC_CFG_PRELEN_3
3 bytes of preamble
End of enumeration elements list.
EMAC_CFG_RE : Receiver Enable
bits : 2 - 4 (3 bit)
EMAC_CFG_TE : Transmitter Enable
bits : 3 - 6 (4 bit)
EMAC_CFG_DC : Deferral Check
bits : 4 - 8 (5 bit)
EMAC_CFG_BL : Back-Off Limit
bits : 5 - 11 (7 bit)
Enumeration:
0x0 : EMAC_CFG_BL_1024
k = min (n,10)
0x1 : EMAC_CFG_BL_256
k = min (n,8)
0x2 : EMAC_CFG_BL_8
k = min (n,4)
0x3 : EMAC_CFG_BL_2
k = min (n,1)
End of enumeration elements list.
EMAC_CFG_ACS : Automatic Pad or CRC Stripping
bits : 7 - 14 (8 bit)
EMAC_CFG_DR : Disable Retry
bits : 9 - 18 (10 bit)
EMAC_CFG_IPC : Checksum Offload
bits : 10 - 20 (11 bit)
EMAC_CFG_DUPM : Duplex Mode
bits : 11 - 22 (12 bit)
EMAC_CFG_LOOPBM : Loopback Mode
bits : 12 - 24 (13 bit)
EMAC_CFG_DRO : Disable Receive Own
bits : 13 - 26 (14 bit)
EMAC_CFG_FES : Speed
bits : 14 - 28 (15 bit)
EMAC_CFG_PS : Port Select
bits : 15 - 30 (16 bit)
EMAC_CFG_DISCRS : Disable Carrier Sense During Transmission
bits : 16 - 32 (17 bit)
EMAC_CFG_IFG : Inter-Frame Gap (IFG)
bits : 17 - 36 (20 bit)
Enumeration:
0x0 : EMAC_CFG_IFG_96
96 bit times
0x1 : EMAC_CFG_IFG_88
88 bit times
0x2 : EMAC_CFG_IFG_80
80 bit times
0x3 : EMAC_CFG_IFG_72
72 bit times
0x4 : EMAC_CFG_IFG_64
64 bit times
0x5 : EMAC_CFG_IFG_56
56 bit times
0x6 : EMAC_CFG_IFG_48
48 bit times
0x7 : EMAC_CFG_IFG_40
40 bit times
End of enumeration elements list.
EMAC_CFG_JFEN : Jumbo Frame Enable
bits : 20 - 40 (21 bit)
EMAC_CFG_JD : Jabber Disable
bits : 22 - 44 (23 bit)
EMAC_CFG_WDDIS : Watchdog Disable
bits : 23 - 46 (24 bit)
EMAC_CFG_CST : CRC Stripping for Type Frames
bits : 25 - 50 (26 bit)
EMAC_CFG_TWOKPEN : IEEE 802
bits : 27 - 54 (28 bit)
Ethernet MAC MII Address
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_MIIADDR_MIIB : MII Busy
bits : 0 - 0 (1 bit)
EMAC_MIIADDR_MIIW : MII Write
bits : 1 - 2 (2 bit)
EMAC_MIIADDR_CR : Clock Reference Frequency Selection
bits : 2 - 7 (6 bit)
Enumeration:
0x0 : EMAC_MIIADDR_CR_60_100
The frequency of the System Clock is 60 to 100 MHz providing a MDIO clock of SYSCLK/42
0x1 : EMAC_MIIADDR_CR_100_150
The frequency of the System Clock is 100 to 150 MHz providing a MDIO clock of SYSCLK/62
0x2 : EMAC_MIIADDR_CR_20_35
The frequency of the System Clock is 20-35 MHz providing a MDIO clock of System Clock/16
0x3 : EMAC_MIIADDR_CR_35_60
The frequency of the System Clock is 35 to 60 MHz providing a MDIO clock of System Clock/26
End of enumeration elements list.
EMAC_MIIADDR_MII : MII Register
bits : 6 - 16 (11 bit)
EMAC_MIIADDR_PLA : Physical Layer Address
bits : 11 - 26 (16 bit)
Ethernet MAC MII Address
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_MIIADDR_MIIB : MII Busy
bits : 0 - 0 (1 bit)
EMAC_MIIADDR_MIIW : MII Write
bits : 1 - 2 (2 bit)
EMAC_MIIADDR_CR : Clock Reference Frequency Selection
bits : 2 - 7 (6 bit)
Enumeration:
0x0 : EMAC_MIIADDR_CR_60_100
The frequency of the System Clock is 60 to 100 MHz providing a MDIO clock of SYSCLK/42
0x1 : EMAC_MIIADDR_CR_100_150
The frequency of the System Clock is 100 to 150 MHz providing a MDIO clock of SYSCLK/62
0x2 : EMAC_MIIADDR_CR_20_35
The frequency of the System Clock is 20-35 MHz providing a MDIO clock of System Clock/16
0x3 : EMAC_MIIADDR_CR_35_60
The frequency of the System Clock is 35 to 60 MHz providing a MDIO clock of System Clock/26
End of enumeration elements list.
EMAC_MIIADDR_MII : MII Register
bits : 6 - 16 (11 bit)
EMAC_MIIADDR_PLA : Physical Layer Address
bits : 11 - 26 (16 bit)
Ethernet MAC MMC Control
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_MMCCTRL_CNTRST : Counters Reset
bits : 0 - 0 (1 bit)
EMAC_MMCCTRL_CNTSTPRO : Counters Stop Rollover
bits : 1 - 2 (2 bit)
EMAC_MMCCTRL_RSTONRD : Reset on Read
bits : 2 - 4 (3 bit)
EMAC_MMCCTRL_CNTFREEZ : MMC Counter Freeze
bits : 3 - 6 (4 bit)
EMAC_MMCCTRL_CNTPRST : Counters Preset
bits : 4 - 8 (5 bit)
EMAC_MMCCTRL_CNTPRSTLVL : Full/Half Preset Level Value
bits : 5 - 10 (6 bit)
EMAC_MMCCTRL_UCDBC : Update MMC Counters for Dropped Broadcast Frames
bits : 8 - 16 (9 bit)
Ethernet MAC MMC Control
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_MMCCTRL_CNTRST : Counters Reset
bits : 0 - 0 (1 bit)
EMAC_MMCCTRL_CNTSTPRO : Counters Stop Rollover
bits : 1 - 2 (2 bit)
EMAC_MMCCTRL_RSTONRD : Reset on Read
bits : 2 - 4 (3 bit)
EMAC_MMCCTRL_CNTFREEZ : MMC Counter Freeze
bits : 3 - 6 (4 bit)
EMAC_MMCCTRL_CNTPRST : Counters Preset
bits : 4 - 8 (5 bit)
EMAC_MMCCTRL_CNTPRSTLVL : Full/Half Preset Level Value
bits : 5 - 10 (6 bit)
EMAC_MMCCTRL_UCDBC : Update MMC Counters for Dropped Broadcast Frames
bits : 8 - 16 (9 bit)
Ethernet MAC MMC Receive Raw Interrupt Status
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_MMCRXRIS_GBF : MMC Receive Good Bad Frame Counter Interrupt Status
bits : 0 - 0 (1 bit)
EMAC_MMCRXRIS_CRCERR : MMC Receive CRC Error Frame Counter Interrupt Status
bits : 5 - 10 (6 bit)
EMAC_MMCRXRIS_ALGNERR : MMC Receive Alignment Error Frame Counter Interrupt Status
bits : 6 - 12 (7 bit)
EMAC_MMCRXRIS_UCGF : MMC Receive Unicast Good Frame Counter Interrupt Status
bits : 17 - 34 (18 bit)
Ethernet MAC MMC Receive Raw Interrupt Status
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_MMCRXRIS_GBF : MMC Receive Good Bad Frame Counter Interrupt Status
bits : 0 - 0 (1 bit)
EMAC_MMCRXRIS_CRCERR : MMC Receive CRC Error Frame Counter Interrupt Status
bits : 5 - 10 (6 bit)
EMAC_MMCRXRIS_ALGNERR : MMC Receive Alignment Error Frame Counter Interrupt Status
bits : 6 - 12 (7 bit)
EMAC_MMCRXRIS_UCGF : MMC Receive Unicast Good Frame Counter Interrupt Status
bits : 17 - 34 (18 bit)
Ethernet MAC MMC Transmit Raw Interrupt Status
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_MMCTXRIS_GBF : MMC Transmit Good Bad Frame Counter Interrupt Status
bits : 1 - 2 (2 bit)
EMAC_MMCTXRIS_SCOLLGF : MMC Transmit Single Collision Good Frame Counter Interrupt Status
bits : 14 - 28 (15 bit)
EMAC_MMCTXRIS_MCOLLGF : MMC Transmit Multiple Collision Good Frame Counter Interrupt Status
bits : 15 - 30 (16 bit)
EMAC_MMCTXRIS_OCTCNT : Octet Counter Interrupt Status
bits : 20 - 40 (21 bit)
Ethernet MAC MMC Transmit Raw Interrupt Status
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_MMCTXRIS_GBF : MMC Transmit Good Bad Frame Counter Interrupt Status
bits : 1 - 2 (2 bit)
EMAC_MMCTXRIS_SCOLLGF : MMC Transmit Single Collision Good Frame Counter Interrupt Status
bits : 14 - 28 (15 bit)
EMAC_MMCTXRIS_MCOLLGF : MMC Transmit Multiple Collision Good Frame Counter Interrupt Status
bits : 15 - 30 (16 bit)
EMAC_MMCTXRIS_OCTCNT : Octet Counter Interrupt Status
bits : 20 - 40 (21 bit)
Ethernet MAC MMC Receive Interrupt Mask
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_MMCRXIM_GBF : MMC Receive Good Bad Frame Counter Interrupt Mask
bits : 0 - 0 (1 bit)
EMAC_MMCRXIM_CRCERR : MMC Receive CRC Error Frame Counter Interrupt Mask
bits : 5 - 10 (6 bit)
EMAC_MMCRXIM_ALGNERR : MMC Receive Alignment Error Frame Counter Interrupt Mask
bits : 6 - 12 (7 bit)
EMAC_MMCRXIM_UCGF : MMC Receive Unicast Good Frame Counter Interrupt Mask
bits : 17 - 34 (18 bit)
Ethernet MAC MMC Receive Interrupt Mask
address_offset : 0x10C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_MMCRXIM_GBF : MMC Receive Good Bad Frame Counter Interrupt Mask
bits : 0 - 0 (1 bit)
EMAC_MMCRXIM_CRCERR : MMC Receive CRC Error Frame Counter Interrupt Mask
bits : 5 - 10 (6 bit)
EMAC_MMCRXIM_ALGNERR : MMC Receive Alignment Error Frame Counter Interrupt Mask
bits : 6 - 12 (7 bit)
EMAC_MMCRXIM_UCGF : MMC Receive Unicast Good Frame Counter Interrupt Mask
bits : 17 - 34 (18 bit)
Ethernet MAC MMC Transmit Interrupt Mask
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_MMCTXIM_GBF : MMC Transmit Good Bad Frame Counter Interrupt Mask
bits : 1 - 2 (2 bit)
EMAC_MMCTXIM_SCOLLGF : MMC Transmit Single Collision Good Frame Counter Interrupt Mask
bits : 14 - 28 (15 bit)
EMAC_MMCTXIM_MCOLLGF : MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask
bits : 15 - 30 (16 bit)
EMAC_MMCTXIM_OCTCNT : MMC Transmit Good Octet Counter Interrupt Mask
bits : 20 - 40 (21 bit)
Ethernet MAC MMC Transmit Interrupt Mask
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_MMCTXIM_GBF : MMC Transmit Good Bad Frame Counter Interrupt Mask
bits : 1 - 2 (2 bit)
EMAC_MMCTXIM_SCOLLGF : MMC Transmit Single Collision Good Frame Counter Interrupt Mask
bits : 14 - 28 (15 bit)
EMAC_MMCTXIM_MCOLLGF : MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask
bits : 15 - 30 (16 bit)
EMAC_MMCTXIM_OCTCNT : MMC Transmit Good Octet Counter Interrupt Mask
bits : 20 - 40 (21 bit)
Ethernet MAC Transmit Frame Count for Good and Bad Frames
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TXCNTGB_TXFRMGB : This field indicates the number of good and bad frames transmitted, exclusive of retried frames
bits : 0 - 31 (32 bit)
Ethernet MAC Transmit Frame Count for Good and Bad Frames
address_offset : 0x118 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TXCNTGB_TXFRMGB : This field indicates the number of good and bad frames transmitted, exclusive of retried frames
bits : 0 - 31 (32 bit)
Ethernet MAC MII Data Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_MIIDATA_DATA : MII Data
bits : 0 - 15 (16 bit)
Ethernet MAC MII Data Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_MIIDATA_DATA : MII Data
bits : 0 - 15 (16 bit)
Ethernet MAC Transmit Frame Count for Frames Transmitted after Single Collision
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TXCNTSCOL_TXSNGLCOLG : This field indicates the number of successfully transmitted frames after a single collision in the half-duplex mode
bits : 0 - 31 (32 bit)
Ethernet MAC Transmit Frame Count for Frames Transmitted after Single Collision
address_offset : 0x14C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TXCNTSCOL_TXSNGLCOLG : This field indicates the number of successfully transmitted frames after a single collision in the half-duplex mode
bits : 0 - 31 (32 bit)
Ethernet MAC Transmit Frame Count for Frames Transmitted after Multiple Collisions
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TXCNTMCOL_TXMULTCOLG : This field indicates the number of successfully transmitted frames after multiple collisions in the half-duplex mode
bits : 0 - 31 (32 bit)
Ethernet MAC Transmit Frame Count for Frames Transmitted after Multiple Collisions
address_offset : 0x150 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TXCNTMCOL_TXMULTCOLG : This field indicates the number of successfully transmitted frames after multiple collisions in the half-duplex mode
bits : 0 - 31 (32 bit)
Ethernet MAC Transmit Octet Count Good
address_offset : 0x164 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TXOCTCNTG_TXOCTG : This field indicates the number of bytes transmitted, exclusive of preamble, in good frames
bits : 0 - 31 (32 bit)
Ethernet MAC Transmit Octet Count Good
address_offset : 0x164 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TXOCTCNTG_TXOCTG : This field indicates the number of bytes transmitted, exclusive of preamble, in good frames
bits : 0 - 31 (32 bit)
Ethernet MAC Flow Control
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_FLOWCTL_FCBBPA : Flow Control Busy or Back-pressure Activate
bits : 0 - 0 (1 bit)
EMAC_FLOWCTL_TFE : Transmit Flow Control Enable
bits : 1 - 2 (2 bit)
EMAC_FLOWCTL_RFE : Receive Flow Control Enable
bits : 2 - 4 (3 bit)
EMAC_FLOWCTL_UP : Unicast Pause Frame Detect
bits : 3 - 6 (4 bit)
EMAC_FLOWCTL_PLT : Pause Low Threshold
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EMAC_FLOWCTL_PLT_4
The threshold is Pause time minus 4 slot times (PT - 4 slot times)
0x1 : EMAC_FLOWCTL_PLT_28
The threshold is Pause time minus 28 slot times (PT - 28 slot times)
0x2 : EMAC_FLOWCTL_PLT_144
The threshold is Pause time minus 144 slot times (PT - 144 slot times)
0x3 : EMAC_FLOWCTL_PLT_156
The threshold is Pause time minus 256 slot times (PT - 256 slot times)
End of enumeration elements list.
EMAC_FLOWCTL_DZQP : Disable Zero-Quanta Pause
bits : 7 - 14 (8 bit)
EMAC_FLOWCTL_PT : Pause Time
bits : 16 - 47 (32 bit)
Ethernet MAC Flow Control
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_FLOWCTL_FCBBPA : Flow Control Busy or Back-pressure Activate
bits : 0 - 0 (1 bit)
EMAC_FLOWCTL_TFE : Transmit Flow Control Enable
bits : 1 - 2 (2 bit)
EMAC_FLOWCTL_RFE : Receive Flow Control Enable
bits : 2 - 4 (3 bit)
EMAC_FLOWCTL_UP : Unicast Pause Frame Detect
bits : 3 - 6 (4 bit)
EMAC_FLOWCTL_PLT : Pause Low Threshold
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EMAC_FLOWCTL_PLT_4
The threshold is Pause time minus 4 slot times (PT - 4 slot times)
0x1 : EMAC_FLOWCTL_PLT_28
The threshold is Pause time minus 28 slot times (PT - 28 slot times)
0x2 : EMAC_FLOWCTL_PLT_144
The threshold is Pause time minus 144 slot times (PT - 144 slot times)
0x3 : EMAC_FLOWCTL_PLT_156
The threshold is Pause time minus 256 slot times (PT - 256 slot times)
End of enumeration elements list.
EMAC_FLOWCTL_DZQP : Disable Zero-Quanta Pause
bits : 7 - 14 (8 bit)
EMAC_FLOWCTL_PT : Pause Time
bits : 16 - 47 (32 bit)
Ethernet MAC Receive Frame Count for Good and Bad Frames
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_RXCNTGB_RXFRMGB : This field indicates the number of received good and bad frames
bits : 0 - 31 (32 bit)
Ethernet MAC Receive Frame Count for Good and Bad Frames
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_RXCNTGB_RXFRMGB : This field indicates the number of received good and bad frames
bits : 0 - 31 (32 bit)
Ethernet MAC Receive Frame Count for CRC Error Frames
address_offset : 0x194 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_RXCNTCRCERR_RXCRCERR : This field indicates the number of frames received with CRC error
bits : 0 - 31 (32 bit)
Ethernet MAC Receive Frame Count for CRC Error Frames
address_offset : 0x194 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_RXCNTCRCERR_RXCRCERR : This field indicates the number of frames received with CRC error
bits : 0 - 31 (32 bit)
Ethernet MAC Receive Frame Count for Alignment Error Frames
address_offset : 0x198 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_RXCNTALGNERR_RXALGNERR : This field indicates the number of frames received with alignment (dribble) error
bits : 0 - 31 (32 bit)
Ethernet MAC Receive Frame Count for Alignment Error Frames
address_offset : 0x198 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_RXCNTALGNERR_RXALGNERR : This field indicates the number of frames received with alignment (dribble) error
bits : 0 - 31 (32 bit)
Ethernet MAC VLAN Tag
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_VLANTG_VL : VLAN Tag Identifier for Receive Frames
bits : 0 - 15 (16 bit)
EMAC_VLANTG_ETV : Enable 12-Bit VLAN Tag Comparison
bits : 16 - 32 (17 bit)
EMAC_VLANTG_VTIM : VLAN Tag Inverse Match Enable
bits : 17 - 34 (18 bit)
EMAC_VLANTG_ESVL : Enable S-VLAN
bits : 18 - 36 (19 bit)
EMAC_VLANTG_VTHM : VLAN Tag Hash Table Match Enable
bits : 19 - 38 (20 bit)
Ethernet MAC VLAN Tag
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_VLANTG_VL : VLAN Tag Identifier for Receive Frames
bits : 0 - 15 (16 bit)
EMAC_VLANTG_ETV : Enable 12-Bit VLAN Tag Comparison
bits : 16 - 32 (17 bit)
EMAC_VLANTG_VTIM : VLAN Tag Inverse Match Enable
bits : 17 - 34 (18 bit)
EMAC_VLANTG_ESVL : Enable S-VLAN
bits : 18 - 36 (19 bit)
EMAC_VLANTG_VTHM : VLAN Tag Hash Table Match Enable
bits : 19 - 38 (20 bit)
Ethernet MAC Receive Frame Count for Good Unicast Frames
address_offset : 0x1C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_RXCNTGUNI_RXUCASTG : This field indicates the number of received good unicast frames
bits : 0 - 31 (32 bit)
Ethernet MAC Receive Frame Count for Good Unicast Frames
address_offset : 0x1C4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_RXCNTGUNI_RXUCASTG : This field indicates the number of received good unicast frames
bits : 0 - 31 (32 bit)
Ethernet MAC Status
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_STATUS_RPE : MAC MII Receive Protocol Engine Status
bits : 0 - 0 (1 bit)
EMAC_STATUS_RFCFC : MAC Receive Frame Controller FIFO Status
bits : 1 - 3 (3 bit)
EMAC_STATUS_RWC : TX/RX Controller RX FIFO Write Controller Active Status
bits : 4 - 8 (5 bit)
EMAC_STATUS_RRC : TX/RX Controller Read Controller State
bits : 5 - 11 (7 bit)
Enumeration:
0x0 : EMAC_STATUS_RRC_IDLE
IDLE state
0x1 : EMAC_STATUS_RRC_STATUS
Reading frame data
0x2 : EMAC_STATUS_RRC_DATA
Reading frame status (or timestamp)
0x3 : EMAC_STATUS_RRC_FLUSH
Flushing the frame data and status
End of enumeration elements list.
EMAC_STATUS_RXF : TX/RX Controller RX FIFO Fill-level Status
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : EMAC_STATUS_RXF_EMPTY
RX FIFO Empty
0x1 : EMAC_STATUS_RXF_BELOW
RX FIFO fill level is below the flow-control deactivate threshold
0x2 : EMAC_STATUS_RXF_ABOVE
RX FIFO fill level is above the flow-control activate threshold
0x3 : EMAC_STATUS_RXF_FULL
RX FIFO Full
End of enumeration elements list.
EMAC_STATUS_TPE : MAC MII Transmit Protocol Engine Status
bits : 16 - 32 (17 bit)
EMAC_STATUS_TFC : MAC Transmit Frame Controller Status
bits : 17 - 35 (19 bit)
Enumeration:
0x0 : EMAC_STATUS_TFC_IDLE
IDLE state
0x1 : EMAC_STATUS_TFC_STATUS
Waiting for status of previous frame or IFG or backoff period to be over
0x2 : EMAC_STATUS_TFC_PAUSE
Generating and transmitting a PAUSE control frame (in the full-duplex mode)
0x3 : EMAC_STATUS_TFC_INPUT
Transferring input frame for transmission
End of enumeration elements list.
EMAC_STATUS_TXPAUSED : MAC Transmitter PAUSE
bits : 19 - 38 (20 bit)
EMAC_STATUS_TRC : TX/RX Controller's TX FIFO Read Controller Status
bits : 20 - 41 (22 bit)
Enumeration:
0x0 : EMAC_STATUS_TRC_IDLE
IDLE state
0x1 : EMAC_STATUS_TRC_READ
READ state (transferring data to MAC transmitter)
0x2 : EMAC_STATUS_TRC_WAIT
Waiting for TX Status from MAC transmitter
0x3 : EMAC_STATUS_TRC_WRFLUSH
Writing the received TX Status or flushing the TX FIFO
End of enumeration elements list.
EMAC_STATUS_TWC : TX/RX Controller TX FIFO Write Controller Active Status
bits : 22 - 44 (23 bit)
EMAC_STATUS_TXFE : TX/RX Controller TX FIFO Not Empty Status
bits : 24 - 48 (25 bit)
EMAC_STATUS_TXFF : TX/RX Controller TX FIFO Full Status
bits : 25 - 50 (26 bit)
Ethernet MAC Status
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_STATUS_RPE : MAC MII Receive Protocol Engine Status
bits : 0 - 0 (1 bit)
EMAC_STATUS_RFCFC : MAC Receive Frame Controller FIFO Status
bits : 1 - 3 (3 bit)
EMAC_STATUS_RWC : TX/RX Controller RX FIFO Write Controller Active Status
bits : 4 - 8 (5 bit)
EMAC_STATUS_RRC : TX/RX Controller Read Controller State
bits : 5 - 11 (7 bit)
Enumeration:
0x0 : EMAC_STATUS_RRC_IDLE
IDLE state
0x1 : EMAC_STATUS_RRC_STATUS
Reading frame data
0x2 : EMAC_STATUS_RRC_DATA
Reading frame status (or timestamp)
0x3 : EMAC_STATUS_RRC_FLUSH
Flushing the frame data and status
End of enumeration elements list.
EMAC_STATUS_RXF : TX/RX Controller RX FIFO Fill-level Status
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : EMAC_STATUS_RXF_EMPTY
RX FIFO Empty
0x1 : EMAC_STATUS_RXF_BELOW
RX FIFO fill level is below the flow-control deactivate threshold
0x2 : EMAC_STATUS_RXF_ABOVE
RX FIFO fill level is above the flow-control activate threshold
0x3 : EMAC_STATUS_RXF_FULL
RX FIFO Full
End of enumeration elements list.
EMAC_STATUS_TPE : MAC MII Transmit Protocol Engine Status
bits : 16 - 32 (17 bit)
EMAC_STATUS_TFC : MAC Transmit Frame Controller Status
bits : 17 - 35 (19 bit)
Enumeration:
0x0 : EMAC_STATUS_TFC_IDLE
IDLE state
0x1 : EMAC_STATUS_TFC_STATUS
Waiting for status of previous frame or IFG or backoff period to be over
0x2 : EMAC_STATUS_TFC_PAUSE
Generating and transmitting a PAUSE control frame (in the full-duplex mode)
0x3 : EMAC_STATUS_TFC_INPUT
Transferring input frame for transmission
End of enumeration elements list.
EMAC_STATUS_TXPAUSED : MAC Transmitter PAUSE
bits : 19 - 38 (20 bit)
EMAC_STATUS_TRC : TX/RX Controller's TX FIFO Read Controller Status
bits : 20 - 41 (22 bit)
Enumeration:
0x0 : EMAC_STATUS_TRC_IDLE
IDLE state
0x1 : EMAC_STATUS_TRC_READ
READ state (transferring data to MAC transmitter)
0x2 : EMAC_STATUS_TRC_WAIT
Waiting for TX Status from MAC transmitter
0x3 : EMAC_STATUS_TRC_WRFLUSH
Writing the received TX Status or flushing the TX FIFO
End of enumeration elements list.
EMAC_STATUS_TWC : TX/RX Controller TX FIFO Write Controller Active Status
bits : 22 - 44 (23 bit)
EMAC_STATUS_TXFE : TX/RX Controller TX FIFO Not Empty Status
bits : 24 - 48 (25 bit)
EMAC_STATUS_TXFF : TX/RX Controller TX FIFO Full Status
bits : 25 - 50 (26 bit)
Ethernet MAC Remote Wake-Up Frame Filter
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_RWUFF_WAKEUPFIL : Remote Wake-Up Frame Filter
bits : 0 - 31 (32 bit)
Ethernet MAC Remote Wake-Up Frame Filter
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_RWUFF_WAKEUPFIL : Remote Wake-Up Frame Filter
bits : 0 - 31 (32 bit)
Ethernet MAC PMT Control and Status Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_PMTCTLSTAT_PWRDWN : Power Down
bits : 0 - 0 (1 bit)
EMAC_PMTCTLSTAT_MGKPKTEN : Magic Packet Enable
bits : 1 - 2 (2 bit)
EMAC_PMTCTLSTAT_WUPFREN : Wake-Up Frame Enable
bits : 2 - 4 (3 bit)
EMAC_PMTCTLSTAT_MGKPRX : Magic Packet Received
bits : 5 - 10 (6 bit)
EMAC_PMTCTLSTAT_WUPRX : Wake-Up Frame Received
bits : 6 - 12 (7 bit)
EMAC_PMTCTLSTAT_GLBLUCAST : Global Unicast
bits : 9 - 18 (10 bit)
EMAC_PMTCTLSTAT_RWKPTR : Remote Wake-Up FIFO Pointer
bits : 24 - 50 (27 bit)
EMAC_PMTCTLSTAT_WUPFRRST : Wake-Up Frame Filter Register Pointer Reset
bits : 31 - 62 (32 bit)
Ethernet MAC PMT Control and Status Register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_PMTCTLSTAT_PWRDWN : Power Down
bits : 0 - 0 (1 bit)
EMAC_PMTCTLSTAT_MGKPKTEN : Magic Packet Enable
bits : 1 - 2 (2 bit)
EMAC_PMTCTLSTAT_WUPFREN : Wake-Up Frame Enable
bits : 2 - 4 (3 bit)
EMAC_PMTCTLSTAT_MGKPRX : Magic Packet Received
bits : 5 - 10 (6 bit)
EMAC_PMTCTLSTAT_WUPRX : Wake-Up Frame Received
bits : 6 - 12 (7 bit)
EMAC_PMTCTLSTAT_GLBLUCAST : Global Unicast
bits : 9 - 18 (10 bit)
EMAC_PMTCTLSTAT_RWKPTR : Remote Wake-Up FIFO Pointer
bits : 24 - 50 (27 bit)
EMAC_PMTCTLSTAT_WUPFRRST : Wake-Up Frame Filter Register Pointer Reset
bits : 31 - 62 (32 bit)
Ethernet MAC Raw Interrupt Status
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_RIS_PMT : PMT Interrupt Status
bits : 3 - 6 (4 bit)
EMAC_RIS_MMC : MMC Interrupt Status
bits : 4 - 8 (5 bit)
EMAC_RIS_MMCRX : MMC Receive Interrupt Status
bits : 5 - 10 (6 bit)
EMAC_RIS_MMCTX : MMC Transmit Interrupt Status
bits : 6 - 12 (7 bit)
EMAC_RIS_TS : Timestamp Interrupt Status
bits : 9 - 18 (10 bit)
Ethernet MAC Raw Interrupt Status
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_RIS_PMT : PMT Interrupt Status
bits : 3 - 6 (4 bit)
EMAC_RIS_MMC : MMC Interrupt Status
bits : 4 - 8 (5 bit)
EMAC_RIS_MMCRX : MMC Receive Interrupt Status
bits : 5 - 10 (6 bit)
EMAC_RIS_MMCTX : MMC Transmit Interrupt Status
bits : 6 - 12 (7 bit)
EMAC_RIS_TS : Timestamp Interrupt Status
bits : 9 - 18 (10 bit)
Ethernet MAC Interrupt Mask
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_IM_PMT : PMT Interrupt Mask
bits : 3 - 6 (4 bit)
EMAC_IM_TSI : Timestamp Interrupt Mask
bits : 9 - 18 (10 bit)
Ethernet MAC Interrupt Mask
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_IM_PMT : PMT Interrupt Mask
bits : 3 - 6 (4 bit)
EMAC_IM_TSI : Timestamp Interrupt Mask
bits : 9 - 18 (10 bit)
Ethernet MAC Frame Filter
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_FRAMEFLTR_PR : Promiscuous Mode
bits : 0 - 0 (1 bit)
EMAC_FRAMEFLTR_HUC : Hash Unicast
bits : 1 - 2 (2 bit)
EMAC_FRAMEFLTR_HMC : Hash Multicast
bits : 2 - 4 (3 bit)
EMAC_FRAMEFLTR_DAIF : Destination Address (DA) Inverse Filtering
bits : 3 - 6 (4 bit)
EMAC_FRAMEFLTR_PM : Pass All Multicast
bits : 4 - 8 (5 bit)
EMAC_FRAMEFLTR_DBF : Disable Broadcast Frames
bits : 5 - 10 (6 bit)
EMAC_FRAMEFLTR_PCF : Pass Control Frames
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EMAC_FRAMEFLTR_PCF_ALL
The MAC filters all control frames from reaching application
0x1 : EMAC_FRAMEFLTR_PCF_PAUSE
MAC forwards all control frames except PAUSE control frames to application even if they fail the address filter
0x2 : EMAC_FRAMEFLTR_PCF_NONE
MAC forwards all control frames to application even if they fail the address Filter
0x3 : EMAC_FRAMEFLTR_PCF_ADDR
MAC forwards control frames that pass the address Filter
End of enumeration elements list.
EMAC_FRAMEFLTR_SAIF : Source Address (SA) Inverse Filtering
bits : 8 - 16 (9 bit)
EMAC_FRAMEFLTR_SAF : Source Address Filter Enable
bits : 9 - 18 (10 bit)
EMAC_FRAMEFLTR_HPF : Hash or Perfect Filter
bits : 10 - 20 (11 bit)
EMAC_FRAMEFLTR_VTFE : VLAN Tag Filter Enable
bits : 16 - 32 (17 bit)
EMAC_FRAMEFLTR_RA : Receive All
bits : 31 - 62 (32 bit)
Ethernet MAC Frame Filter
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_FRAMEFLTR_PR : Promiscuous Mode
bits : 0 - 0 (1 bit)
EMAC_FRAMEFLTR_HUC : Hash Unicast
bits : 1 - 2 (2 bit)
EMAC_FRAMEFLTR_HMC : Hash Multicast
bits : 2 - 4 (3 bit)
EMAC_FRAMEFLTR_DAIF : Destination Address (DA) Inverse Filtering
bits : 3 - 6 (4 bit)
EMAC_FRAMEFLTR_PM : Pass All Multicast
bits : 4 - 8 (5 bit)
EMAC_FRAMEFLTR_DBF : Disable Broadcast Frames
bits : 5 - 10 (6 bit)
EMAC_FRAMEFLTR_PCF : Pass Control Frames
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EMAC_FRAMEFLTR_PCF_ALL
The MAC filters all control frames from reaching application
0x1 : EMAC_FRAMEFLTR_PCF_PAUSE
MAC forwards all control frames except PAUSE control frames to application even if they fail the address filter
0x2 : EMAC_FRAMEFLTR_PCF_NONE
MAC forwards all control frames to application even if they fail the address Filter
0x3 : EMAC_FRAMEFLTR_PCF_ADDR
MAC forwards control frames that pass the address Filter
End of enumeration elements list.
EMAC_FRAMEFLTR_SAIF : Source Address (SA) Inverse Filtering
bits : 8 - 16 (9 bit)
EMAC_FRAMEFLTR_SAF : Source Address Filter Enable
bits : 9 - 18 (10 bit)
EMAC_FRAMEFLTR_HPF : Hash or Perfect Filter
bits : 10 - 20 (11 bit)
EMAC_FRAMEFLTR_VTFE : VLAN Tag Filter Enable
bits : 16 - 32 (17 bit)
EMAC_FRAMEFLTR_RA : Receive All
bits : 31 - 62 (32 bit)
Ethernet MAC Address 0 High
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_ADDR0H_ADDRHI : MAC Address0 [47:32]
bits : 0 - 15 (16 bit)
EMAC_ADDR0H_AE : Address Enable
bits : 31 - 62 (32 bit)
Ethernet MAC Address 0 High
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_ADDR0H_ADDRHI : MAC Address0 [47:32]
bits : 0 - 15 (16 bit)
EMAC_ADDR0H_AE : Address Enable
bits : 31 - 62 (32 bit)
Ethernet MAC Address 0 Low Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_ADDR0L_ADDRLO : MAC Address0 [31:0]
bits : 0 - 31 (32 bit)
Ethernet MAC Address 0 Low Register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_ADDR0L_ADDRLO : MAC Address0 [31:0]
bits : 0 - 31 (32 bit)
Ethernet MAC Address 1 High
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_ADDR1H_ADDRHI : MAC Address1 [47:32]
bits : 0 - 15 (16 bit)
EMAC_ADDR1H_MBC : Mask Byte Control
bits : 24 - 53 (30 bit)
EMAC_ADDR1H_SA : Source Address
bits : 30 - 60 (31 bit)
EMAC_ADDR1H_AE : Address Enable
bits : 31 - 62 (32 bit)
Ethernet MAC Address 1 High
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_ADDR1H_ADDRHI : MAC Address1 [47:32]
bits : 0 - 15 (16 bit)
EMAC_ADDR1H_MBC : Mask Byte Control
bits : 24 - 53 (30 bit)
EMAC_ADDR1H_SA : Source Address
bits : 30 - 60 (31 bit)
EMAC_ADDR1H_AE : Address Enable
bits : 31 - 62 (32 bit)
Ethernet MAC Address 1 Low
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_ADDR1L_ADDRLO : MAC Address1 [31:0]
bits : 0 - 31 (32 bit)
Ethernet MAC Address 1 Low
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_ADDR1L_ADDRLO : MAC Address1 [31:0]
bits : 0 - 31 (32 bit)
Ethernet MAC Address 2 High
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_ADDR2H_ADDRHI : MAC Address2 [47:32]
bits : 0 - 15 (16 bit)
EMAC_ADDR2H_MBC : Mask Byte Control
bits : 24 - 53 (30 bit)
EMAC_ADDR2H_SA : Source Address
bits : 30 - 60 (31 bit)
EMAC_ADDR2H_AE : Address Enable
bits : 31 - 62 (32 bit)
Ethernet MAC Address 2 High
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_ADDR2H_ADDRHI : MAC Address2 [47:32]
bits : 0 - 15 (16 bit)
EMAC_ADDR2H_MBC : Mask Byte Control
bits : 24 - 53 (30 bit)
EMAC_ADDR2H_SA : Source Address
bits : 30 - 60 (31 bit)
EMAC_ADDR2H_AE : Address Enable
bits : 31 - 62 (32 bit)
Ethernet MAC Address 2 Low
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_ADDR2L_ADDRLO : MAC Address2 [31:0]
bits : 0 - 31 (32 bit)
Ethernet MAC Address 2 Low
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_ADDR2L_ADDRLO : MAC Address2 [31:0]
bits : 0 - 31 (32 bit)
Ethernet MAC Address 3 High
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_ADDR3H_ADDRHI : MAC Address3 [47:32]
bits : 0 - 15 (16 bit)
EMAC_ADDR3H_MBC : Mask Byte Control
bits : 24 - 53 (30 bit)
EMAC_ADDR3H_SA : Source Address
bits : 30 - 60 (31 bit)
EMAC_ADDR3H_AE : Address Enable
bits : 31 - 62 (32 bit)
Ethernet MAC Address 3 High
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_ADDR3H_ADDRHI : MAC Address3 [47:32]
bits : 0 - 15 (16 bit)
EMAC_ADDR3H_MBC : Mask Byte Control
bits : 24 - 53 (30 bit)
EMAC_ADDR3H_SA : Source Address
bits : 30 - 60 (31 bit)
EMAC_ADDR3H_AE : Address Enable
bits : 31 - 62 (32 bit)
Ethernet MAC VLAN Tag Inclusion or Replacement
address_offset : 0x584 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_VLNINCREP_VLT : VLAN Tag for Transmit Frames
bits : 0 - 15 (16 bit)
EMAC_VLNINCREP_VLC : VLAN Tag Control in Transmit Frames
bits : 16 - 33 (18 bit)
Enumeration:
0x0 : EMAC_VLNINCREP_VLC_NONE
No VLAN tag deletion, insertion, or replacement
0x1 : EMAC_VLNINCREP_VLC_TAGDEL
VLAN tag deletion
0x2 : EMAC_VLNINCREP_VLC_TAGINS
VLAN tag insertion
0x3 : EMAC_VLNINCREP_VLC_TAGREP
VLAN tag replacement
End of enumeration elements list.
EMAC_VLNINCREP_VLP : VLAN Priority Control
bits : 18 - 36 (19 bit)
EMAC_VLNINCREP_CSVL : C-VLAN or S-VLAN
bits : 19 - 38 (20 bit)
Ethernet MAC VLAN Tag Inclusion or Replacement
address_offset : 0x584 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_VLNINCREP_VLT : VLAN Tag for Transmit Frames
bits : 0 - 15 (16 bit)
EMAC_VLNINCREP_VLC : VLAN Tag Control in Transmit Frames
bits : 16 - 33 (18 bit)
Enumeration:
0x0 : EMAC_VLNINCREP_VLC_NONE
No VLAN tag deletion, insertion, or replacement
0x1 : EMAC_VLNINCREP_VLC_TAGDEL
VLAN tag deletion
0x2 : EMAC_VLNINCREP_VLC_TAGINS
VLAN tag insertion
0x3 : EMAC_VLNINCREP_VLC_TAGREP
VLAN tag replacement
End of enumeration elements list.
EMAC_VLNINCREP_VLP : VLAN Priority Control
bits : 18 - 36 (19 bit)
EMAC_VLNINCREP_CSVL : C-VLAN or S-VLAN
bits : 19 - 38 (20 bit)
Ethernet MAC VLAN Hash Table
address_offset : 0x588 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_VLANHASH_VLHT : VLAN Hash Table
bits : 0 - 15 (16 bit)
Ethernet MAC VLAN Hash Table
address_offset : 0x588 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_VLANHASH_VLHT : VLAN Hash Table
bits : 0 - 15 (16 bit)
Ethernet MAC Address 3 Low
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_ADDR3L_ADDRLO : MAC Address3 [31:0]
bits : 0 - 31 (32 bit)
Ethernet MAC Address 3 Low
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_ADDR3L_ADDRLO : MAC Address3 [31:0]
bits : 0 - 31 (32 bit)
Ethernet MAC Timestamp Control
address_offset : 0x700 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TIMSTCTRL_TSEN : Timestamp Enable
bits : 0 - 0 (1 bit)
EMAC_TIMSTCTRL_TSFCUPDT : Timestamp Fine or Coarse Update
bits : 1 - 2 (2 bit)
EMAC_TIMSTCTRL_TSINIT : Timestamp Initialize
bits : 2 - 4 (3 bit)
EMAC_TIMSTCTRL_TSUPDT : Timestamp Update
bits : 3 - 6 (4 bit)
EMAC_TIMSTCTRL_INTTRIG : Timestamp Interrupt Trigger Enable
bits : 4 - 8 (5 bit)
EMAC_TIMSTCTRL_ADDREGUP : Addend Register Update
bits : 5 - 10 (6 bit)
EMAC_TIMSTCTRL_ALLF : Enable Timestamp For All Frames
bits : 8 - 16 (9 bit)
EMAC_TIMSTCTRL_DGTLBIN : Timestamp Digital or Binary Rollover Control
bits : 9 - 18 (10 bit)
EMAC_TIMSTCTRL_PTPVER2 : Enable PTP Packet Processing For Version 2 Format
bits : 10 - 20 (11 bit)
EMAC_TIMSTCTRL_PTPETH : Enable Processing of PTP Over Ethernet Frames
bits : 11 - 22 (12 bit)
EMAC_TIMSTCTRL_PTPIPV6 : Enable Processing of PTP Frames Sent Over IPv6-UDP
bits : 12 - 24 (13 bit)
EMAC_TIMSTCTRL_PTPIPV4 : Enable Processing of PTP Frames Sent over IPv4-UDP
bits : 13 - 26 (14 bit)
EMAC_TIMSTCTRL_TSEVNT : Enable Timestamp Snapshot for Event Messages
bits : 14 - 28 (15 bit)
EMAC_TIMSTCTRL_TSMAST : Enable Snapshot for Messages Relevant to Master
bits : 15 - 30 (16 bit)
EMAC_TIMSTCTRL_SELPTP : Select PTP packets for Taking Snapshots
bits : 16 - 33 (18 bit)
EMAC_TIMSTCTRL_PTPFLTR : Enable MAC address for PTP Frame Filtering
bits : 18 - 36 (19 bit)
Ethernet MAC Timestamp Control
address_offset : 0x700 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TIMSTCTRL_TSEN : Timestamp Enable
bits : 0 - 0 (1 bit)
EMAC_TIMSTCTRL_TSFCUPDT : Timestamp Fine or Coarse Update
bits : 1 - 2 (2 bit)
EMAC_TIMSTCTRL_TSINIT : Timestamp Initialize
bits : 2 - 4 (3 bit)
EMAC_TIMSTCTRL_TSUPDT : Timestamp Update
bits : 3 - 6 (4 bit)
EMAC_TIMSTCTRL_INTTRIG : Timestamp Interrupt Trigger Enable
bits : 4 - 8 (5 bit)
EMAC_TIMSTCTRL_ADDREGUP : Addend Register Update
bits : 5 - 10 (6 bit)
EMAC_TIMSTCTRL_ALLF : Enable Timestamp For All Frames
bits : 8 - 16 (9 bit)
EMAC_TIMSTCTRL_DGTLBIN : Timestamp Digital or Binary Rollover Control
bits : 9 - 18 (10 bit)
EMAC_TIMSTCTRL_PTPVER2 : Enable PTP Packet Processing For Version 2 Format
bits : 10 - 20 (11 bit)
EMAC_TIMSTCTRL_PTPETH : Enable Processing of PTP Over Ethernet Frames
bits : 11 - 22 (12 bit)
EMAC_TIMSTCTRL_PTPIPV6 : Enable Processing of PTP Frames Sent Over IPv6-UDP
bits : 12 - 24 (13 bit)
EMAC_TIMSTCTRL_PTPIPV4 : Enable Processing of PTP Frames Sent over IPv4-UDP
bits : 13 - 26 (14 bit)
EMAC_TIMSTCTRL_TSEVNT : Enable Timestamp Snapshot for Event Messages
bits : 14 - 28 (15 bit)
EMAC_TIMSTCTRL_TSMAST : Enable Snapshot for Messages Relevant to Master
bits : 15 - 30 (16 bit)
EMAC_TIMSTCTRL_SELPTP : Select PTP packets for Taking Snapshots
bits : 16 - 33 (18 bit)
EMAC_TIMSTCTRL_PTPFLTR : Enable MAC address for PTP Frame Filtering
bits : 18 - 36 (19 bit)
Ethernet MAC Sub-Second Increment
address_offset : 0x704 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_SUBSECINC_SSINC : Sub-second Increment Value
bits : 0 - 7 (8 bit)
Ethernet MAC Sub-Second Increment
address_offset : 0x704 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_SUBSECINC_SSINC : Sub-second Increment Value
bits : 0 - 7 (8 bit)
Ethernet MAC System Time - Seconds
address_offset : 0x708 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TIMSEC_TSS : Timestamp Second
bits : 0 - 31 (32 bit)
Ethernet MAC System Time - Seconds
address_offset : 0x708 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TIMSEC_TSS : Timestamp Second
bits : 0 - 31 (32 bit)
Ethernet MAC System Time - Nanoseconds
address_offset : 0x70C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TIMNANO_TSSS : Timestamp Sub-Seconds
bits : 0 - 30 (31 bit)
Ethernet MAC System Time - Nanoseconds
address_offset : 0x70C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TIMNANO_TSSS : Timestamp Sub-Seconds
bits : 0 - 30 (31 bit)
Ethernet MAC System Time - Seconds Update
address_offset : 0x710 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TIMSECU_TSS : Timestamp Second
bits : 0 - 31 (32 bit)
Ethernet MAC System Time - Seconds Update
address_offset : 0x710 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TIMSECU_TSS : Timestamp Second
bits : 0 - 31 (32 bit)
Ethernet MAC System Time - Nanoseconds Update
address_offset : 0x714 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TIMNANOU_TSSS : Timestamp Sub-Second
bits : 0 - 30 (31 bit)
EMAC_TIMNANOU_ADDSUB : Add or subtract time
bits : 31 - 62 (32 bit)
Ethernet MAC System Time - Nanoseconds Update
address_offset : 0x714 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TIMNANOU_TSSS : Timestamp Sub-Second
bits : 0 - 30 (31 bit)
EMAC_TIMNANOU_ADDSUB : Add or subtract time
bits : 31 - 62 (32 bit)
Ethernet MAC Timestamp Addend
address_offset : 0x718 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TIMADD_TSAR : Timestamp Addend Register
bits : 0 - 31 (32 bit)
Ethernet MAC Timestamp Addend
address_offset : 0x718 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TIMADD_TSAR : Timestamp Addend Register
bits : 0 - 31 (32 bit)
Ethernet MAC Target Time Seconds
address_offset : 0x71C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TARGSEC_TSTR : Target Time Seconds Register
bits : 0 - 31 (32 bit)
Ethernet MAC Target Time Seconds
address_offset : 0x71C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TARGSEC_TSTR : Target Time Seconds Register
bits : 0 - 31 (32 bit)
Ethernet MAC Target Time Nanoseconds
address_offset : 0x720 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TARGNANO_TTSLO : Target Timestamp Low Register
bits : 0 - 30 (31 bit)
EMAC_TARGNANO_TRGTBUSY : Target Time Register Busy
bits : 31 - 62 (32 bit)
Ethernet MAC Target Time Nanoseconds
address_offset : 0x720 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TARGNANO_TTSLO : Target Timestamp Low Register
bits : 0 - 30 (31 bit)
EMAC_TARGNANO_TRGTBUSY : Target Time Register Busy
bits : 31 - 62 (32 bit)
Ethernet MAC System Time-Higher Word Seconds
address_offset : 0x724 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_HWORDSEC_TSHWR : Target Timestamp Higher Word Register
bits : 0 - 15 (16 bit)
Ethernet MAC System Time-Higher Word Seconds
address_offset : 0x724 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_HWORDSEC_TSHWR : Target Timestamp Higher Word Register
bits : 0 - 15 (16 bit)
Ethernet MAC Timestamp Status
address_offset : 0x728 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TIMSTAT_TSSOVF : Timestamp Seconds Overflow
bits : 0 - 0 (1 bit)
EMAC_TIMSTAT_TSTARGT : Timestamp Target Time Reached
bits : 1 - 2 (2 bit)
Ethernet MAC Timestamp Status
address_offset : 0x728 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TIMSTAT_TSSOVF : Timestamp Seconds Overflow
bits : 0 - 0 (1 bit)
EMAC_TIMSTAT_TSTARGT : Timestamp Target Time Reached
bits : 1 - 2 (2 bit)
Ethernet MAC PPS Control
address_offset : 0x72C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_PPSCTRL_PPSCTRL : EN0PPS Output Frequency Control (PPSCTRL) or Command Control (PPSCMD)
bits : 0 - 3 (4 bit)
Enumeration:
0x0 : EMAC_PPSCTRL_PPSCTRL_1HZ
When the PPSEN0 bit = 0x0, the EN0PPS signal is 1 pulse of the PTP reference clock.(of width clk_ptp_i) every second
0x1 : EMAC_PPSCTRL_PPSCTRL_2HZ
When the PPSEN0 bit = 0x0, the binary rollover is 2 Hz, and the digital rollover is 1 Hz
0x2 : EMAC_PPSCTRL_PPSCTRL_4HZ
When the PPSEN0 bit = 0x0, the binary rollover is 4 Hz, and the digital rollover is 2 Hz
0x3 : EMAC_PPSCTRL_PPSCTRL_8HZ
When thePPSEN0 bit = 0x0, the binary rollover is 8 Hz, and the digital rollover is 4 Hz,
0x4 : EMAC_PPSCTRL_PPSCTRL_16HZ
When thePPSEN0 bit = 0x0, the binary rollover is 16 Hz, and the digital rollover is 8 Hz
0x5 : EMAC_PPSCTRL_PPSCTRL_32HZ
When thePPSEN0 bit = 0x0, the binary rollover is 32 Hz, and the digital rollover is 16 Hz
0x6 : EMAC_PPSCTRL_PPSCTRL_64HZ
When thePPSEN0 bit = 0x0, the binary rollover is 64 Hz, and the digital rollover is 32 Hz
0x7 : EMAC_PPSCTRL_PPSCTRL_128HZ
When thePPSEN0 bit = 0x0, the binary rollover is 128 Hz, and the digital rollover is 64 Hz
0x8 : EMAC_PPSCTRL_PPSCTRL_256HZ
When thePPSEN0 bit = 0x0, the binary rollover is 256 Hz, and the digital rollover is 128 Hz
0x9 : EMAC_PPSCTRL_PPSCTRL_512HZ
When thePPSEN0 bit = 0x0, the binary rollover is 512 Hz, and the digital rollover is 256 Hz
0xa : EMAC_PPSCTRL_PPSCTRL_1024HZ
When the PPSEN0 bit = 0x0, the binary rollover is 1.024 kHz, and the digital rollover is 512 Hz
0xb : EMAC_PPSCTRL_PPSCTRL_2048HZ
When thePPSEN0 bit = 0x0, the binary rollover is 2.048 kHz, and the digital rollover is 1.024 kHz
0xc : EMAC_PPSCTRL_PPSCTRL_4096HZ
When thePPSEN0 bit = 0x0, the binary rollover is 4.096 kHz, and the digital rollover is 2.048 kHz
0xd : EMAC_PPSCTRL_PPSCTRL_8192HZ
When thePPSEN0 bit = 0x0, the binary rollover is 8.192 kHz, and the digital rollover is 4.096 kHz
0xe : EMAC_PPSCTRL_PPSCTRL_16384HZ
When thePPSEN0 bit = 0x0, the binary rollover is 16.384 kHz, and the digital rollover is 8.092 kHz
0xf : EMAC_PPSCTRL_PPSCTRL_32768HZ
When thePPSEN0 bit = 0x0, the binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz
End of enumeration elements list.
EMAC_PPSCTRL_PPSEN0 : Flexible PPS Output Mode Enable
bits : 4 - 8 (5 bit)
EMAC_PPSCTRL_TRGMODS0 : Target Time Register Mode for PPS0 Output
bits : 5 - 11 (7 bit)
Enumeration:
0x0 : EMAC_PPSCTRL_TRGMODS0_INTONLY
Indicates that the Target Time registers are programmed only for generating the interrupt event
0x2 : EMAC_PPSCTRL_TRGMODS0_INTPPS0
Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the EN0PPS output signal
0x3 : EMAC_PPSCTRL_TRGMODS0_PPS0ONLY
Indicates that the Target Time registers are programmed only for starting or stopping the generation of the EN0PPS output signal. No interrupt is asserted
End of enumeration elements list.
Ethernet MAC PPS Control
address_offset : 0x72C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_PPSCTRL_PPSCTRL : EN0PPS Output Frequency Control (PPSCTRL) or Command Control (PPSCMD)
bits : 0 - 3 (4 bit)
Enumeration:
0x0 : EMAC_PPSCTRL_PPSCTRL_1HZ
When the PPSEN0 bit = 0x0, the EN0PPS signal is 1 pulse of the PTP reference clock.(of width clk_ptp_i) every second
0x1 : EMAC_PPSCTRL_PPSCTRL_2HZ
When the PPSEN0 bit = 0x0, the binary rollover is 2 Hz, and the digital rollover is 1 Hz
0x2 : EMAC_PPSCTRL_PPSCTRL_4HZ
When the PPSEN0 bit = 0x0, the binary rollover is 4 Hz, and the digital rollover is 2 Hz
0x3 : EMAC_PPSCTRL_PPSCTRL_8HZ
When thePPSEN0 bit = 0x0, the binary rollover is 8 Hz, and the digital rollover is 4 Hz,
0x4 : EMAC_PPSCTRL_PPSCTRL_16HZ
When thePPSEN0 bit = 0x0, the binary rollover is 16 Hz, and the digital rollover is 8 Hz
0x5 : EMAC_PPSCTRL_PPSCTRL_32HZ
When thePPSEN0 bit = 0x0, the binary rollover is 32 Hz, and the digital rollover is 16 Hz
0x6 : EMAC_PPSCTRL_PPSCTRL_64HZ
When thePPSEN0 bit = 0x0, the binary rollover is 64 Hz, and the digital rollover is 32 Hz
0x7 : EMAC_PPSCTRL_PPSCTRL_128HZ
When thePPSEN0 bit = 0x0, the binary rollover is 128 Hz, and the digital rollover is 64 Hz
0x8 : EMAC_PPSCTRL_PPSCTRL_256HZ
When thePPSEN0 bit = 0x0, the binary rollover is 256 Hz, and the digital rollover is 128 Hz
0x9 : EMAC_PPSCTRL_PPSCTRL_512HZ
When thePPSEN0 bit = 0x0, the binary rollover is 512 Hz, and the digital rollover is 256 Hz
0xa : EMAC_PPSCTRL_PPSCTRL_1024HZ
When the PPSEN0 bit = 0x0, the binary rollover is 1.024 kHz, and the digital rollover is 512 Hz
0xb : EMAC_PPSCTRL_PPSCTRL_2048HZ
When thePPSEN0 bit = 0x0, the binary rollover is 2.048 kHz, and the digital rollover is 1.024 kHz
0xc : EMAC_PPSCTRL_PPSCTRL_4096HZ
When thePPSEN0 bit = 0x0, the binary rollover is 4.096 kHz, and the digital rollover is 2.048 kHz
0xd : EMAC_PPSCTRL_PPSCTRL_8192HZ
When thePPSEN0 bit = 0x0, the binary rollover is 8.192 kHz, and the digital rollover is 4.096 kHz
0xe : EMAC_PPSCTRL_PPSCTRL_16384HZ
When thePPSEN0 bit = 0x0, the binary rollover is 16.384 kHz, and the digital rollover is 8.092 kHz
0xf : EMAC_PPSCTRL_PPSCTRL_32768HZ
When thePPSEN0 bit = 0x0, the binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz
End of enumeration elements list.
EMAC_PPSCTRL_PPSEN0 : Flexible PPS Output Mode Enable
bits : 4 - 8 (5 bit)
EMAC_PPSCTRL_TRGMODS0 : Target Time Register Mode for PPS0 Output
bits : 5 - 11 (7 bit)
Enumeration:
0x0 : EMAC_PPSCTRL_TRGMODS0_INTONLY
Indicates that the Target Time registers are programmed only for generating the interrupt event
0x2 : EMAC_PPSCTRL_TRGMODS0_INTPPS0
Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the EN0PPS output signal
0x3 : EMAC_PPSCTRL_TRGMODS0_PPS0ONLY
Indicates that the Target Time registers are programmed only for starting or stopping the generation of the EN0PPS output signal. No interrupt is asserted
End of enumeration elements list.
Ethernet MAC PPS0 Interval
address_offset : 0x760 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_PPS0INTVL_PPS0INT : PPS0 Output Signal Interval
bits : 0 - 31 (32 bit)
Ethernet MAC PPS0 Interval
address_offset : 0x760 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_PPS0INTVL_PPS0INT : PPS0 Output Signal Interval
bits : 0 - 31 (32 bit)
Ethernet MAC PPS0 Width
address_offset : 0x764 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_PPS0WIDTH : EN0PPS Output Signal Width
bits : 0 - 31 (32 bit)
Ethernet MAC PPS0 Width
address_offset : 0x764 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_PPS0WIDTH : EN0PPS Output Signal Width
bits : 0 - 31 (32 bit)
Ethernet MAC Hash Table High
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_HASHTBLH_HTH : Hash Table High
bits : 0 - 31 (32 bit)
Ethernet MAC Hash Table High
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_HASHTBLH_HTH : Hash Table High
bits : 0 - 31 (32 bit)
Ethernet MAC Hash Table Low
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_HASHTBLL_HTL : Hash Table Low
bits : 0 - 31 (32 bit)
Ethernet MAC Hash Table Low
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_HASHTBLL_HTL : Hash Table Low
bits : 0 - 31 (32 bit)
Ethernet MAC DMA Bus Mode
address_offset : 0xC00 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_DMABUSMOD_SWR : DMA Software Reset
bits : 0 - 0 (1 bit)
EMAC_DMABUSMOD_DA : DMA Arbitration Scheme
bits : 1 - 2 (2 bit)
EMAC_DMABUSMOD_DSL : Descriptor Skip Length
bits : 2 - 8 (7 bit)
EMAC_DMABUSMOD_ATDS : Alternate Descriptor Size
bits : 7 - 14 (8 bit)
EMAC_DMABUSMOD_PBL : Programmable Burst Length
bits : 8 - 21 (14 bit)
EMAC_DMABUSMOD_PR : Priority Ratio
bits : 14 - 29 (16 bit)
EMAC_DMABUSMOD_FB : Fixed Burst
bits : 16 - 32 (17 bit)
EMAC_DMABUSMOD_RPBL : RX DMA Programmable Burst Length (PBL)
bits : 17 - 39 (23 bit)
EMAC_DMABUSMOD_USP : Use Separate Programmable Burst Length (PBL)
bits : 23 - 46 (24 bit)
EMAC_DMABUSMOD_8XPBL : 8 x Programmable Burst Length (PBL) Mode
bits : 24 - 48 (25 bit)
EMAC_DMABUSMOD_AAL : Address Aligned Beats
bits : 25 - 50 (26 bit)
EMAC_DMABUSMOD_MB : Mixed Burst
bits : 26 - 52 (27 bit)
EMAC_DMABUSMOD_TXPR : Transmit Priority
bits : 27 - 54 (28 bit)
EMAC_DMABUSMOD_RIB : Rebuild Burst
bits : 31 - 62 (32 bit)
Ethernet MAC DMA Bus Mode
address_offset : 0xC00 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_DMABUSMOD_SWR : DMA Software Reset
bits : 0 - 0 (1 bit)
EMAC_DMABUSMOD_DA : DMA Arbitration Scheme
bits : 1 - 2 (2 bit)
EMAC_DMABUSMOD_DSL : Descriptor Skip Length
bits : 2 - 8 (7 bit)
EMAC_DMABUSMOD_ATDS : Alternate Descriptor Size
bits : 7 - 14 (8 bit)
EMAC_DMABUSMOD_PBL : Programmable Burst Length
bits : 8 - 21 (14 bit)
EMAC_DMABUSMOD_PR : Priority Ratio
bits : 14 - 29 (16 bit)
EMAC_DMABUSMOD_FB : Fixed Burst
bits : 16 - 32 (17 bit)
EMAC_DMABUSMOD_RPBL : RX DMA Programmable Burst Length (PBL)
bits : 17 - 39 (23 bit)
EMAC_DMABUSMOD_USP : Use Separate Programmable Burst Length (PBL)
bits : 23 - 46 (24 bit)
EMAC_DMABUSMOD_8XPBL : 8 x Programmable Burst Length (PBL) Mode
bits : 24 - 48 (25 bit)
EMAC_DMABUSMOD_AAL : Address Aligned Beats
bits : 25 - 50 (26 bit)
EMAC_DMABUSMOD_MB : Mixed Burst
bits : 26 - 52 (27 bit)
EMAC_DMABUSMOD_TXPR : Transmit Priority
bits : 27 - 54 (28 bit)
EMAC_DMABUSMOD_RIB : Rebuild Burst
bits : 31 - 62 (32 bit)
Ethernet MAC Transmit Poll Demand
address_offset : 0xC04 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EMAC_TXPOLLD_TPD : Transmit Poll Demand
bits : 0 - 31 (32 bit)
access : write-only
Ethernet MAC Transmit Poll Demand
address_offset : 0xC04 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EMAC_TXPOLLD_TPD : Transmit Poll Demand
bits : 0 - 31 (32 bit)
access : write-only
Ethernet MAC Receive Poll Demand
address_offset : 0xC08 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EMAC_RXPOLLD_RPD : Receive Poll Demand
bits : 0 - 31 (32 bit)
access : write-only
Ethernet MAC Receive Poll Demand
address_offset : 0xC08 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EMAC_RXPOLLD_RPD : Receive Poll Demand
bits : 0 - 31 (32 bit)
access : write-only
Ethernet MAC Receive Descriptor List Address
address_offset : 0xC0C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_RXDLADDR_STRXLIST : Start of Receive List
bits : 2 - 33 (32 bit)
Ethernet MAC Receive Descriptor List Address
address_offset : 0xC0C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_RXDLADDR_STRXLIST : Start of Receive List
bits : 2 - 33 (32 bit)
Ethernet MAC Transmit Descriptor List Address
address_offset : 0xC10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TXDLADDR_TXDLADDR : Start of Transmit List Base Address
bits : 2 - 33 (32 bit)
Ethernet MAC Transmit Descriptor List Address
address_offset : 0xC10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_TXDLADDR_TXDLADDR : Start of Transmit List Base Address
bits : 2 - 33 (32 bit)
Ethernet MAC DMA Interrupt Status
address_offset : 0xC14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_DMARIS_TI : Transmit Interrupt
bits : 0 - 0 (1 bit)
EMAC_DMARIS_TPS : Transmit Process Stopped
bits : 1 - 2 (2 bit)
EMAC_DMARIS_TU : Transmit Buffer Unavailable
bits : 2 - 4 (3 bit)
EMAC_DMARIS_TJT : Transmit Jabber Timeout
bits : 3 - 6 (4 bit)
EMAC_DMARIS_OVF : Receive Overflow
bits : 4 - 8 (5 bit)
EMAC_DMARIS_UNF : Transmit Underflow
bits : 5 - 10 (6 bit)
EMAC_DMARIS_RI : Receive Interrupt
bits : 6 - 12 (7 bit)
EMAC_DMARIS_RU : Receive Buffer Unavailable
bits : 7 - 14 (8 bit)
EMAC_DMARIS_RPS : Receive Process Stopped
bits : 8 - 16 (9 bit)
EMAC_DMARIS_RWT : Receive Watchdog Timeout
bits : 9 - 18 (10 bit)
EMAC_DMARIS_ETI : Early Transmit Interrupt
bits : 10 - 20 (11 bit)
EMAC_DMARIS_FBI : Fatal Bus Error Interrupt
bits : 13 - 26 (14 bit)
EMAC_DMARIS_ERI : Early Receive Interrupt
bits : 14 - 28 (15 bit)
EMAC_DMARIS_AIS : Abnormal Interrupt Summary
bits : 15 - 30 (16 bit)
EMAC_DMARIS_NIS : Normal Interrupt Summary
bits : 16 - 32 (17 bit)
EMAC_DMARIS_RS : Received Process State
bits : 17 - 36 (20 bit)
Enumeration:
0x0 : EMAC_DMARIS_RS_STOP
Stopped: Reset or stop receive command issued
0x1 : EMAC_DMARIS_RS_RUNRXTD
Running: Fetching receive transfer descriptor
0x3 : EMAC_DMARIS_RS_RUNRXD
Running: Waiting for receive packet
0x4 : EMAC_DMARIS_RS_SUSPEND
Suspended: Receive descriptor unavailable
0x5 : EMAC_DMARIS_RS_RUNCRD
Running: Closing receive descriptor
0x6 : EMAC_DMARIS_RS_TSWS
Writing Timestamp
0x7 : EMAC_DMARIS_RS_RUNTXD
Running: Transferring the receive packet data from receive buffer to host memory
End of enumeration elements list.
EMAC_DMARIS_TS : Transmit Process State
bits : 20 - 42 (23 bit)
Enumeration:
0x0 : EMAC_DMARIS_TS_STOP
Stopped; Reset or Stop transmit command processed
0x1 : EMAC_DMARIS_TS_RUNTXTD
Running; Fetching transmit transfer descriptor
0x2 : EMAC_DMARIS_TS_STATUS
Running; Waiting for status
0x3 : EMAC_DMARIS_TS_RUNTX
Running; Reading data from host memory buffer and queuing it to transmit buffer (TX FIFO)
0x4 : EMAC_DMARIS_TS_TSTAMP
Writing Timestamp
0x6 : EMAC_DMARIS_TS_SUSPEND
Suspended; Transmit descriptor unavailable or transmit buffer underflow
0x7 : EMAC_DMARIS_TS_RUNCTD
Running; Closing transmit descriptor
End of enumeration elements list.
EMAC_DMARIS_AE : Access Error
bits : 23 - 48 (26 bit)
Enumeration:
0x0 : EMAC_DMARIS_AE_RXDMAWD
Error during RX DMA Write Data Transfer
0x3 : EMAC_DMARIS_AE_TXDMARD
Error during TX DMA Read Data Transfer
0x4 : EMAC_DMARIS_AE_RXDMADW
Error during RX DMA Descriptor Write Access
0x5 : EMAC_DMARIS_AE_TXDMADW
Error during TX DMA Descriptor Write Access
0x6 : EMAC_DMARIS_AE_RXDMADR
Error during RX DMA Descriptor Read Access
0x7 : EMAC_DMARIS_AE_TXDMADR
Error during TX DMA Descriptor Read Access
End of enumeration elements list.
EMAC_DMARIS_MMC : MAC MMC Interrupt
bits : 27 - 54 (28 bit)
EMAC_DMARIS_PMT : MAC PMT Interrupt Status
bits : 28 - 56 (29 bit)
EMAC_DMARIS_TT : Timestamp Trigger Interrupt Status
bits : 29 - 58 (30 bit)
Ethernet MAC DMA Interrupt Status
address_offset : 0xC14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_DMARIS_TI : Transmit Interrupt
bits : 0 - 0 (1 bit)
EMAC_DMARIS_TPS : Transmit Process Stopped
bits : 1 - 2 (2 bit)
EMAC_DMARIS_TU : Transmit Buffer Unavailable
bits : 2 - 4 (3 bit)
EMAC_DMARIS_TJT : Transmit Jabber Timeout
bits : 3 - 6 (4 bit)
EMAC_DMARIS_OVF : Receive Overflow
bits : 4 - 8 (5 bit)
EMAC_DMARIS_UNF : Transmit Underflow
bits : 5 - 10 (6 bit)
EMAC_DMARIS_RI : Receive Interrupt
bits : 6 - 12 (7 bit)
EMAC_DMARIS_RU : Receive Buffer Unavailable
bits : 7 - 14 (8 bit)
EMAC_DMARIS_RPS : Receive Process Stopped
bits : 8 - 16 (9 bit)
EMAC_DMARIS_RWT : Receive Watchdog Timeout
bits : 9 - 18 (10 bit)
EMAC_DMARIS_ETI : Early Transmit Interrupt
bits : 10 - 20 (11 bit)
EMAC_DMARIS_FBI : Fatal Bus Error Interrupt
bits : 13 - 26 (14 bit)
EMAC_DMARIS_ERI : Early Receive Interrupt
bits : 14 - 28 (15 bit)
EMAC_DMARIS_AIS : Abnormal Interrupt Summary
bits : 15 - 30 (16 bit)
EMAC_DMARIS_NIS : Normal Interrupt Summary
bits : 16 - 32 (17 bit)
EMAC_DMARIS_RS : Received Process State
bits : 17 - 36 (20 bit)
Enumeration:
0x0 : EMAC_DMARIS_RS_STOP
Stopped: Reset or stop receive command issued
0x1 : EMAC_DMARIS_RS_RUNRXTD
Running: Fetching receive transfer descriptor
0x3 : EMAC_DMARIS_RS_RUNRXD
Running: Waiting for receive packet
0x4 : EMAC_DMARIS_RS_SUSPEND
Suspended: Receive descriptor unavailable
0x5 : EMAC_DMARIS_RS_RUNCRD
Running: Closing receive descriptor
0x6 : EMAC_DMARIS_RS_TSWS
Writing Timestamp
0x7 : EMAC_DMARIS_RS_RUNTXD
Running: Transferring the receive packet data from receive buffer to host memory
End of enumeration elements list.
EMAC_DMARIS_TS : Transmit Process State
bits : 20 - 42 (23 bit)
Enumeration:
0x0 : EMAC_DMARIS_TS_STOP
Stopped Reset or Stop transmit command processed
0x1 : EMAC_DMARIS_TS_RUNTXTD
Running Fetching transmit transfer descriptor
0x2 : EMAC_DMARIS_TS_STATUS
Running Waiting for status
0x3 : EMAC_DMARIS_TS_RUNTX
Running Reading data from host memory buffer and queuing it to transmit buffer (TX FIFO)
0x4 : EMAC_DMARIS_TS_TSTAMP
Writing Timestamp
0x6 : EMAC_DMARIS_TS_SUSPEND
Suspended Transmit descriptor unavailable or transmit buffer underflow
0x7 : EMAC_DMARIS_TS_RUNCTD
Running Closing transmit descriptor
End of enumeration elements list.
EMAC_DMARIS_AE : Access Error
bits : 23 - 48 (26 bit)
Enumeration:
0x0 : EMAC_DMARIS_AE_RXDMAWD
Error during RX DMA Write Data Transfer
0x3 : EMAC_DMARIS_AE_TXDMARD
Error during TX DMA Read Data Transfer
0x4 : EMAC_DMARIS_AE_RXDMADW
Error during RX DMA Descriptor Write Access
0x5 : EMAC_DMARIS_AE_TXDMADW
Error during TX DMA Descriptor Write Access
0x6 : EMAC_DMARIS_AE_RXDMADR
Error during RX DMA Descriptor Read Access
0x7 : EMAC_DMARIS_AE_TXDMADR
Error during TX DMA Descriptor Read Access
End of enumeration elements list.
EMAC_DMARIS_MMC : MAC MMC Interrupt
bits : 27 - 54 (28 bit)
EMAC_DMARIS_PMT : MAC PMT Interrupt Status
bits : 28 - 56 (29 bit)
EMAC_DMARIS_TT : Timestamp Trigger Interrupt Status
bits : 29 - 58 (30 bit)
Ethernet MAC DMA Operation Mode
address_offset : 0xC18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_DMAOPMODE_SR : Start or Stop Receive
bits : 1 - 2 (2 bit)
EMAC_DMAOPMODE_OSF : Operate on Second Frame
bits : 2 - 4 (3 bit)
EMAC_DMAOPMODE_RTC : Receive Threshold Control
bits : 3 - 7 (5 bit)
Enumeration:
0x0 : EMAC_DMAOPMODE_RTC_64
64 bytes
0x1 : EMAC_DMAOPMODE_RTC_32
32 bytes
0x2 : EMAC_DMAOPMODE_RTC_96
96 bytes
0x3 : EMAC_DMAOPMODE_RTC_128
128 bytes
End of enumeration elements list.
EMAC_DMAOPMODE_DGF : Drop Giant Frame Enable
bits : 5 - 10 (6 bit)
EMAC_DMAOPMODE_FUF : Forward Undersized Good Frames
bits : 6 - 12 (7 bit)
EMAC_DMAOPMODE_FEF : Forward Error Frames
bits : 7 - 14 (8 bit)
EMAC_DMAOPMODE_ST : Start or Stop Transmission Command
bits : 13 - 26 (14 bit)
EMAC_DMAOPMODE_TTC : Transmit Threshold Control
bits : 14 - 30 (17 bit)
Enumeration:
0x0 : EMAC_DMAOPMODE_TTC_64
64 bytes
0x1 : EMAC_DMAOPMODE_TTC_128
128 bytes
0x2 : EMAC_DMAOPMODE_TTC_192
192 bytes
0x3 : EMAC_DMAOPMODE_TTC_256
256 bytes
0x4 : EMAC_DMAOPMODE_TTC_40
40 bytes
0x5 : EMAC_DMAOPMODE_TTC_32
32 bytes
0x6 : EMAC_DMAOPMODE_TTC_24
24 bytes
0x7 : EMAC_DMAOPMODE_TTC_16
16 bytes
End of enumeration elements list.
EMAC_DMAOPMODE_FTF : Flush Transmit FIFO
bits : 20 - 40 (21 bit)
EMAC_DMAOPMODE_TSF : Transmit Store and Forward
bits : 21 - 42 (22 bit)
EMAC_DMAOPMODE_DFF : Disable Flushing of Received Frames
bits : 24 - 48 (25 bit)
EMAC_DMAOPMODE_RSF : Receive Store and Forward
bits : 25 - 50 (26 bit)
EMAC_DMAOPMODE_DT : Disable Dropping of TCP/IP Checksum Error Frames
bits : 26 - 52 (27 bit)
Ethernet MAC DMA Operation Mode
address_offset : 0xC18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_DMAOPMODE_SR : Start or Stop Receive
bits : 1 - 2 (2 bit)
EMAC_DMAOPMODE_OSF : Operate on Second Frame
bits : 2 - 4 (3 bit)
EMAC_DMAOPMODE_RTC : Receive Threshold Control
bits : 3 - 7 (5 bit)
Enumeration:
0x0 : EMAC_DMAOPMODE_RTC_64
64 bytes
0x1 : EMAC_DMAOPMODE_RTC_32
32 bytes
0x2 : EMAC_DMAOPMODE_RTC_96
96 bytes
0x3 : EMAC_DMAOPMODE_RTC_128
128 bytes
End of enumeration elements list.
EMAC_DMAOPMODE_DGF : Drop Giant Frame Enable
bits : 5 - 10 (6 bit)
EMAC_DMAOPMODE_FUF : Forward Undersized Good Frames
bits : 6 - 12 (7 bit)
EMAC_DMAOPMODE_FEF : Forward Error Frames
bits : 7 - 14 (8 bit)
EMAC_DMAOPMODE_ST : Start or Stop Transmission Command
bits : 13 - 26 (14 bit)
EMAC_DMAOPMODE_TTC : Transmit Threshold Control
bits : 14 - 30 (17 bit)
Enumeration:
0x0 : EMAC_DMAOPMODE_TTC_64
64 bytes
0x1 : EMAC_DMAOPMODE_TTC_128
128 bytes
0x2 : EMAC_DMAOPMODE_TTC_192
192 bytes
0x3 : EMAC_DMAOPMODE_TTC_256
256 bytes
0x4 : EMAC_DMAOPMODE_TTC_40
40 bytes
0x5 : EMAC_DMAOPMODE_TTC_32
32 bytes
0x6 : EMAC_DMAOPMODE_TTC_24
24 bytes
0x7 : EMAC_DMAOPMODE_TTC_16
16 bytes
End of enumeration elements list.
EMAC_DMAOPMODE_FTF : Flush Transmit FIFO
bits : 20 - 40 (21 bit)
EMAC_DMAOPMODE_TSF : Transmit Store and Forward
bits : 21 - 42 (22 bit)
EMAC_DMAOPMODE_DFF : Disable Flushing of Received Frames
bits : 24 - 48 (25 bit)
EMAC_DMAOPMODE_RSF : Receive Store and Forward
bits : 25 - 50 (26 bit)
EMAC_DMAOPMODE_DT : Disable Dropping of TCP/IP Checksum Error Frames
bits : 26 - 52 (27 bit)
Ethernet MAC DMA Interrupt Mask Register
address_offset : 0xC1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_DMAIM_TIE : Transmit Interrupt Enable
bits : 0 - 0 (1 bit)
EMAC_DMAIM_TSE : Transmit Stopped Enable
bits : 1 - 2 (2 bit)
EMAC_DMAIM_TUE : Transmit Buffer Unvailable Enable
bits : 2 - 4 (3 bit)
EMAC_DMAIM_TJE : Transmit Jabber Timeout Enable
bits : 3 - 6 (4 bit)
EMAC_DMAIM_OVE : Overflow Interrupt Enable
bits : 4 - 8 (5 bit)
EMAC_DMAIM_UNE : Underflow Interrupt Enable
bits : 5 - 10 (6 bit)
EMAC_DMAIM_RIE : Receive Interrupt Enable
bits : 6 - 12 (7 bit)
EMAC_DMAIM_RUE : Receive Buffer Unavailable Enable
bits : 7 - 14 (8 bit)
EMAC_DMAIM_RSE : Receive Stopped Enable
bits : 8 - 16 (9 bit)
EMAC_DMAIM_RWE : Receive Watchdog Timeout Enable
bits : 9 - 18 (10 bit)
EMAC_DMAIM_ETE : Early Transmit Interrupt Enable
bits : 10 - 20 (11 bit)
EMAC_DMAIM_FBE : Fatal Bus Error Enable
bits : 13 - 26 (14 bit)
EMAC_DMAIM_ERE : Early Receive Interrupt Enable
bits : 14 - 28 (15 bit)
EMAC_DMAIM_AIE : Abnormal Interrupt Summary Enable
bits : 15 - 30 (16 bit)
EMAC_DMAIM_NIE : Normal Interrupt Summary Enable
bits : 16 - 32 (17 bit)
Ethernet MAC DMA Interrupt Mask Register
address_offset : 0xC1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_DMAIM_TIE : Transmit Interrupt Enable
bits : 0 - 0 (1 bit)
EMAC_DMAIM_TSE : Transmit Stopped Enable
bits : 1 - 2 (2 bit)
EMAC_DMAIM_TUE : Transmit Buffer Unvailable Enable
bits : 2 - 4 (3 bit)
EMAC_DMAIM_TJE : Transmit Jabber Timeout Enable
bits : 3 - 6 (4 bit)
EMAC_DMAIM_OVE : Overflow Interrupt Enable
bits : 4 - 8 (5 bit)
EMAC_DMAIM_UNE : Underflow Interrupt Enable
bits : 5 - 10 (6 bit)
EMAC_DMAIM_RIE : Receive Interrupt Enable
bits : 6 - 12 (7 bit)
EMAC_DMAIM_RUE : Receive Buffer Unavailable Enable
bits : 7 - 14 (8 bit)
EMAC_DMAIM_RSE : Receive Stopped Enable
bits : 8 - 16 (9 bit)
EMAC_DMAIM_RWE : Receive Watchdog Timeout Enable
bits : 9 - 18 (10 bit)
EMAC_DMAIM_ETE : Early Transmit Interrupt Enable
bits : 10 - 20 (11 bit)
EMAC_DMAIM_FBE : Fatal Bus Error Enable
bits : 13 - 26 (14 bit)
EMAC_DMAIM_ERE : Early Receive Interrupt Enable
bits : 14 - 28 (15 bit)
EMAC_DMAIM_AIE : Abnormal Interrupt Summary Enable
bits : 15 - 30 (16 bit)
EMAC_DMAIM_NIE : Normal Interrupt Summary Enable
bits : 16 - 32 (17 bit)
Ethernet MAC Missed Frame and Buffer Overflow Counter
address_offset : 0xC20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_MFBOC_MISFRMCNT : Missed Frame Counter
bits : 0 - 15 (16 bit)
EMAC_MFBOC_MISCNTOVF : Overflow bit for Missed Frame Counter
bits : 16 - 32 (17 bit)
EMAC_MFBOC_OVFFRMCNT : Overflow Frame Counter
bits : 17 - 44 (28 bit)
EMAC_MFBOC_OVFCNTOVF : Overflow Bit for FIFO Overflow Counter
bits : 28 - 56 (29 bit)
Ethernet MAC Missed Frame and Buffer Overflow Counter
address_offset : 0xC20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_MFBOC_MISFRMCNT : Missed Frame Counter
bits : 0 - 15 (16 bit)
EMAC_MFBOC_MISCNTOVF : Overflow bit for Missed Frame Counter
bits : 16 - 32 (17 bit)
EMAC_MFBOC_OVFFRMCNT : Overflow Frame Counter
bits : 17 - 44 (28 bit)
EMAC_MFBOC_OVFCNTOVF : Overflow Bit for FIFO Overflow Counter
bits : 28 - 56 (29 bit)
Ethernet MAC Receive Interrupt Watchdog Timer
address_offset : 0xC24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_RXINTWDT_RIWT : Receive Interrupt Watchdog Timer Count
bits : 0 - 7 (8 bit)
Ethernet MAC Receive Interrupt Watchdog Timer
address_offset : 0xC24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_RXINTWDT_RIWT : Receive Interrupt Watchdog Timer Count
bits : 0 - 7 (8 bit)
Ethernet MAC Current Host Transmit Descriptor
address_offset : 0xC48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_HOSTXDESC_CURTXDESC : Host Transmit Descriptor Address Pointer
bits : 0 - 31 (32 bit)
Ethernet MAC Current Host Transmit Descriptor
address_offset : 0xC48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_HOSTXDESC_CURTXDESC : Host Transmit Descriptor Address Pointer
bits : 0 - 31 (32 bit)
Ethernet MAC Current Host Receive Descriptor
address_offset : 0xC4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_HOSRXDESC_CURRXDESC : Host Receive Descriptor Address Pointer
bits : 0 - 31 (32 bit)
Ethernet MAC Current Host Receive Descriptor
address_offset : 0xC4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_HOSRXDESC_CURRXDESC : Host Receive Descriptor Address Pointer
bits : 0 - 31 (32 bit)
Ethernet MAC Current Host Transmit Buffer Address
address_offset : 0xC50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_HOSTXBA_CURTXBUFA : Host Transmit Buffer Address Pointer
bits : 0 - 31 (32 bit)
Ethernet MAC Current Host Transmit Buffer Address
address_offset : 0xC50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_HOSTXBA_CURTXBUFA : Host Transmit Buffer Address Pointer
bits : 0 - 31 (32 bit)
Ethernet MAC Current Host Receive Buffer Address
address_offset : 0xC54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_HOSRXBA_CURRXBUFA : Host Receive Buffer Address Pointer
bits : 0 - 31 (32 bit)
Ethernet MAC Current Host Receive Buffer Address
address_offset : 0xC54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_HOSRXBA_CURRXBUFA : Host Receive Buffer Address Pointer
bits : 0 - 31 (32 bit)
Ethernet MAC Watchdog Timeout
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_WDOGTO_WTO : Watchdog Timeout
bits : 0 - 13 (14 bit)
EMAC_WDOGTO_PWE : Programmable Watchdog Enable
bits : 16 - 32 (17 bit)
Ethernet MAC Watchdog Timeout
address_offset : 0xDC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_WDOGTO_WTO : Watchdog Timeout
bits : 0 - 13 (14 bit)
EMAC_WDOGTO_PWE : Programmable Watchdog Enable
bits : 16 - 32 (17 bit)
Ethernet MAC Peripheral Property Register
address_offset : 0xFC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_PP_PHYTYPE : Ethernet PHY Type
bits : 0 - 2 (3 bit)
Enumeration:
0x0 : EMAC_PP_PHYTYPE_NONE
No PHY
0x3 : EMAC_PP_PHYTYPE_1
Snowflake class PHY
End of enumeration elements list.
EMAC_PP_MACTYPE : Ethernet MAC Type
bits : 8 - 18 (11 bit)
Ethernet MAC Peripheral Property Register
address_offset : 0xFC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_PP_PHYTYPE : Ethernet PHY Type
bits : 0 - 2 (3 bit)
Enumeration:
0x0 : EMAC_PP_PHYTYPE_NONE
No PHY
0x3 : EMAC_PP_PHYTYPE_1
Snowflake class PHY
End of enumeration elements list.
EMAC_PP_MACTYPE : Ethernet MAC Type
bits : 8 - 18 (11 bit)
Ethernet MAC Peripheral Configuration Register
address_offset : 0xFC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_PC_PHYHOLD : Ethernet PHY Hold
bits : 0 - 0 (1 bit)
EMAC_PC_ANMODE : Auto Negotiation Mode
bits : 1 - 3 (3 bit)
Enumeration:
0x0 : EMAC_PC_ANMODE_10HD
When ANEN = 0x0, the mode is 10Base-T, Half-Duplex
0x1 : EMAC_PC_ANMODE_10FD
When ANEN = 0x0, the mode is 10Base-T, Full-Duplex
0x2 : EMAC_PC_ANMODE_100HD
When ANEN = 0x0, the mode is 100Base-TX, Half-Duplex
0x3 : EMAC_PC_ANMODE_100FD
When ANEN = 0x0, the mode is 100Base-TX, Full-Duplex
End of enumeration elements list.
EMAC_PC_ANEN : Auto Negotiation Enable
bits : 3 - 6 (4 bit)
EMAC_PC_FASTANSEL : Fast Auto Negotiation Select
bits : 4 - 9 (6 bit)
EMAC_PC_FASTANEN : Fast Auto Negotiation Enable
bits : 6 - 12 (7 bit)
EMAC_PC_EXTFD : Extended Full Duplex Ability
bits : 7 - 14 (8 bit)
EMAC_PC_FASTLUPD : FAST Link-Up in Parallel Detect
bits : 8 - 16 (9 bit)
EMAC_PC_FASTRXDV : Fast RXDV Detection
bits : 9 - 18 (10 bit)
EMAC_PC_MDIXEN : MDIX Enable
bits : 10 - 20 (11 bit)
EMAC_PC_FASTMDIX : Fast Auto MDI-X
bits : 11 - 22 (12 bit)
EMAC_PC_RBSTMDIX : Robust Auto MDI-X
bits : 12 - 24 (13 bit)
EMAC_PC_MDISWAP : MDI Swap
bits : 13 - 26 (14 bit)
EMAC_PC_POLSWAP : Polarity Swap
bits : 14 - 28 (15 bit)
EMAC_PC_FASTLDMODE : Fast Link Down Mode
bits : 15 - 34 (20 bit)
EMAC_PC_TDRRUN : TDR Auto Run
bits : 20 - 40 (21 bit)
EMAC_PC_LRR : Link Loss Recovery
bits : 21 - 42 (22 bit)
EMAC_PC_ISOMIILL : Isolate MII in Link Loss
bits : 22 - 44 (23 bit)
EMAC_PC_RXERIDLE : RXER Detection During Idle
bits : 23 - 46 (24 bit)
EMAC_PC_NIBDETDIS : Odd Nibble TXER Detection Disable
bits : 24 - 48 (25 bit)
EMAC_PC_DIGRESTART : PHY Soft Restart
bits : 25 - 50 (26 bit)
EMAC_PC_PINTFS : Ethernet Interface Select
bits : 28 - 58 (31 bit)
Enumeration:
0x0 : EMAC_PC_PINTFS_IMII
MII (default) Used for internal PHY or external PHY connected via MII
0x4 : EMAC_PC_PINTFS_RMII
RMII: Used for external PHY connected via RMII
End of enumeration elements list.
EMAC_PC_PHYEXT : PHY Select
bits : 31 - 62 (32 bit)
Ethernet MAC Peripheral Configuration Register
address_offset : 0xFC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_PC_PHYHOLD : Ethernet PHY Hold
bits : 0 - 0 (1 bit)
EMAC_PC_ANMODE : Auto Negotiation Mode
bits : 1 - 3 (3 bit)
Enumeration:
0x0 : EMAC_PC_ANMODE_10HD
When ANEN = 0x0, the mode is 10Base-T, Half-Duplex
0x1 : EMAC_PC_ANMODE_10FD
When ANEN = 0x0, the mode is 10Base-T, Full-Duplex
0x2 : EMAC_PC_ANMODE_100HD
When ANEN = 0x0, the mode is 100Base-TX, Half-Duplex
0x3 : EMAC_PC_ANMODE_100FD
When ANEN = 0x0, the mode is 100Base-TX, Full-Duplex
End of enumeration elements list.
EMAC_PC_ANEN : Auto Negotiation Enable
bits : 3 - 6 (4 bit)
EMAC_PC_FASTANSEL : Fast Auto Negotiation Select
bits : 4 - 9 (6 bit)
EMAC_PC_FASTANEN : Fast Auto Negotiation Enable
bits : 6 - 12 (7 bit)
EMAC_PC_EXTFD : Extended Full Duplex Ability
bits : 7 - 14 (8 bit)
EMAC_PC_FASTLUPD : FAST Link-Up in Parallel Detect
bits : 8 - 16 (9 bit)
EMAC_PC_FASTRXDV : Fast RXDV Detection
bits : 9 - 18 (10 bit)
EMAC_PC_MDIXEN : MDIX Enable
bits : 10 - 20 (11 bit)
EMAC_PC_FASTMDIX : Fast Auto MDI-X
bits : 11 - 22 (12 bit)
EMAC_PC_RBSTMDIX : Robust Auto MDI-X
bits : 12 - 24 (13 bit)
EMAC_PC_MDISWAP : MDI Swap
bits : 13 - 26 (14 bit)
EMAC_PC_POLSWAP : Polarity Swap
bits : 14 - 28 (15 bit)
EMAC_PC_FASTLDMODE : Fast Link Down Mode
bits : 15 - 34 (20 bit)
EMAC_PC_TDRRUN : TDR Auto Run
bits : 20 - 40 (21 bit)
EMAC_PC_LRR : Link Loss Recovery
bits : 21 - 42 (22 bit)
EMAC_PC_ISOMIILL : Isolate MII in Link Loss
bits : 22 - 44 (23 bit)
EMAC_PC_RXERIDLE : RXER Detection During Idle
bits : 23 - 46 (24 bit)
EMAC_PC_NIBDETDIS : Odd Nibble TXER Detection Disable
bits : 24 - 48 (25 bit)
EMAC_PC_DIGRESTART : PHY Soft Restart
bits : 25 - 50 (26 bit)
EMAC_PC_PINTFS : Ethernet Interface Select
bits : 28 - 58 (31 bit)
Enumeration:
0x0 : EMAC_PC_PINTFS_IMII
MII (default) Used for internal PHY or external PHY connected via MII
0x4 : EMAC_PC_PINTFS_RMII
RMII: Used for external PHY connected via RMII
End of enumeration elements list.
EMAC_PC_PHYEXT : PHY Select
bits : 31 - 62 (32 bit)
Ethernet MAC Clock Configuration Register
address_offset : 0xFC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_CC_POL : LED Polarity Control
bits : 17 - 34 (18 bit)
EMAC_CC_PTPCEN : PTP Clock Reference Enable
bits : 18 - 36 (19 bit)
Ethernet MAC Clock Configuration Register
address_offset : 0xFC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMAC_CC_POL : LED Polarity Control
bits : 17 - 34 (18 bit)
EMAC_CC_PTPCEN : PTP Clock Reference Enable
bits : 18 - 36 (19 bit)
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