Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Device Identification 0
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DID0_MIN : Minor Revision
bits : 0 - 7 (8 bit)
Enumeration:
0x0 : SYSCTL_DID0_MIN_0
Initial device, or a major revision update
0x1 : SYSCTL_DID0_MIN_1
First metal layer change
0x2 : SYSCTL_DID0_MIN_2
Second metal layer change
End of enumeration elements list.
SYSCTL_DID0_MAJ : Major Revision
bits : 8 - 23 (16 bit)
Enumeration:
0x0 : SYSCTL_DID0_MAJ_REVA
Revision A (initial device)
0x1 : SYSCTL_DID0_MAJ_REVB
Revision B (first base layer revision)
0x2 : SYSCTL_DID0_MAJ_REVC
Revision C (second base layer revision)
End of enumeration elements list.
SYSCTL_DID0_CLASS : Device Class
bits : 16 - 39 (24 bit)
Enumeration:
0xa : SYSCTL_DID0_CLASS_TM4C129
Tiva(TM) TM4C129-class microcontrollers
End of enumeration elements list.
SYSCTL_DID0_VER : DID0 Version
bits : 28 - 58 (31 bit)
Enumeration:
0x1 : SYSCTL_DID0_VER_1
Second version of the DID0 register format.
End of enumeration elements list.
Device Identification 0
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DID0_MIN : Minor Revision
bits : 0 - 7 (8 bit)
Enumeration:
0x0 : SYSCTL_DID0_MIN_0
Initial device, or a major revision update
0x1 : SYSCTL_DID0_MIN_1
First metal layer change
0x2 : SYSCTL_DID0_MIN_2
Second metal layer change
End of enumeration elements list.
SYSCTL_DID0_MAJ : Major Revision
bits : 8 - 23 (16 bit)
Enumeration:
0x0 : SYSCTL_DID0_MAJ_REVA
Revision A (initial device)
0x1 : SYSCTL_DID0_MAJ_REVB
Revision B (first base layer revision)
0x2 : SYSCTL_DID0_MAJ_REVC
Revision C (second base layer revision)
End of enumeration elements list.
SYSCTL_DID0_CLASS : Device Class
bits : 16 - 39 (24 bit)
Enumeration:
0xa : SYSCTL_DID0_CLASS_TM4C129
Tiva(TM) TM4C129-class microcontrollers
End of enumeration elements list.
SYSCTL_DID0_VER : DID0 Version
bits : 28 - 58 (31 bit)
Enumeration:
0x1 : SYSCTL_DID0_VER_1
Second version of the DID0 register format.
End of enumeration elements list.
Alternate Clock Configuration
address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_ALTCLKCFG_ALTCLK : Alternate Clock Source
bits : 0 - 3 (4 bit)
Enumeration:
0x0 : SYSCTL_ALTCLKCFG_ALTCLK_PIOSC
PIOSC
0x3 : SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC
Hibernation Module Real-time clock output (RTCOSC)
0x4 : SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC
Low-frequency internal oscillator (LFIOSC)
End of enumeration elements list.
Alternate Clock Configuration
address_offset : 0x138 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_ALTCLKCFG_ALTCLK : Alternate Clock Source
bits : 0 - 3 (4 bit)
Enumeration:
0x0 : SYSCTL_ALTCLKCFG_ALTCLK_PIOSC
PIOSC
0x3 : SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC
Hibernation Module Real-time clock output (RTCOSC)
0x4 : SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC
Low-frequency internal oscillator (LFIOSC)
End of enumeration elements list.
Deep Sleep Clock Configuration Register
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DSCLKCFG_DSSYSDIV : Deep Sleep Clock Divisor
bits : 0 - 9 (10 bit)
SYSCTL_DSCLKCFG_DSOSCSRC : Deep Sleep Oscillator Source
bits : 20 - 43 (24 bit)
Enumeration:
0x0 : SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC
PIOSC
0x2 : SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC
LFIOSC
0x3 : SYSCTL_DSCLKCFG_DSOSCSRC_MOSC
MOSC
0x4 : SYSCTL_DSCLKCFG_DSOSCSRC_RTC
Hibernation Module RTCOSC
End of enumeration elements list.
SYSCTL_DSCLKCFG_MOSCDPD : MOSC Disable Power Down
bits : 30 - 60 (31 bit)
SYSCTL_DSCLKCFG_PIOSCPD : PIOSC Power Down
bits : 31 - 62 (32 bit)
Deep Sleep Clock Configuration Register
address_offset : 0x144 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DSCLKCFG_DSSYSDIV : Deep Sleep Clock Divisor
bits : 0 - 9 (10 bit)
SYSCTL_DSCLKCFG_DSOSCSRC : Deep Sleep Oscillator Source
bits : 20 - 43 (24 bit)
Enumeration:
0x0 : SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC
PIOSC
0x2 : SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC
LFIOSC
0x3 : SYSCTL_DSCLKCFG_DSOSCSRC_MOSC
MOSC
0x4 : SYSCTL_DSCLKCFG_DSOSCSRC_RTC
Hibernation Module RTCOSC
End of enumeration elements list.
SYSCTL_DSCLKCFG_MOSCDPD : MOSC Disable Power Down
bits : 30 - 60 (31 bit)
SYSCTL_DSCLKCFG_PIOSCPD : PIOSC Power Down
bits : 31 - 62 (32 bit)
Divisor and Source Clock Configuration
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DIVSCLK_DIV : Divisor Value
bits : 0 - 7 (8 bit)
SYSCTL_DIVSCLK_SRC : Clock Source
bits : 16 - 33 (18 bit)
Enumeration:
0x0 : SYSCTL_DIVSCLK_SRC_SYSCLK
System Clock
0x1 : SYSCTL_DIVSCLK_SRC_PIOSC
PIOSC
0x2 : SYSCTL_DIVSCLK_SRC_MOSC
MOSC
End of enumeration elements list.
SYSCTL_DIVSCLK_EN : DIVSCLK Enable
bits : 31 - 62 (32 bit)
Divisor and Source Clock Configuration
address_offset : 0x148 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DIVSCLK_DIV : Divisor Value
bits : 0 - 7 (8 bit)
SYSCTL_DIVSCLK_SRC : Clock Source
bits : 16 - 33 (18 bit)
Enumeration:
0x0 : SYSCTL_DIVSCLK_SRC_SYSCLK
System Clock
0x1 : SYSCTL_DIVSCLK_SRC_PIOSC
PIOSC
0x2 : SYSCTL_DIVSCLK_SRC_MOSC
MOSC
End of enumeration elements list.
SYSCTL_DIVSCLK_EN : DIVSCLK Enable
bits : 31 - 62 (32 bit)
System Properties
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SYSPROP_FPU : FPU Present
bits : 0 - 0 (1 bit)
System Properties
address_offset : 0x14C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SYSPROP_FPU : FPU Present
bits : 0 - 0 (1 bit)
Precision Internal Oscillator Calibration
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PIOSCCAL_UT : User Trim Value
bits : 0 - 6 (7 bit)
SYSCTL_PIOSCCAL_UPDATE : Update Trim
bits : 8 - 16 (9 bit)
SYSCTL_PIOSCCAL_CAL : Start Calibration
bits : 9 - 18 (10 bit)
SYSCTL_PIOSCCAL_UTEN : Use User Trim Value
bits : 31 - 62 (32 bit)
Precision Internal Oscillator Calibration
address_offset : 0x150 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PIOSCCAL_UT : User Trim Value
bits : 0 - 6 (7 bit)
SYSCTL_PIOSCCAL_UPDATE : Update Trim
bits : 8 - 16 (9 bit)
SYSCTL_PIOSCCAL_CAL : Start Calibration
bits : 9 - 18 (10 bit)
SYSCTL_PIOSCCAL_UTEN : Use User Trim Value
bits : 31 - 62 (32 bit)
Precision Internal Oscillator Statistics
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PIOSCSTAT_CT : Calibration Trim Value
bits : 0 - 6 (7 bit)
SYSCTL_PIOSCSTAT_CR : Calibration Result
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : SYSCTL_PIOSCSTAT_CRNONE
Calibration has not been attempted
0x1 : SYSCTL_PIOSCSTAT_CRPASS
The last calibration operation completed to meet 1% accuracy
0x2 : SYSCTL_PIOSCSTAT_CRFAIL
The last calibration operation failed to meet 1% accuracy
End of enumeration elements list.
SYSCTL_PIOSCSTAT_DT : Default Trim Value
bits : 16 - 38 (23 bit)
Precision Internal Oscillator Statistics
address_offset : 0x154 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PIOSCSTAT_CT : Calibration Trim Value
bits : 0 - 6 (7 bit)
SYSCTL_PIOSCSTAT_CR : Calibration Result
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : SYSCTL_PIOSCSTAT_CRNONE
Calibration has not been attempted
0x1 : SYSCTL_PIOSCSTAT_CRPASS
The last calibration operation completed to meet 1% accuracy
0x2 : SYSCTL_PIOSCSTAT_CRFAIL
The last calibration operation failed to meet 1% accuracy
End of enumeration elements list.
SYSCTL_PIOSCSTAT_DT : Default Trim Value
bits : 16 - 38 (23 bit)
PLL Frequency 0
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PLLFREQ0_MINT : PLL M Integer Value
bits : 0 - 9 (10 bit)
SYSCTL_PLLFREQ0_MFRAC : PLL M Fractional Value
bits : 10 - 29 (20 bit)
SYSCTL_PLLFREQ0_PLLPWR : PLL Power
bits : 23 - 46 (24 bit)
PLL Frequency 0
address_offset : 0x160 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PLLFREQ0_MINT : PLL M Integer Value
bits : 0 - 9 (10 bit)
SYSCTL_PLLFREQ0_MFRAC : PLL M Fractional Value
bits : 10 - 29 (20 bit)
SYSCTL_PLLFREQ0_PLLPWR : PLL Power
bits : 23 - 46 (24 bit)
PLL Frequency 1
address_offset : 0x164 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PLLFREQ1_N : PLL N Value
bits : 0 - 4 (5 bit)
SYSCTL_PLLFREQ1_Q : PLL Q Value
bits : 8 - 20 (13 bit)
PLL Frequency 1
address_offset : 0x164 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PLLFREQ1_N : PLL N Value
bits : 0 - 4 (5 bit)
SYSCTL_PLLFREQ1_Q : PLL Q Value
bits : 8 - 20 (13 bit)
PLL Status
address_offset : 0x168 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PLLSTAT_LOCK : PLL Lock
bits : 0 - 0 (1 bit)
PLL Status
address_offset : 0x168 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PLLSTAT_LOCK : PLL Lock
bits : 0 - 0 (1 bit)
Sleep Power Configuration
address_offset : 0x188 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SLPPWRCFG_SRAMPM : SRAM Power Modes
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : SYSCTL_SLPPWRCFG_SRAMPM_NRM
Active Mode
0x1 : SYSCTL_SLPPWRCFG_SRAMPM_SBY
Standby Mode
0x3 : SYSCTL_SLPPWRCFG_SRAMPM_LP
Low Power Mode
End of enumeration elements list.
SYSCTL_SLPPWRCFG_FLASHPM : Flash Power Modes
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : SYSCTL_SLPPWRCFG_FLASHPM_NRM
Active Mode
0x2 : SYSCTL_SLPPWRCFG_FLASHPM_SLP
Low Power Mode
End of enumeration elements list.
Sleep Power Configuration
address_offset : 0x188 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SLPPWRCFG_SRAMPM : SRAM Power Modes
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : SYSCTL_SLPPWRCFG_SRAMPM_NRM
Active Mode
0x1 : SYSCTL_SLPPWRCFG_SRAMPM_SBY
Standby Mode
0x3 : SYSCTL_SLPPWRCFG_SRAMPM_LP
Low Power Mode
End of enumeration elements list.
SYSCTL_SLPPWRCFG_FLASHPM : Flash Power Modes
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : SYSCTL_SLPPWRCFG_FLASHPM_NRM
Active Mode
0x2 : SYSCTL_SLPPWRCFG_FLASHPM_SLP
Low Power Mode
End of enumeration elements list.
Deep-Sleep Power Configuration
address_offset : 0x18C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DSLPPWRCFG_SRAMPM : SRAM Power Modes
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : SYSCTL_DSLPPWRCFG_SRAMPM_NRM
Active Mode
0x1 : SYSCTL_DSLPPWRCFG_SRAMPM_SBY
Standby Mode
0x3 : SYSCTL_DSLPPWRCFG_SRAMPM_LP
Low Power Mode
End of enumeration elements list.
SYSCTL_DSLPPWRCFG_FLASHPM : Flash Power Modes
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : SYSCTL_DSLPPWRCFG_FLASHPM_NRM
Active Mode
0x2 : SYSCTL_DSLPPWRCFG_FLASHPM_SLP
Low Power Mode
End of enumeration elements list.
SYSCTL_DSLPPWRCFG_TSPD : Temperature Sense Power Down
bits : 8 - 16 (9 bit)
SYSCTL_DSLPPWRCFG_LDOSM : LDO Sleep Mode
bits : 9 - 18 (10 bit)
Deep-Sleep Power Configuration
address_offset : 0x18C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DSLPPWRCFG_SRAMPM : SRAM Power Modes
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : SYSCTL_DSLPPWRCFG_SRAMPM_NRM
Active Mode
0x1 : SYSCTL_DSLPPWRCFG_SRAMPM_SBY
Standby Mode
0x3 : SYSCTL_DSLPPWRCFG_SRAMPM_LP
Low Power Mode
End of enumeration elements list.
SYSCTL_DSLPPWRCFG_FLASHPM : Flash Power Modes
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : SYSCTL_DSLPPWRCFG_FLASHPM_NRM
Active Mode
0x2 : SYSCTL_DSLPPWRCFG_FLASHPM_SLP
Low Power Mode
End of enumeration elements list.
SYSCTL_DSLPPWRCFG_TSPD : Temperature Sense Power Down
bits : 8 - 16 (9 bit)
SYSCTL_DSLPPWRCFG_LDOSM : LDO Sleep Mode
bits : 9 - 18 (10 bit)
Non-Volatile Memory Information
address_offset : 0x1A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_NVMSTAT_FWB : 32 Word Flash Write Buffer Available
bits : 0 - 0 (1 bit)
Non-Volatile Memory Information
address_offset : 0x1A0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_NVMSTAT_FWB : 32 Word Flash Write Buffer Available
bits : 0 - 0 (1 bit)
LDO Sleep Power Control
address_offset : 0x1B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_LDOSPCTL_VLDO : LDO Output Voltage
bits : 0 - 7 (8 bit)
Enumeration:
0x12 : SYSCTL_LDOSPCTL_VLDO_0_90V
0.90 V
0x13 : SYSCTL_LDOSPCTL_VLDO_0_95V
0.95 V
0x14 : SYSCTL_LDOSPCTL_VLDO_1_00V
1.00 V
0x15 : SYSCTL_LDOSPCTL_VLDO_1_05V
1.05 V
0x16 : SYSCTL_LDOSPCTL_VLDO_1_10V
1.10 V
0x17 : SYSCTL_LDOSPCTL_VLDO_1_15V
1.15 V
0x18 : SYSCTL_LDOSPCTL_VLDO_1_20V
1.20 V
End of enumeration elements list.
SYSCTL_LDOSPCTL_VADJEN : Voltage Adjust Enable
bits : 31 - 62 (32 bit)
LDO Sleep Power Control
address_offset : 0x1B4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_LDOSPCTL_VLDO : LDO Output Voltage
bits : 0 - 7 (8 bit)
Enumeration:
0x12 : SYSCTL_LDOSPCTL_VLDO_0_90V
0.90 V
0x13 : SYSCTL_LDOSPCTL_VLDO_0_95V
0.95 V
0x14 : SYSCTL_LDOSPCTL_VLDO_1_00V
1.00 V
0x15 : SYSCTL_LDOSPCTL_VLDO_1_05V
1.05 V
0x16 : SYSCTL_LDOSPCTL_VLDO_1_10V
1.10 V
0x17 : SYSCTL_LDOSPCTL_VLDO_1_15V
1.15 V
0x18 : SYSCTL_LDOSPCTL_VLDO_1_20V
1.20 V
End of enumeration elements list.
SYSCTL_LDOSPCTL_VADJEN : Voltage Adjust Enable
bits : 31 - 62 (32 bit)
LDO Deep-Sleep Power Control
address_offset : 0x1BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_LDODPCTL_VLDO : LDO Output Voltage
bits : 0 - 7 (8 bit)
Enumeration:
0x12 : SYSCTL_LDODPCTL_VLDO_0_90V
0.90 V
0x13 : SYSCTL_LDODPCTL_VLDO_0_95V
0.95 V
0x14 : SYSCTL_LDODPCTL_VLDO_1_00V
1.00 V
0x15 : SYSCTL_LDODPCTL_VLDO_1_05V
1.05 V
0x16 : SYSCTL_LDODPCTL_VLDO_1_10V
1.10 V
0x17 : SYSCTL_LDODPCTL_VLDO_1_15V
1.15 V
0x18 : SYSCTL_LDODPCTL_VLDO_1_20V
1.20 V
0x19 : SYSCTL_LDODPCTL_VLDO_1_25V
1.25 V
0x1a : SYSCTL_LDODPCTL_VLDO_1_30V
1.30 V
0x1b : SYSCTL_LDODPCTL_VLDO_1_35V
1.35 V
End of enumeration elements list.
SYSCTL_LDODPCTL_VADJEN : Voltage Adjust Enable
bits : 31 - 62 (32 bit)
LDO Deep-Sleep Power Control
address_offset : 0x1BC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_LDODPCTL_VLDO : LDO Output Voltage
bits : 0 - 7 (8 bit)
Enumeration:
0x12 : SYSCTL_LDODPCTL_VLDO_0_90V
0.90 V
0x13 : SYSCTL_LDODPCTL_VLDO_0_95V
0.95 V
0x14 : SYSCTL_LDODPCTL_VLDO_1_00V
1.00 V
0x15 : SYSCTL_LDODPCTL_VLDO_1_05V
1.05 V
0x16 : SYSCTL_LDODPCTL_VLDO_1_10V
1.10 V
0x17 : SYSCTL_LDODPCTL_VLDO_1_15V
1.15 V
0x18 : SYSCTL_LDODPCTL_VLDO_1_20V
1.20 V
0x19 : SYSCTL_LDODPCTL_VLDO_1_25V
1.25 V
0x1a : SYSCTL_LDODPCTL_VLDO_1_30V
1.30 V
0x1b : SYSCTL_LDODPCTL_VLDO_1_35V
1.35 V
End of enumeration elements list.
SYSCTL_LDODPCTL_VADJEN : Voltage Adjust Enable
bits : 31 - 62 (32 bit)
Reset Behavior Control Register
address_offset : 0x1D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RESBEHAVCTL_EXTRES : External RST Pin Operation
bits : 0 - 1 (2 bit)
Enumeration:
0x2 : SYSCTL_RESBEHAVCTL_EXTRES_SYSRST
External RST assertion issues a system reset. The application starts within 10 us
0x3 : SYSCTL_RESBEHAVCTL_EXTRES_POR
External RST assertion issues a simulated POR sequence. Application starts less than 500 us after deassertion (Default)
End of enumeration elements list.
SYSCTL_RESBEHAVCTL_BOR : BOR Reset operation
bits : 2 - 5 (4 bit)
Enumeration:
0x2 : SYSCTL_RESBEHAVCTL_BOR_SYSRST
Brown Out Reset issues system reset. The application starts within 10 us
0x3 : SYSCTL_RESBEHAVCTL_BOR_POR
Brown Out Reset issues a simulated POR sequence. The application starts less than 500 us after deassertion (Default)
End of enumeration elements list.
SYSCTL_RESBEHAVCTL_WDOG0 : Watchdog 0 Reset Operation
bits : 4 - 9 (6 bit)
Enumeration:
0x2 : SYSCTL_RESBEHAVCTL_WDOG0_SYSRST
Watchdog 0 issues a system reset. The application starts within 10 us
0x3 : SYSCTL_RESBEHAVCTL_WDOG0_POR
Watchdog 0 issues a simulated POR sequence. Application starts less than 500 us after deassertion (Default)
End of enumeration elements list.
SYSCTL_RESBEHAVCTL_WDOG1 : Watchdog 1 Reset Operation
bits : 6 - 13 (8 bit)
Enumeration:
0x2 : SYSCTL_RESBEHAVCTL_WDOG1_SYSRST
Watchdog 1 issues a system reset. The application starts within 10 us
0x3 : SYSCTL_RESBEHAVCTL_WDOG1_POR
Watchdog 1 issues a simulated POR sequence. Application starts less than 500 us after deassertion (Default)
End of enumeration elements list.
Reset Behavior Control Register
address_offset : 0x1D8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RESBEHAVCTL_EXTRES : External RST Pin Operation
bits : 0 - 1 (2 bit)
Enumeration:
0x2 : SYSCTL_RESBEHAVCTL_EXTRES_SYSRST
External RST assertion issues a system reset. The application starts within 10 us
0x3 : SYSCTL_RESBEHAVCTL_EXTRES_POR
External RST assertion issues a simulated POR sequence. Application starts less than 500 us after deassertion (Default)
End of enumeration elements list.
SYSCTL_RESBEHAVCTL_BOR : BOR Reset operation
bits : 2 - 5 (4 bit)
Enumeration:
0x2 : SYSCTL_RESBEHAVCTL_BOR_SYSRST
Brown Out Reset issues system reset. The application starts within 10 us
0x3 : SYSCTL_RESBEHAVCTL_BOR_POR
Brown Out Reset issues a simulated POR sequence. The application starts less than 500 us after deassertion (Default)
End of enumeration elements list.
SYSCTL_RESBEHAVCTL_WDOG0 : Watchdog 0 Reset Operation
bits : 4 - 9 (6 bit)
Enumeration:
0x2 : SYSCTL_RESBEHAVCTL_WDOG0_SYSRST
Watchdog 0 issues a system reset. The application starts within 10 us
0x3 : SYSCTL_RESBEHAVCTL_WDOG0_POR
Watchdog 0 issues a simulated POR sequence. Application starts less than 500 us after deassertion (Default)
End of enumeration elements list.
SYSCTL_RESBEHAVCTL_WDOG1 : Watchdog 1 Reset Operation
bits : 6 - 13 (8 bit)
Enumeration:
0x2 : SYSCTL_RESBEHAVCTL_WDOG1_SYSRST
Watchdog 1 issues a system reset. The application starts within 10 us
0x3 : SYSCTL_RESBEHAVCTL_WDOG1_POR
Watchdog 1 issues a simulated POR sequence. Application starts less than 500 us after deassertion (Default)
End of enumeration elements list.
Hardware System Service Request
address_offset : 0x1F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_HSSR_CDOFF : Command Descriptor Pointer
bits : 0 - 23 (24 bit)
SYSCTL_HSSR_KEY : Write Key
bits : 24 - 55 (32 bit)
Hardware System Service Request
address_offset : 0x1F4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_HSSR_CDOFF : Command Descriptor Pointer
bits : 0 - 23 (24 bit)
SYSCTL_HSSR_KEY : Write Key
bits : 24 - 55 (32 bit)
USB Power Domain Status
address_offset : 0x280 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_USBPDS_PWRSTAT : Power Domain Status
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : SYSCTL_USBPDS_PWRSTAT_OFF
OFF
0x3 : SYSCTL_USBPDS_PWRSTAT_ON
ON
End of enumeration elements list.
SYSCTL_USBPDS_MEMSTAT : Memory Array Power Status
bits : 2 - 5 (4 bit)
Enumeration:
0x0 : SYSCTL_USBPDS_MEMSTAT_OFF
Array OFF
0x1 : SYSCTL_USBPDS_MEMSTAT_RETAIN
SRAM Retention
0x3 : SYSCTL_USBPDS_MEMSTAT_ON
Array On
End of enumeration elements list.
USB Power Domain Status
address_offset : 0x280 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_USBPDS_PWRSTAT : Power Domain Status
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : SYSCTL_USBPDS_PWRSTAT_OFF
OFF
0x3 : SYSCTL_USBPDS_PWRSTAT_ON
ON
End of enumeration elements list.
SYSCTL_USBPDS_MEMSTAT : Memory Array Power Status
bits : 2 - 5 (4 bit)
Enumeration:
0x0 : SYSCTL_USBPDS_MEMSTAT_OFF
Array OFF
0x1 : SYSCTL_USBPDS_MEMSTAT_RETAIN
SRAM Retention
0x3 : SYSCTL_USBPDS_MEMSTAT_ON
Array On
End of enumeration elements list.
USB Memory Power Control
address_offset : 0x284 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_USBMPC_PWRCTL : Memory Array Power Control
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : SYSCTL_USBMPC_PWRCTL_OFF
Array OFF
0x1 : SYSCTL_USBMPC_PWRCTL_RETAIN
SRAM Retention
0x3 : SYSCTL_USBMPC_PWRCTL_ON
Array On
End of enumeration elements list.
USB Memory Power Control
address_offset : 0x284 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_USBMPC_PWRCTL : Memory Array Power Control
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : SYSCTL_USBMPC_PWRCTL_OFF
Array OFF
0x1 : SYSCTL_USBMPC_PWRCTL_RETAIN
SRAM Retention
0x3 : SYSCTL_USBMPC_PWRCTL_ON
Array On
End of enumeration elements list.
Ethernet MAC Power Domain Status
address_offset : 0x288 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_EMACPDS_PWRSTAT : Power Domain Status
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : SYSCTL_EMACPDS_PWRSTAT_OFF
OFF
0x3 : SYSCTL_EMACPDS_PWRSTAT_ON
ON
End of enumeration elements list.
SYSCTL_EMACPDS_MEMSTAT : Memory Array Power Status
bits : 2 - 5 (4 bit)
Enumeration:
0x0 : SYSCTL_EMACPDS_MEMSTAT_OFF
Array OFF
0x3 : SYSCTL_EMACPDS_MEMSTAT_ON
Array On
End of enumeration elements list.
Ethernet MAC Power Domain Status
address_offset : 0x288 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_EMACPDS_PWRSTAT : Power Domain Status
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : SYSCTL_EMACPDS_PWRSTAT_OFF
OFF
0x3 : SYSCTL_EMACPDS_PWRSTAT_ON
ON
End of enumeration elements list.
SYSCTL_EMACPDS_MEMSTAT : Memory Array Power Status
bits : 2 - 5 (4 bit)
Enumeration:
0x0 : SYSCTL_EMACPDS_MEMSTAT_OFF
Array OFF
0x3 : SYSCTL_EMACPDS_MEMSTAT_ON
Array On
End of enumeration elements list.
Ethernet MAC Memory Power Control
address_offset : 0x28C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_EMACMPC_PWRCTL : Memory Array Power Control
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : SYSCTL_EMACMPC_PWRCTL_OFF
Array OFF
0x3 : SYSCTL_EMACMPC_PWRCTL_ON
Array On
End of enumeration elements list.
Ethernet MAC Memory Power Control
address_offset : 0x28C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_EMACMPC_PWRCTL : Memory Array Power Control
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : SYSCTL_EMACMPC_PWRCTL_OFF
Array OFF
0x3 : SYSCTL_EMACMPC_PWRCTL_ON
Array On
End of enumeration elements list.
Watchdog Timer Peripheral Present
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPWD_P0 : Watchdog Timer 0 Present
bits : 0 - 0 (1 bit)
SYSCTL_PPWD_P1 : Watchdog Timer 1 Present
bits : 1 - 2 (2 bit)
Watchdog Timer Peripheral Present
address_offset : 0x300 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPWD_P0 : Watchdog Timer 0 Present
bits : 0 - 0 (1 bit)
SYSCTL_PPWD_P1 : Watchdog Timer 1 Present
bits : 1 - 2 (2 bit)
16/32-Bit General-Purpose Timer Peripheral Present
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPTIMER_P0 : 16/32-Bit General-Purpose Timer 0 Present
bits : 0 - 0 (1 bit)
SYSCTL_PPTIMER_P1 : 16/32-Bit General-Purpose Timer 1 Present
bits : 1 - 2 (2 bit)
SYSCTL_PPTIMER_P2 : 16/32-Bit General-Purpose Timer 2 Present
bits : 2 - 4 (3 bit)
SYSCTL_PPTIMER_P3 : 16/32-Bit General-Purpose Timer 3 Present
bits : 3 - 6 (4 bit)
SYSCTL_PPTIMER_P4 : 16/32-Bit General-Purpose Timer 4 Present
bits : 4 - 8 (5 bit)
SYSCTL_PPTIMER_P5 : 16/32-Bit General-Purpose Timer 5 Present
bits : 5 - 10 (6 bit)
SYSCTL_PPTIMER_P6 : 16/32-Bit General-Purpose Timer 6 Present
bits : 6 - 12 (7 bit)
SYSCTL_PPTIMER_P7 : 16/32-Bit General-Purpose Timer 7 Present
bits : 7 - 14 (8 bit)
16/32-Bit General-Purpose Timer Peripheral Present
address_offset : 0x304 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPTIMER_P0 : 16/32-Bit General-Purpose Timer 0 Present
bits : 0 - 0 (1 bit)
SYSCTL_PPTIMER_P1 : 16/32-Bit General-Purpose Timer 1 Present
bits : 1 - 2 (2 bit)
SYSCTL_PPTIMER_P2 : 16/32-Bit General-Purpose Timer 2 Present
bits : 2 - 4 (3 bit)
SYSCTL_PPTIMER_P3 : 16/32-Bit General-Purpose Timer 3 Present
bits : 3 - 6 (4 bit)
SYSCTL_PPTIMER_P4 : 16/32-Bit General-Purpose Timer 4 Present
bits : 4 - 8 (5 bit)
SYSCTL_PPTIMER_P5 : 16/32-Bit General-Purpose Timer 5 Present
bits : 5 - 10 (6 bit)
SYSCTL_PPTIMER_P6 : 16/32-Bit General-Purpose Timer 6 Present
bits : 6 - 12 (7 bit)
SYSCTL_PPTIMER_P7 : 16/32-Bit General-Purpose Timer 7 Present
bits : 7 - 14 (8 bit)
General-Purpose Input/Output Peripheral Present
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPGPIO_P0 : GPIO Port A Present
bits : 0 - 0 (1 bit)
SYSCTL_PPGPIO_P1 : GPIO Port B Present
bits : 1 - 2 (2 bit)
SYSCTL_PPGPIO_P2 : GPIO Port C Present
bits : 2 - 4 (3 bit)
SYSCTL_PPGPIO_P3 : GPIO Port D Present
bits : 3 - 6 (4 bit)
SYSCTL_PPGPIO_P4 : GPIO Port E Present
bits : 4 - 8 (5 bit)
SYSCTL_PPGPIO_P5 : GPIO Port F Present
bits : 5 - 10 (6 bit)
SYSCTL_PPGPIO_P6 : GPIO Port G Present
bits : 6 - 12 (7 bit)
SYSCTL_PPGPIO_P7 : GPIO Port H Present
bits : 7 - 14 (8 bit)
SYSCTL_PPGPIO_P8 : GPIO Port J Present
bits : 8 - 16 (9 bit)
SYSCTL_PPGPIO_P9 : GPIO Port K Present
bits : 9 - 18 (10 bit)
SYSCTL_PPGPIO_P10 : GPIO Port L Present
bits : 10 - 20 (11 bit)
SYSCTL_PPGPIO_P11 : GPIO Port M Present
bits : 11 - 22 (12 bit)
SYSCTL_PPGPIO_P12 : GPIO Port N Present
bits : 12 - 24 (13 bit)
SYSCTL_PPGPIO_P13 : GPIO Port P Present
bits : 13 - 26 (14 bit)
SYSCTL_PPGPIO_P14 : GPIO Port Q Present
bits : 14 - 28 (15 bit)
General-Purpose Input/Output Peripheral Present
address_offset : 0x308 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPGPIO_P0 : GPIO Port A Present
bits : 0 - 0 (1 bit)
SYSCTL_PPGPIO_P1 : GPIO Port B Present
bits : 1 - 2 (2 bit)
SYSCTL_PPGPIO_P2 : GPIO Port C Present
bits : 2 - 4 (3 bit)
SYSCTL_PPGPIO_P3 : GPIO Port D Present
bits : 3 - 6 (4 bit)
SYSCTL_PPGPIO_P4 : GPIO Port E Present
bits : 4 - 8 (5 bit)
SYSCTL_PPGPIO_P5 : GPIO Port F Present
bits : 5 - 10 (6 bit)
SYSCTL_PPGPIO_P6 : GPIO Port G Present
bits : 6 - 12 (7 bit)
SYSCTL_PPGPIO_P7 : GPIO Port H Present
bits : 7 - 14 (8 bit)
SYSCTL_PPGPIO_P8 : GPIO Port J Present
bits : 8 - 16 (9 bit)
SYSCTL_PPGPIO_P9 : GPIO Port K Present
bits : 9 - 18 (10 bit)
SYSCTL_PPGPIO_P10 : GPIO Port L Present
bits : 10 - 20 (11 bit)
SYSCTL_PPGPIO_P11 : GPIO Port M Present
bits : 11 - 22 (12 bit)
SYSCTL_PPGPIO_P12 : GPIO Port N Present
bits : 12 - 24 (13 bit)
SYSCTL_PPGPIO_P13 : GPIO Port P Present
bits : 13 - 26 (14 bit)
SYSCTL_PPGPIO_P14 : GPIO Port Q Present
bits : 14 - 28 (15 bit)
Micro Direct Memory Access Peripheral Present
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPDMA_P0 : uDMA Module Present
bits : 0 - 0 (1 bit)
Micro Direct Memory Access Peripheral Present
address_offset : 0x30C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPDMA_P0 : uDMA Module Present
bits : 0 - 0 (1 bit)
EPI Peripheral Present
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPEPI_P0 : EPI Module Present
bits : 0 - 0 (1 bit)
EPI Peripheral Present
address_offset : 0x310 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPEPI_P0 : EPI Module Present
bits : 0 - 0 (1 bit)
Hibernation Peripheral Present
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPHIB_P0 : Hibernation Module Present
bits : 0 - 0 (1 bit)
Hibernation Peripheral Present
address_offset : 0x314 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPHIB_P0 : Hibernation Module Present
bits : 0 - 0 (1 bit)
Universal Asynchronous Receiver/Transmitter Peripheral Present
address_offset : 0x318 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPUART_P0 : UART Module 0 Present
bits : 0 - 0 (1 bit)
SYSCTL_PPUART_P1 : UART Module 1 Present
bits : 1 - 2 (2 bit)
SYSCTL_PPUART_P2 : UART Module 2 Present
bits : 2 - 4 (3 bit)
SYSCTL_PPUART_P3 : UART Module 3 Present
bits : 3 - 6 (4 bit)
SYSCTL_PPUART_P4 : UART Module 4 Present
bits : 4 - 8 (5 bit)
SYSCTL_PPUART_P5 : UART Module 5 Present
bits : 5 - 10 (6 bit)
SYSCTL_PPUART_P6 : UART Module 6 Present
bits : 6 - 12 (7 bit)
SYSCTL_PPUART_P7 : UART Module 7 Present
bits : 7 - 14 (8 bit)
Universal Asynchronous Receiver/Transmitter Peripheral Present
address_offset : 0x318 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPUART_P0 : UART Module 0 Present
bits : 0 - 0 (1 bit)
SYSCTL_PPUART_P1 : UART Module 1 Present
bits : 1 - 2 (2 bit)
SYSCTL_PPUART_P2 : UART Module 2 Present
bits : 2 - 4 (3 bit)
SYSCTL_PPUART_P3 : UART Module 3 Present
bits : 3 - 6 (4 bit)
SYSCTL_PPUART_P4 : UART Module 4 Present
bits : 4 - 8 (5 bit)
SYSCTL_PPUART_P5 : UART Module 5 Present
bits : 5 - 10 (6 bit)
SYSCTL_PPUART_P6 : UART Module 6 Present
bits : 6 - 12 (7 bit)
SYSCTL_PPUART_P7 : UART Module 7 Present
bits : 7 - 14 (8 bit)
Synchronous Serial Interface Peripheral Present
address_offset : 0x31C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPSSI_P0 : SSI Module 0 Present
bits : 0 - 0 (1 bit)
SYSCTL_PPSSI_P1 : SSI Module 1 Present
bits : 1 - 2 (2 bit)
SYSCTL_PPSSI_P2 : SSI Module 2 Present
bits : 2 - 4 (3 bit)
SYSCTL_PPSSI_P3 : SSI Module 3 Present
bits : 3 - 6 (4 bit)
Synchronous Serial Interface Peripheral Present
address_offset : 0x31C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPSSI_P0 : SSI Module 0 Present
bits : 0 - 0 (1 bit)
SYSCTL_PPSSI_P1 : SSI Module 1 Present
bits : 1 - 2 (2 bit)
SYSCTL_PPSSI_P2 : SSI Module 2 Present
bits : 2 - 4 (3 bit)
SYSCTL_PPSSI_P3 : SSI Module 3 Present
bits : 3 - 6 (4 bit)
Inter-Integrated Circuit Peripheral Present
address_offset : 0x320 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPI2C_P0 : I2C Module 0 Present
bits : 0 - 0 (1 bit)
SYSCTL_PPI2C_P1 : I2C Module 1 Present
bits : 1 - 2 (2 bit)
SYSCTL_PPI2C_P2 : I2C Module 2 Present
bits : 2 - 4 (3 bit)
SYSCTL_PPI2C_P3 : I2C Module 3 Present
bits : 3 - 6 (4 bit)
SYSCTL_PPI2C_P4 : I2C Module 4 Present
bits : 4 - 8 (5 bit)
SYSCTL_PPI2C_P5 : I2C Module 5 Present
bits : 5 - 10 (6 bit)
SYSCTL_PPI2C_P6 : I2C Module 6 Present
bits : 6 - 12 (7 bit)
SYSCTL_PPI2C_P7 : I2C Module 7 Present
bits : 7 - 14 (8 bit)
SYSCTL_PPI2C_P8 : I2C Module 8 Present
bits : 8 - 16 (9 bit)
SYSCTL_PPI2C_P9 : I2C Module 9 Present
bits : 9 - 18 (10 bit)
Inter-Integrated Circuit Peripheral Present
address_offset : 0x320 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPI2C_P0 : I2C Module 0 Present
bits : 0 - 0 (1 bit)
SYSCTL_PPI2C_P1 : I2C Module 1 Present
bits : 1 - 2 (2 bit)
SYSCTL_PPI2C_P2 : I2C Module 2 Present
bits : 2 - 4 (3 bit)
SYSCTL_PPI2C_P3 : I2C Module 3 Present
bits : 3 - 6 (4 bit)
SYSCTL_PPI2C_P4 : I2C Module 4 Present
bits : 4 - 8 (5 bit)
SYSCTL_PPI2C_P5 : I2C Module 5 Present
bits : 5 - 10 (6 bit)
SYSCTL_PPI2C_P6 : I2C Module 6 Present
bits : 6 - 12 (7 bit)
SYSCTL_PPI2C_P7 : I2C Module 7 Present
bits : 7 - 14 (8 bit)
SYSCTL_PPI2C_P8 : I2C Module 8 Present
bits : 8 - 16 (9 bit)
SYSCTL_PPI2C_P9 : I2C Module 9 Present
bits : 9 - 18 (10 bit)
Universal Serial Bus Peripheral Present
address_offset : 0x328 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPUSB_P0 : USB Module Present
bits : 0 - 0 (1 bit)
Universal Serial Bus Peripheral Present
address_offset : 0x328 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPUSB_P0 : USB Module Present
bits : 0 - 0 (1 bit)
Ethernet PHY Peripheral Present
address_offset : 0x330 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPEPHY_P0 : Ethernet PHY Module Present
bits : 0 - 0 (1 bit)
Ethernet PHY Peripheral Present
address_offset : 0x330 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPEPHY_P0 : Ethernet PHY Module Present
bits : 0 - 0 (1 bit)
Controller Area Network Peripheral Present
address_offset : 0x334 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPCAN_P0 : CAN Module 0 Present
bits : 0 - 0 (1 bit)
SYSCTL_PPCAN_P1 : CAN Module 1 Present
bits : 1 - 2 (2 bit)
Controller Area Network Peripheral Present
address_offset : 0x334 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPCAN_P0 : CAN Module 0 Present
bits : 0 - 0 (1 bit)
SYSCTL_PPCAN_P1 : CAN Module 1 Present
bits : 1 - 2 (2 bit)
Analog-to-Digital Converter Peripheral Present
address_offset : 0x338 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPADC_P0 : ADC Module 0 Present
bits : 0 - 0 (1 bit)
SYSCTL_PPADC_P1 : ADC Module 1 Present
bits : 1 - 2 (2 bit)
Analog-to-Digital Converter Peripheral Present
address_offset : 0x338 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPADC_P0 : ADC Module 0 Present
bits : 0 - 0 (1 bit)
SYSCTL_PPADC_P1 : ADC Module 1 Present
bits : 1 - 2 (2 bit)
Analog Comparator Peripheral Present
address_offset : 0x33C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPACMP_P0 : Analog Comparator Module Present
bits : 0 - 0 (1 bit)
Analog Comparator Peripheral Present
address_offset : 0x33C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPACMP_P0 : Analog Comparator Module Present
bits : 0 - 0 (1 bit)
Pulse Width Modulator Peripheral Present
address_offset : 0x340 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPPWM_P0 : PWM Module 0 Present
bits : 0 - 0 (1 bit)
Pulse Width Modulator Peripheral Present
address_offset : 0x340 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPPWM_P0 : PWM Module 0 Present
bits : 0 - 0 (1 bit)
Quadrature Encoder Interface Peripheral Present
address_offset : 0x344 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPQEI_P0 : QEI Module 0 Present
bits : 0 - 0 (1 bit)
Quadrature Encoder Interface Peripheral Present
address_offset : 0x344 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPQEI_P0 : QEI Module 0 Present
bits : 0 - 0 (1 bit)
Low Pin Count Interface Peripheral Present
address_offset : 0x348 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPLPC_P0 : LPC Module Present
bits : 0 - 0 (1 bit)
Low Pin Count Interface Peripheral Present
address_offset : 0x348 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPLPC_P0 : LPC Module Present
bits : 0 - 0 (1 bit)
Platform Environment Control Interface Peripheral Present
address_offset : 0x350 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPPECI_P0 : PECI Module Present
bits : 0 - 0 (1 bit)
Platform Environment Control Interface Peripheral Present
address_offset : 0x350 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPPECI_P0 : PECI Module Present
bits : 0 - 0 (1 bit)
Fan Control Peripheral Present
address_offset : 0x354 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPFAN_P0 : FAN Module 0 Present
bits : 0 - 0 (1 bit)
Fan Control Peripheral Present
address_offset : 0x354 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPFAN_P0 : FAN Module 0 Present
bits : 0 - 0 (1 bit)
EEPROM Peripheral Present
address_offset : 0x358 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPEEPROM_P0 : EEPROM Module Present
bits : 0 - 0 (1 bit)
EEPROM Peripheral Present
address_offset : 0x358 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPEEPROM_P0 : EEPROM Module Present
bits : 0 - 0 (1 bit)
32/64-Bit Wide General-Purpose Timer Peripheral Present
address_offset : 0x35C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPWTIMER_P0 : 32/64-Bit Wide General-Purpose Timer 0 Present
bits : 0 - 0 (1 bit)
32/64-Bit Wide General-Purpose Timer Peripheral Present
address_offset : 0x35C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPWTIMER_P0 : 32/64-Bit Wide General-Purpose Timer 0 Present
bits : 0 - 0 (1 bit)
Remote Temperature Sensor Peripheral Present
address_offset : 0x370 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPRTS_P0 : RTS Module Present
bits : 0 - 0 (1 bit)
Remote Temperature Sensor Peripheral Present
address_offset : 0x370 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPRTS_P0 : RTS Module Present
bits : 0 - 0 (1 bit)
CRC and Cryptographic Modules Peripheral Present
address_offset : 0x374 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPCCM_P0 : CRC and Cryptographic Modules Present
bits : 0 - 0 (1 bit)
CRC and Cryptographic Modules Peripheral Present
address_offset : 0x374 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPCCM_P0 : CRC and Cryptographic Modules Present
bits : 0 - 0 (1 bit)
Power-Temp Brown Out Control
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PTBOCTL_VDD_UBOR : VDD (VDDS) under BOR Event Action
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : SYSCTL_PTBOCTL_VDD_UBOR_NONE
No Action
0x1 : SYSCTL_PTBOCTL_VDD_UBOR_SYSINT
System control interrupt
0x2 : SYSCTL_PTBOCTL_VDD_UBOR_NMI
NMI
0x3 : SYSCTL_PTBOCTL_VDD_UBOR_RST
Reset
End of enumeration elements list.
SYSCTL_PTBOCTL_VDDA_UBOR : VDDA under BOR Event Action
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : SYSCTL_PTBOCTL_VDDA_UBOR_NONE
No Action
0x1 : SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT
System control interrupt
0x2 : SYSCTL_PTBOCTL_VDDA_UBOR_NMI
NMI
0x3 : SYSCTL_PTBOCTL_VDDA_UBOR_RST
Reset
End of enumeration elements list.
Power-Temp Brown Out Control
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PTBOCTL_VDD_UBOR : VDD (VDDS) under BOR Event Action
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : SYSCTL_PTBOCTL_VDD_UBOR_NONE
No Action
0x1 : SYSCTL_PTBOCTL_VDD_UBOR_SYSINT
System control interrupt
0x2 : SYSCTL_PTBOCTL_VDD_UBOR_NMI
NMI
0x3 : SYSCTL_PTBOCTL_VDD_UBOR_RST
Reset
End of enumeration elements list.
SYSCTL_PTBOCTL_VDDA_UBOR : VDDA under BOR Event Action
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : SYSCTL_PTBOCTL_VDDA_UBOR_NONE
No Action
0x1 : SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT
System control interrupt
0x2 : SYSCTL_PTBOCTL_VDDA_UBOR_NMI
NMI
0x3 : SYSCTL_PTBOCTL_VDDA_UBOR_RST
Reset
End of enumeration elements list.
LCD Peripheral Present
address_offset : 0x390 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPLCD_P0 : LCD Module Present
bits : 0 - 0 (1 bit)
LCD Peripheral Present
address_offset : 0x390 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPLCD_P0 : LCD Module Present
bits : 0 - 0 (1 bit)
1-Wire Peripheral Present
address_offset : 0x398 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPOWIRE_P0 : 1-Wire Module Present
bits : 0 - 0 (1 bit)
1-Wire Peripheral Present
address_offset : 0x398 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPOWIRE_P0 : 1-Wire Module Present
bits : 0 - 0 (1 bit)
Ethernet MAC Peripheral Present
address_offset : 0x39C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPEMAC_P0 : Ethernet Controller Module Present
bits : 0 - 0 (1 bit)
Ethernet MAC Peripheral Present
address_offset : 0x39C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPEMAC_P0 : Ethernet Controller Module Present
bits : 0 - 0 (1 bit)
Human Interface Master Peripheral Present
address_offset : 0x3A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPHIM_P0 : HIM Module Present
bits : 0 - 0 (1 bit)
Human Interface Master Peripheral Present
address_offset : 0x3A4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PPHIM_P0 : HIM Module Present
bits : 0 - 0 (1 bit)
Device Identification 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DID1_QUAL : Qualification Status
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : SYSCTL_DID1_QUAL_ES
Engineering Sample (unqualified)
0x1 : SYSCTL_DID1_QUAL_PP
Pilot Production (unqualified)
0x2 : SYSCTL_DID1_QUAL_FQ
Fully Qualified
End of enumeration elements list.
SYSCTL_DID1_ROHS : RoHS-Compliance
bits : 2 - 4 (3 bit)
SYSCTL_DID1_PKG : Package Type
bits : 3 - 7 (5 bit)
Enumeration:
0x1 : SYSCTL_DID1_PKG_QFP
QFP package
0x2 : SYSCTL_DID1_PKG_BGA
BGA package
End of enumeration elements list.
SYSCTL_DID1_TEMP : Temperature Range
bits : 5 - 12 (8 bit)
Enumeration:
0x0 : SYSCTL_DID1_TEMP_C
Commercial temperature range
0x1 : SYSCTL_DID1_TEMP_I
Industrial temperature range
0x2 : SYSCTL_DID1_TEMP_E
Extended temperature range
End of enumeration elements list.
SYSCTL_DID1_PINCNT : Package Pin Count
bits : 13 - 28 (16 bit)
Enumeration:
0x2 : SYSCTL_DID1_PINCNT_100
100-pin LQFP package
0x3 : SYSCTL_DID1_PINCNT_64
64-pin LQFP package
0x4 : SYSCTL_DID1_PINCNT_144
144-pin LQFP package
0x5 : SYSCTL_DID1_PINCNT_157
157-pin BGA package
0x6 : SYSCTL_DID1_PINCNT_128
128-pin TQFP package
End of enumeration elements list.
SYSCTL_DID1_PRTNO : Part Number
bits : 16 - 39 (24 bit)
SYSCTL_DID1_FAM : Family
bits : 24 - 51 (28 bit)
SYSCTL_DID1_VER : DID1 Version
bits : 28 - 59 (32 bit)
Device Identification 1
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DID1_QUAL : Qualification Status
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : SYSCTL_DID1_QUAL_ES
Engineering Sample (unqualified)
0x1 : SYSCTL_DID1_QUAL_PP
Pilot Production (unqualified)
0x2 : SYSCTL_DID1_QUAL_FQ
Fully Qualified
End of enumeration elements list.
SYSCTL_DID1_ROHS : RoHS-Compliance
bits : 2 - 4 (3 bit)
SYSCTL_DID1_PKG : Package Type
bits : 3 - 7 (5 bit)
Enumeration:
0x1 : SYSCTL_DID1_PKG_QFP
QFP package
0x2 : SYSCTL_DID1_PKG_BGA
BGA package
End of enumeration elements list.
SYSCTL_DID1_TEMP : Temperature Range
bits : 5 - 12 (8 bit)
Enumeration:
0x0 : SYSCTL_DID1_TEMP_C
Commercial temperature range
0x1 : SYSCTL_DID1_TEMP_I
Industrial temperature range
0x2 : SYSCTL_DID1_TEMP_E
Extended temperature range
End of enumeration elements list.
SYSCTL_DID1_PINCNT : Package Pin Count
bits : 13 - 28 (16 bit)
Enumeration:
0x2 : SYSCTL_DID1_PINCNT_100
100-pin LQFP package
0x3 : SYSCTL_DID1_PINCNT_64
64-pin LQFP package
0x4 : SYSCTL_DID1_PINCNT_144
144-pin LQFP package
0x5 : SYSCTL_DID1_PINCNT_157
157-pin BGA package
0x6 : SYSCTL_DID1_PINCNT_128
128-pin TQFP package
End of enumeration elements list.
SYSCTL_DID1_PRTNO : Part Number
bits : 16 - 39 (24 bit)
SYSCTL_DID1_FAM : Family
bits : 24 - 51 (28 bit)
SYSCTL_DID1_VER : DID1 Version
bits : 28 - 59 (32 bit)
Raw Interrupt Status
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RIS_BORRIS : Brown-Out Reset Raw Interrupt Status
bits : 1 - 2 (2 bit)
SYSCTL_RIS_MOFRIS : Main Oscillator Failure Raw Interrupt Status
bits : 3 - 6 (4 bit)
SYSCTL_RIS_PLLLRIS : PLL Lock Raw Interrupt Status
bits : 6 - 12 (7 bit)
SYSCTL_RIS_MOSCPUPRIS : MOSC Power Up Raw Interrupt Status
bits : 8 - 16 (9 bit)
Raw Interrupt Status
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RIS_BORRIS : Brown-Out Reset Raw Interrupt Status
bits : 1 - 2 (2 bit)
SYSCTL_RIS_MOFRIS : Main Oscillator Failure Raw Interrupt Status
bits : 3 - 6 (4 bit)
SYSCTL_RIS_PLLLRIS : PLL Lock Raw Interrupt Status
bits : 6 - 12 (7 bit)
SYSCTL_RIS_MOSCPUPRIS : MOSC Power Up Raw Interrupt Status
bits : 8 - 16 (9 bit)
Watchdog Timer Software Reset
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRWD_R0 : Watchdog Timer 0 Software Reset
bits : 0 - 0 (1 bit)
SYSCTL_SRWD_R1 : Watchdog Timer 1 Software Reset
bits : 1 - 2 (2 bit)
Watchdog Timer Software Reset
address_offset : 0x500 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRWD_R0 : Watchdog Timer 0 Software Reset
bits : 0 - 0 (1 bit)
SYSCTL_SRWD_R1 : Watchdog Timer 1 Software Reset
bits : 1 - 2 (2 bit)
16/32-Bit General-Purpose Timer Software Reset
address_offset : 0x504 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRTIMER_R0 : 16/32-Bit General-Purpose Timer 0 Software Reset
bits : 0 - 0 (1 bit)
SYSCTL_SRTIMER_R1 : 16/32-Bit General-Purpose Timer 1 Software Reset
bits : 1 - 2 (2 bit)
SYSCTL_SRTIMER_R2 : 16/32-Bit General-Purpose Timer 2 Software Reset
bits : 2 - 4 (3 bit)
SYSCTL_SRTIMER_R3 : 16/32-Bit General-Purpose Timer 3 Software Reset
bits : 3 - 6 (4 bit)
SYSCTL_SRTIMER_R4 : 16/32-Bit General-Purpose Timer 4 Software Reset
bits : 4 - 8 (5 bit)
SYSCTL_SRTIMER_R5 : 16/32-Bit General-Purpose Timer 5 Software Reset
bits : 5 - 10 (6 bit)
SYSCTL_SRTIMER_R6 : 16/32-Bit General-Purpose Timer 6 Software Reset
bits : 6 - 12 (7 bit)
SYSCTL_SRTIMER_R7 : 16/32-Bit General-Purpose Timer 7 Software Reset
bits : 7 - 14 (8 bit)
16/32-Bit General-Purpose Timer Software Reset
address_offset : 0x504 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRTIMER_R0 : 16/32-Bit General-Purpose Timer 0 Software Reset
bits : 0 - 0 (1 bit)
SYSCTL_SRTIMER_R1 : 16/32-Bit General-Purpose Timer 1 Software Reset
bits : 1 - 2 (2 bit)
SYSCTL_SRTIMER_R2 : 16/32-Bit General-Purpose Timer 2 Software Reset
bits : 2 - 4 (3 bit)
SYSCTL_SRTIMER_R3 : 16/32-Bit General-Purpose Timer 3 Software Reset
bits : 3 - 6 (4 bit)
SYSCTL_SRTIMER_R4 : 16/32-Bit General-Purpose Timer 4 Software Reset
bits : 4 - 8 (5 bit)
SYSCTL_SRTIMER_R5 : 16/32-Bit General-Purpose Timer 5 Software Reset
bits : 5 - 10 (6 bit)
SYSCTL_SRTIMER_R6 : 16/32-Bit General-Purpose Timer 6 Software Reset
bits : 6 - 12 (7 bit)
SYSCTL_SRTIMER_R7 : 16/32-Bit General-Purpose Timer 7 Software Reset
bits : 7 - 14 (8 bit)
General-Purpose Input/Output Software Reset
address_offset : 0x508 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRGPIO_R0 : GPIO Port A Software Reset
bits : 0 - 0 (1 bit)
SYSCTL_SRGPIO_R1 : GPIO Port B Software Reset
bits : 1 - 2 (2 bit)
SYSCTL_SRGPIO_R2 : GPIO Port C Software Reset
bits : 2 - 4 (3 bit)
SYSCTL_SRGPIO_R3 : GPIO Port D Software Reset
bits : 3 - 6 (4 bit)
SYSCTL_SRGPIO_R4 : GPIO Port E Software Reset
bits : 4 - 8 (5 bit)
SYSCTL_SRGPIO_R5 : GPIO Port F Software Reset
bits : 5 - 10 (6 bit)
SYSCTL_SRGPIO_R6 : GPIO Port G Software Reset
bits : 6 - 12 (7 bit)
SYSCTL_SRGPIO_R7 : GPIO Port H Software Reset
bits : 7 - 14 (8 bit)
SYSCTL_SRGPIO_R8 : GPIO Port J Software Reset
bits : 8 - 16 (9 bit)
SYSCTL_SRGPIO_R9 : GPIO Port K Software Reset
bits : 9 - 18 (10 bit)
SYSCTL_SRGPIO_R10 : GPIO Port L Software Reset
bits : 10 - 20 (11 bit)
SYSCTL_SRGPIO_R11 : GPIO Port M Software Reset
bits : 11 - 22 (12 bit)
SYSCTL_SRGPIO_R12 : GPIO Port N Software Reset
bits : 12 - 24 (13 bit)
SYSCTL_SRGPIO_R13 : GPIO Port P Software Reset
bits : 13 - 26 (14 bit)
SYSCTL_SRGPIO_R14 : GPIO Port Q Software Reset
bits : 14 - 28 (15 bit)
General-Purpose Input/Output Software Reset
address_offset : 0x508 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRGPIO_R0 : GPIO Port A Software Reset
bits : 0 - 0 (1 bit)
SYSCTL_SRGPIO_R1 : GPIO Port B Software Reset
bits : 1 - 2 (2 bit)
SYSCTL_SRGPIO_R2 : GPIO Port C Software Reset
bits : 2 - 4 (3 bit)
SYSCTL_SRGPIO_R3 : GPIO Port D Software Reset
bits : 3 - 6 (4 bit)
SYSCTL_SRGPIO_R4 : GPIO Port E Software Reset
bits : 4 - 8 (5 bit)
SYSCTL_SRGPIO_R5 : GPIO Port F Software Reset
bits : 5 - 10 (6 bit)
SYSCTL_SRGPIO_R6 : GPIO Port G Software Reset
bits : 6 - 12 (7 bit)
SYSCTL_SRGPIO_R7 : GPIO Port H Software Reset
bits : 7 - 14 (8 bit)
SYSCTL_SRGPIO_R8 : GPIO Port J Software Reset
bits : 8 - 16 (9 bit)
SYSCTL_SRGPIO_R9 : GPIO Port K Software Reset
bits : 9 - 18 (10 bit)
SYSCTL_SRGPIO_R10 : GPIO Port L Software Reset
bits : 10 - 20 (11 bit)
SYSCTL_SRGPIO_R11 : GPIO Port M Software Reset
bits : 11 - 22 (12 bit)
SYSCTL_SRGPIO_R12 : GPIO Port N Software Reset
bits : 12 - 24 (13 bit)
SYSCTL_SRGPIO_R13 : GPIO Port P Software Reset
bits : 13 - 26 (14 bit)
SYSCTL_SRGPIO_R14 : GPIO Port Q Software Reset
bits : 14 - 28 (15 bit)
Micro Direct Memory Access Software Reset
address_offset : 0x50C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRDMA_R0 : uDMA Module Software Reset
bits : 0 - 0 (1 bit)
Micro Direct Memory Access Software Reset
address_offset : 0x50C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRDMA_R0 : uDMA Module Software Reset
bits : 0 - 0 (1 bit)
EPI Software Reset
address_offset : 0x510 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SREPI_R0 : EPI Module Software Reset
bits : 0 - 0 (1 bit)
EPI Software Reset
address_offset : 0x510 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SREPI_R0 : EPI Module Software Reset
bits : 0 - 0 (1 bit)
Hibernation Software Reset
address_offset : 0x514 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRHIB_R0 : Hibernation Module Software Reset
bits : 0 - 0 (1 bit)
Hibernation Software Reset
address_offset : 0x514 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRHIB_R0 : Hibernation Module Software Reset
bits : 0 - 0 (1 bit)
Universal Asynchronous Receiver/Transmitter Software Reset
address_offset : 0x518 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRUART_R0 : UART Module 0 Software Reset
bits : 0 - 0 (1 bit)
SYSCTL_SRUART_R1 : UART Module 1 Software Reset
bits : 1 - 2 (2 bit)
SYSCTL_SRUART_R2 : UART Module 2 Software Reset
bits : 2 - 4 (3 bit)
SYSCTL_SRUART_R3 : UART Module 3 Software Reset
bits : 3 - 6 (4 bit)
SYSCTL_SRUART_R4 : UART Module 4 Software Reset
bits : 4 - 8 (5 bit)
SYSCTL_SRUART_R5 : UART Module 5 Software Reset
bits : 5 - 10 (6 bit)
SYSCTL_SRUART_R6 : UART Module 6 Software Reset
bits : 6 - 12 (7 bit)
SYSCTL_SRUART_R7 : UART Module 7 Software Reset
bits : 7 - 14 (8 bit)
Universal Asynchronous Receiver/Transmitter Software Reset
address_offset : 0x518 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRUART_R0 : UART Module 0 Software Reset
bits : 0 - 0 (1 bit)
SYSCTL_SRUART_R1 : UART Module 1 Software Reset
bits : 1 - 2 (2 bit)
SYSCTL_SRUART_R2 : UART Module 2 Software Reset
bits : 2 - 4 (3 bit)
SYSCTL_SRUART_R3 : UART Module 3 Software Reset
bits : 3 - 6 (4 bit)
SYSCTL_SRUART_R4 : UART Module 4 Software Reset
bits : 4 - 8 (5 bit)
SYSCTL_SRUART_R5 : UART Module 5 Software Reset
bits : 5 - 10 (6 bit)
SYSCTL_SRUART_R6 : UART Module 6 Software Reset
bits : 6 - 12 (7 bit)
SYSCTL_SRUART_R7 : UART Module 7 Software Reset
bits : 7 - 14 (8 bit)
Synchronous Serial Interface Software Reset
address_offset : 0x51C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRSSI_R0 : SSI Module 0 Software Reset
bits : 0 - 0 (1 bit)
SYSCTL_SRSSI_R1 : SSI Module 1 Software Reset
bits : 1 - 2 (2 bit)
SYSCTL_SRSSI_R2 : SSI Module 2 Software Reset
bits : 2 - 4 (3 bit)
SYSCTL_SRSSI_R3 : SSI Module 3 Software Reset
bits : 3 - 6 (4 bit)
Synchronous Serial Interface Software Reset
address_offset : 0x51C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRSSI_R0 : SSI Module 0 Software Reset
bits : 0 - 0 (1 bit)
SYSCTL_SRSSI_R1 : SSI Module 1 Software Reset
bits : 1 - 2 (2 bit)
SYSCTL_SRSSI_R2 : SSI Module 2 Software Reset
bits : 2 - 4 (3 bit)
SYSCTL_SRSSI_R3 : SSI Module 3 Software Reset
bits : 3 - 6 (4 bit)
Inter-Integrated Circuit Software Reset
address_offset : 0x520 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRI2C_R0 : I2C Module 0 Software Reset
bits : 0 - 0 (1 bit)
SYSCTL_SRI2C_R1 : I2C Module 1 Software Reset
bits : 1 - 2 (2 bit)
SYSCTL_SRI2C_R2 : I2C Module 2 Software Reset
bits : 2 - 4 (3 bit)
SYSCTL_SRI2C_R3 : I2C Module 3 Software Reset
bits : 3 - 6 (4 bit)
SYSCTL_SRI2C_R4 : I2C Module 4 Software Reset
bits : 4 - 8 (5 bit)
SYSCTL_SRI2C_R5 : I2C Module 5 Software Reset
bits : 5 - 10 (6 bit)
SYSCTL_SRI2C_R6 : I2C Module 6 Software Reset
bits : 6 - 12 (7 bit)
SYSCTL_SRI2C_R7 : I2C Module 7 Software Reset
bits : 7 - 14 (8 bit)
SYSCTL_SRI2C_R8 : I2C Module 8 Software Reset
bits : 8 - 16 (9 bit)
SYSCTL_SRI2C_R9 : I2C Module 9 Software Reset
bits : 9 - 18 (10 bit)
Inter-Integrated Circuit Software Reset
address_offset : 0x520 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRI2C_R0 : I2C Module 0 Software Reset
bits : 0 - 0 (1 bit)
SYSCTL_SRI2C_R1 : I2C Module 1 Software Reset
bits : 1 - 2 (2 bit)
SYSCTL_SRI2C_R2 : I2C Module 2 Software Reset
bits : 2 - 4 (3 bit)
SYSCTL_SRI2C_R3 : I2C Module 3 Software Reset
bits : 3 - 6 (4 bit)
SYSCTL_SRI2C_R4 : I2C Module 4 Software Reset
bits : 4 - 8 (5 bit)
SYSCTL_SRI2C_R5 : I2C Module 5 Software Reset
bits : 5 - 10 (6 bit)
SYSCTL_SRI2C_R6 : I2C Module 6 Software Reset
bits : 6 - 12 (7 bit)
SYSCTL_SRI2C_R7 : I2C Module 7 Software Reset
bits : 7 - 14 (8 bit)
SYSCTL_SRI2C_R8 : I2C Module 8 Software Reset
bits : 8 - 16 (9 bit)
SYSCTL_SRI2C_R9 : I2C Module 9 Software Reset
bits : 9 - 18 (10 bit)
Universal Serial Bus Software Reset
address_offset : 0x528 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRUSB_R0 : USB Module Software Reset
bits : 0 - 0 (1 bit)
Universal Serial Bus Software Reset
address_offset : 0x528 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRUSB_R0 : USB Module Software Reset
bits : 0 - 0 (1 bit)
Ethernet PHY Software Reset
address_offset : 0x530 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SREPHY_R0 : Ethernet PHY Module Software Reset
bits : 0 - 0 (1 bit)
Ethernet PHY Software Reset
address_offset : 0x530 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SREPHY_R0 : Ethernet PHY Module Software Reset
bits : 0 - 0 (1 bit)
Controller Area Network Software Reset
address_offset : 0x534 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRCAN_R0 : CAN Module 0 Software Reset
bits : 0 - 0 (1 bit)
SYSCTL_SRCAN_R1 : CAN Module 1 Software Reset
bits : 1 - 2 (2 bit)
Controller Area Network Software Reset
address_offset : 0x534 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRCAN_R0 : CAN Module 0 Software Reset
bits : 0 - 0 (1 bit)
SYSCTL_SRCAN_R1 : CAN Module 1 Software Reset
bits : 1 - 2 (2 bit)
Analog-to-Digital Converter Software Reset
address_offset : 0x538 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRADC_R0 : ADC Module 0 Software Reset
bits : 0 - 0 (1 bit)
SYSCTL_SRADC_R1 : ADC Module 1 Software Reset
bits : 1 - 2 (2 bit)
Analog-to-Digital Converter Software Reset
address_offset : 0x538 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRADC_R0 : ADC Module 0 Software Reset
bits : 0 - 0 (1 bit)
SYSCTL_SRADC_R1 : ADC Module 1 Software Reset
bits : 1 - 2 (2 bit)
Analog Comparator Software Reset
address_offset : 0x53C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRACMP_R0 : Analog Comparator Module 0 Software Reset
bits : 0 - 0 (1 bit)
Analog Comparator Software Reset
address_offset : 0x53C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRACMP_R0 : Analog Comparator Module 0 Software Reset
bits : 0 - 0 (1 bit)
Interrupt Mask Control
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_IMC_BORIM : Brown-Out Reset Interrupt Mask
bits : 1 - 2 (2 bit)
SYSCTL_IMC_MOFIM : Main Oscillator Failure Interrupt Mask
bits : 3 - 6 (4 bit)
SYSCTL_IMC_PLLLIM : PLL Lock Interrupt Mask
bits : 6 - 12 (7 bit)
SYSCTL_IMC_MOSCPUPIM : MOSC Power Up Interrupt Mask
bits : 8 - 16 (9 bit)
Interrupt Mask Control
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_IMC_BORIM : Brown-Out Reset Interrupt Mask
bits : 1 - 2 (2 bit)
SYSCTL_IMC_MOFIM : Main Oscillator Failure Interrupt Mask
bits : 3 - 6 (4 bit)
SYSCTL_IMC_PLLLIM : PLL Lock Interrupt Mask
bits : 6 - 12 (7 bit)
SYSCTL_IMC_MOSCPUPIM : MOSC Power Up Interrupt Mask
bits : 8 - 16 (9 bit)
Pulse Width Modulator Software Reset
address_offset : 0x540 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRPWM_R0 : PWM Module 0 Software Reset
bits : 0 - 0 (1 bit)
Pulse Width Modulator Software Reset
address_offset : 0x540 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRPWM_R0 : PWM Module 0 Software Reset
bits : 0 - 0 (1 bit)
Quadrature Encoder Interface Software Reset
address_offset : 0x544 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRQEI_R0 : QEI Module 0 Software Reset
bits : 0 - 0 (1 bit)
Quadrature Encoder Interface Software Reset
address_offset : 0x544 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRQEI_R0 : QEI Module 0 Software Reset
bits : 0 - 0 (1 bit)
EEPROM Software Reset
address_offset : 0x558 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SREEPROM_R0 : EEPROM Module Software Reset
bits : 0 - 0 (1 bit)
EEPROM Software Reset
address_offset : 0x558 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SREEPROM_R0 : EEPROM Module Software Reset
bits : 0 - 0 (1 bit)
CRC and Cryptographic Modules Software Reset
address_offset : 0x574 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRCCM_R0 : CRC and Cryptographic Modules Software Reset
bits : 0 - 0 (1 bit)
CRC and Cryptographic Modules Software Reset
address_offset : 0x574 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SRCCM_R0 : CRC and Cryptographic Modules Software Reset
bits : 0 - 0 (1 bit)
Masked Interrupt Status and Clear
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_MISC_BORMIS : BOR Masked Interrupt Status
bits : 1 - 2 (2 bit)
SYSCTL_MISC_MOFMIS : Main Oscillator Failure Masked Interrupt Status
bits : 3 - 6 (4 bit)
SYSCTL_MISC_PLLLMIS : PLL Lock Masked Interrupt Status
bits : 6 - 12 (7 bit)
SYSCTL_MISC_MOSCPUPMIS : MOSC Power Up Masked Interrupt Status
bits : 8 - 16 (9 bit)
Masked Interrupt Status and Clear
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_MISC_BORMIS : BOR Masked Interrupt Status
bits : 1 - 2 (2 bit)
SYSCTL_MISC_MOFMIS : Main Oscillator Failure Masked Interrupt Status
bits : 3 - 6 (4 bit)
SYSCTL_MISC_PLLLMIS : PLL Lock Masked Interrupt Status
bits : 6 - 12 (7 bit)
SYSCTL_MISC_MOSCPUPMIS : MOSC Power Up Masked Interrupt Status
bits : 8 - 16 (9 bit)
Ethernet MAC Software Reset
address_offset : 0x59C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SREMAC_R0 : Ethernet Controller MAC Module 0 Software Reset
bits : 0 - 0 (1 bit)
Ethernet MAC Software Reset
address_offset : 0x59C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SREMAC_R0 : Ethernet Controller MAC Module 0 Software Reset
bits : 0 - 0 (1 bit)
Reset Cause
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RESC_EXT : External Reset
bits : 0 - 0 (1 bit)
SYSCTL_RESC_POR : Power-On Reset
bits : 1 - 2 (2 bit)
SYSCTL_RESC_BOR : Brown-Out Reset
bits : 2 - 4 (3 bit)
SYSCTL_RESC_WDT0 : Watchdog Timer 0 Reset
bits : 3 - 6 (4 bit)
SYSCTL_RESC_SW : Software Reset
bits : 4 - 8 (5 bit)
SYSCTL_RESC_WDT1 : Watchdog Timer 1 Reset
bits : 5 - 10 (6 bit)
SYSCTL_RESC_HIB : HIB Reset
bits : 6 - 12 (7 bit)
SYSCTL_RESC_HSSR : HSSR Reset
bits : 12 - 24 (13 bit)
SYSCTL_RESC_MOSCFAIL : MOSC Failure Reset
bits : 16 - 32 (17 bit)
Reset Cause
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RESC_EXT : External Reset
bits : 0 - 0 (1 bit)
SYSCTL_RESC_POR : Power-On Reset
bits : 1 - 2 (2 bit)
SYSCTL_RESC_BOR : Brown-Out Reset
bits : 2 - 4 (3 bit)
SYSCTL_RESC_WDT0 : Watchdog Timer 0 Reset
bits : 3 - 6 (4 bit)
SYSCTL_RESC_SW : Software Reset
bits : 4 - 8 (5 bit)
SYSCTL_RESC_WDT1 : Watchdog Timer 1 Reset
bits : 5 - 10 (6 bit)
SYSCTL_RESC_HIB : HIB Reset
bits : 6 - 12 (7 bit)
SYSCTL_RESC_HSSR : HSSR Reset
bits : 12 - 24 (13 bit)
SYSCTL_RESC_MOSCFAIL : MOSC Failure Reset
bits : 16 - 32 (17 bit)
Power-Temperature Cause
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PWRTC_VDD_UBOR : VDD Under BOR Status
bits : 0 - 0 (1 bit)
SYSCTL_PWRTC_VDDA_UBOR : VDDA Under BOR Status
bits : 4 - 8 (5 bit)
Power-Temperature Cause
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PWRTC_VDD_UBOR : VDD Under BOR Status
bits : 0 - 0 (1 bit)
SYSCTL_PWRTC_VDDA_UBOR : VDDA Under BOR Status
bits : 4 - 8 (5 bit)
Watchdog Timer Run Mode Clock Gating Control
address_offset : 0x600 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCWD_R0 : Watchdog Timer 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGCWD_R1 : Watchdog Timer 1 Run Mode Clock Gating Control
bits : 1 - 2 (2 bit)
Watchdog Timer Run Mode Clock Gating Control
address_offset : 0x600 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCWD_R0 : Watchdog Timer 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGCWD_R1 : Watchdog Timer 1 Run Mode Clock Gating Control
bits : 1 - 2 (2 bit)
16/32-Bit General-Purpose Timer Run Mode Clock Gating Control
address_offset : 0x604 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCTIMER_R0 : 16/32-Bit General-Purpose Timer 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGCTIMER_R1 : 16/32-Bit General-Purpose Timer 1 Run Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_RCGCTIMER_R2 : 16/32-Bit General-Purpose Timer 2 Run Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_RCGCTIMER_R3 : 16/32-Bit General-Purpose Timer 3 Run Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_RCGCTIMER_R4 : 16/32-Bit General-Purpose Timer 4 Run Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_RCGCTIMER_R5 : 16/32-Bit General-Purpose Timer 5 Run Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_RCGCTIMER_R6 : 16/32-Bit General-Purpose Timer 6 Run Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_RCGCTIMER_R7 : 16/32-Bit General-Purpose Timer 7 Run Mode Clock Gating Control
bits : 7 - 14 (8 bit)
16/32-Bit General-Purpose Timer Run Mode Clock Gating Control
address_offset : 0x604 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCTIMER_R0 : 16/32-Bit General-Purpose Timer 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGCTIMER_R1 : 16/32-Bit General-Purpose Timer 1 Run Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_RCGCTIMER_R2 : 16/32-Bit General-Purpose Timer 2 Run Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_RCGCTIMER_R3 : 16/32-Bit General-Purpose Timer 3 Run Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_RCGCTIMER_R4 : 16/32-Bit General-Purpose Timer 4 Run Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_RCGCTIMER_R5 : 16/32-Bit General-Purpose Timer 5 Run Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_RCGCTIMER_R6 : 16/32-Bit General-Purpose Timer 6 Run Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_RCGCTIMER_R7 : 16/32-Bit General-Purpose Timer 7 Run Mode Clock Gating Control
bits : 7 - 14 (8 bit)
General-Purpose Input/Output Run Mode Clock Gating Control
address_offset : 0x608 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCGPIO_R0 : GPIO Port A Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGCGPIO_R1 : GPIO Port B Run Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_RCGCGPIO_R2 : GPIO Port C Run Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_RCGCGPIO_R3 : GPIO Port D Run Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_RCGCGPIO_R4 : GPIO Port E Run Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_RCGCGPIO_R5 : GPIO Port F Run Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_RCGCGPIO_R6 : GPIO Port G Run Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_RCGCGPIO_R7 : GPIO Port H Run Mode Clock Gating Control
bits : 7 - 14 (8 bit)
SYSCTL_RCGCGPIO_R8 : GPIO Port J Run Mode Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_RCGCGPIO_R9 : GPIO Port K Run Mode Clock Gating Control
bits : 9 - 18 (10 bit)
SYSCTL_RCGCGPIO_R10 : GPIO Port L Run Mode Clock Gating Control
bits : 10 - 20 (11 bit)
SYSCTL_RCGCGPIO_R11 : GPIO Port M Run Mode Clock Gating Control
bits : 11 - 22 (12 bit)
SYSCTL_RCGCGPIO_R12 : GPIO Port N Run Mode Clock Gating Control
bits : 12 - 24 (13 bit)
SYSCTL_RCGCGPIO_R13 : GPIO Port P Run Mode Clock Gating Control
bits : 13 - 26 (14 bit)
SYSCTL_RCGCGPIO_R14 : GPIO Port Q Run Mode Clock Gating Control
bits : 14 - 28 (15 bit)
General-Purpose Input/Output Run Mode Clock Gating Control
address_offset : 0x608 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCGPIO_R0 : GPIO Port A Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGCGPIO_R1 : GPIO Port B Run Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_RCGCGPIO_R2 : GPIO Port C Run Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_RCGCGPIO_R3 : GPIO Port D Run Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_RCGCGPIO_R4 : GPIO Port E Run Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_RCGCGPIO_R5 : GPIO Port F Run Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_RCGCGPIO_R6 : GPIO Port G Run Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_RCGCGPIO_R7 : GPIO Port H Run Mode Clock Gating Control
bits : 7 - 14 (8 bit)
SYSCTL_RCGCGPIO_R8 : GPIO Port J Run Mode Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_RCGCGPIO_R9 : GPIO Port K Run Mode Clock Gating Control
bits : 9 - 18 (10 bit)
SYSCTL_RCGCGPIO_R10 : GPIO Port L Run Mode Clock Gating Control
bits : 10 - 20 (11 bit)
SYSCTL_RCGCGPIO_R11 : GPIO Port M Run Mode Clock Gating Control
bits : 11 - 22 (12 bit)
SYSCTL_RCGCGPIO_R12 : GPIO Port N Run Mode Clock Gating Control
bits : 12 - 24 (13 bit)
SYSCTL_RCGCGPIO_R13 : GPIO Port P Run Mode Clock Gating Control
bits : 13 - 26 (14 bit)
SYSCTL_RCGCGPIO_R14 : GPIO Port Q Run Mode Clock Gating Control
bits : 14 - 28 (15 bit)
Micro Direct Memory Access Run Mode Clock Gating Control
address_offset : 0x60C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCDMA_R0 : uDMA Module Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Micro Direct Memory Access Run Mode Clock Gating Control
address_offset : 0x60C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCDMA_R0 : uDMA Module Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
EPI Run Mode Clock Gating Control
address_offset : 0x610 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCEPI_R0 : EPI Module Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
EPI Run Mode Clock Gating Control
address_offset : 0x610 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCEPI_R0 : EPI Module Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Hibernation Run Mode Clock Gating Control
address_offset : 0x614 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCHIB_R0 : Hibernation Module Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Hibernation Run Mode Clock Gating Control
address_offset : 0x614 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCHIB_R0 : Hibernation Module Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control
address_offset : 0x618 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCUART_R0 : UART Module 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGCUART_R1 : UART Module 1 Run Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_RCGCUART_R2 : UART Module 2 Run Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_RCGCUART_R3 : UART Module 3 Run Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_RCGCUART_R4 : UART Module 4 Run Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_RCGCUART_R5 : UART Module 5 Run Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_RCGCUART_R6 : UART Module 6 Run Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_RCGCUART_R7 : UART Module 7 Run Mode Clock Gating Control
bits : 7 - 14 (8 bit)
Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control
address_offset : 0x618 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCUART_R0 : UART Module 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGCUART_R1 : UART Module 1 Run Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_RCGCUART_R2 : UART Module 2 Run Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_RCGCUART_R3 : UART Module 3 Run Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_RCGCUART_R4 : UART Module 4 Run Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_RCGCUART_R5 : UART Module 5 Run Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_RCGCUART_R6 : UART Module 6 Run Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_RCGCUART_R7 : UART Module 7 Run Mode Clock Gating Control
bits : 7 - 14 (8 bit)
Synchronous Serial Interface Run Mode Clock Gating Control
address_offset : 0x61C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCSSI_R0 : SSI Module 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGCSSI_R1 : SSI Module 1 Run Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_RCGCSSI_R2 : SSI Module 2 Run Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_RCGCSSI_R3 : SSI Module 3 Run Mode Clock Gating Control
bits : 3 - 6 (4 bit)
Synchronous Serial Interface Run Mode Clock Gating Control
address_offset : 0x61C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCSSI_R0 : SSI Module 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGCSSI_R1 : SSI Module 1 Run Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_RCGCSSI_R2 : SSI Module 2 Run Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_RCGCSSI_R3 : SSI Module 3 Run Mode Clock Gating Control
bits : 3 - 6 (4 bit)
Inter-Integrated Circuit Run Mode Clock Gating Control
address_offset : 0x620 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCI2C_R0 : I2C Module 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGCI2C_R1 : I2C Module 1 Run Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_RCGCI2C_R2 : I2C Module 2 Run Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_RCGCI2C_R3 : I2C Module 3 Run Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_RCGCI2C_R4 : I2C Module 4 Run Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_RCGCI2C_R5 : I2C Module 5 Run Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_RCGCI2C_R6 : I2C Module 6 Run Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_RCGCI2C_R7 : I2C Module 7 Run Mode Clock Gating Control
bits : 7 - 14 (8 bit)
SYSCTL_RCGCI2C_R8 : I2C Module 8 Run Mode Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_RCGCI2C_R9 : I2C Module 9 Run Mode Clock Gating Control
bits : 9 - 18 (10 bit)
Inter-Integrated Circuit Run Mode Clock Gating Control
address_offset : 0x620 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCI2C_R0 : I2C Module 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGCI2C_R1 : I2C Module 1 Run Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_RCGCI2C_R2 : I2C Module 2 Run Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_RCGCI2C_R3 : I2C Module 3 Run Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_RCGCI2C_R4 : I2C Module 4 Run Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_RCGCI2C_R5 : I2C Module 5 Run Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_RCGCI2C_R6 : I2C Module 6 Run Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_RCGCI2C_R7 : I2C Module 7 Run Mode Clock Gating Control
bits : 7 - 14 (8 bit)
SYSCTL_RCGCI2C_R8 : I2C Module 8 Run Mode Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_RCGCI2C_R9 : I2C Module 9 Run Mode Clock Gating Control
bits : 9 - 18 (10 bit)
Universal Serial Bus Run Mode Clock Gating Control
address_offset : 0x628 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCUSB_R0 : USB Module Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Universal Serial Bus Run Mode Clock Gating Control
address_offset : 0x628 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCUSB_R0 : USB Module Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Ethernet PHY Run Mode Clock Gating Control
address_offset : 0x630 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCEPHY_R0 : Ethernet PHY Module Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Ethernet PHY Run Mode Clock Gating Control
address_offset : 0x630 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCEPHY_R0 : Ethernet PHY Module Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Controller Area Network Run Mode Clock Gating Control
address_offset : 0x634 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCCAN_R0 : CAN Module 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGCCAN_R1 : CAN Module 1 Run Mode Clock Gating Control
bits : 1 - 2 (2 bit)
Controller Area Network Run Mode Clock Gating Control
address_offset : 0x634 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCCAN_R0 : CAN Module 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGCCAN_R1 : CAN Module 1 Run Mode Clock Gating Control
bits : 1 - 2 (2 bit)
Analog-to-Digital Converter Run Mode Clock Gating Control
address_offset : 0x638 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCADC_R0 : ADC Module 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGCADC_R1 : ADC Module 1 Run Mode Clock Gating Control
bits : 1 - 2 (2 bit)
Analog-to-Digital Converter Run Mode Clock Gating Control
address_offset : 0x638 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCADC_R0 : ADC Module 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_RCGCADC_R1 : ADC Module 1 Run Mode Clock Gating Control
bits : 1 - 2 (2 bit)
Analog Comparator Run Mode Clock Gating Control
address_offset : 0x63C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCACMP_R0 : Analog Comparator Module 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Analog Comparator Run Mode Clock Gating Control
address_offset : 0x63C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCACMP_R0 : Analog Comparator Module 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
NMI Cause Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_NMIC_EXTERNAL : External Pin NMI
bits : 0 - 0 (1 bit)
SYSCTL_NMIC_POWER : Power/Brown Out Event NMI
bits : 2 - 4 (3 bit)
SYSCTL_NMIC_WDT0 : Watch Dog Timer (WDT) 0 NMI
bits : 3 - 6 (4 bit)
SYSCTL_NMIC_WDT1 : Watch Dog Timer (WDT) 1 NMI
bits : 5 - 10 (6 bit)
SYSCTL_NMIC_TAMPER : Tamper Event NMI
bits : 9 - 18 (10 bit)
SYSCTL_NMIC_MOSCFAIL : MOSC Failure NMI
bits : 16 - 32 (17 bit)
NMI Cause Register
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_NMIC_EXTERNAL : External Pin NMI
bits : 0 - 0 (1 bit)
SYSCTL_NMIC_POWER : Power/Brown Out Event NMI
bits : 2 - 4 (3 bit)
SYSCTL_NMIC_WDT0 : Watch Dog Timer (WDT) 0 NMI
bits : 3 - 6 (4 bit)
SYSCTL_NMIC_WDT1 : Watch Dog Timer (WDT) 1 NMI
bits : 5 - 10 (6 bit)
SYSCTL_NMIC_TAMPER : Tamper Event NMI
bits : 9 - 18 (10 bit)
SYSCTL_NMIC_MOSCFAIL : MOSC Failure NMI
bits : 16 - 32 (17 bit)
Pulse Width Modulator Run Mode Clock Gating Control
address_offset : 0x640 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCPWM_R0 : PWM Module 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Pulse Width Modulator Run Mode Clock Gating Control
address_offset : 0x640 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCPWM_R0 : PWM Module 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Quadrature Encoder Interface Run Mode Clock Gating Control
address_offset : 0x644 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCQEI_R0 : QEI Module 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Quadrature Encoder Interface Run Mode Clock Gating Control
address_offset : 0x644 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCQEI_R0 : QEI Module 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
EEPROM Run Mode Clock Gating Control
address_offset : 0x658 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCEEPROM_R0 : EEPROM Module Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
EEPROM Run Mode Clock Gating Control
address_offset : 0x658 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCEEPROM_R0 : EEPROM Module Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
CRC and Cryptographic Modules Run Mode Clock Gating Control
address_offset : 0x674 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCCCM_R0 : CRC and Cryptographic Modules Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
CRC and Cryptographic Modules Run Mode Clock Gating Control
address_offset : 0x674 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCCCM_R0 : CRC and Cryptographic Modules Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Ethernet MAC Run Mode Clock Gating Control
address_offset : 0x69C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCEMAC_R0 : Ethernet MAC Module 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Ethernet MAC Run Mode Clock Gating Control
address_offset : 0x69C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RCGCEMAC_R0 : Ethernet MAC Module 0 Run Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Watchdog Timer Sleep Mode Clock Gating Control
address_offset : 0x700 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCWD_S0 : Watchdog Timer 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGCWD_S1 : Watchdog Timer 1 Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
Watchdog Timer Sleep Mode Clock Gating Control
address_offset : 0x700 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCWD_S0 : Watchdog Timer 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGCWD_S1 : Watchdog Timer 1 Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control
address_offset : 0x704 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCTIMER_S0 : 16/32-Bit General-Purpose Timer 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGCTIMER_S1 : 16/32-Bit General-Purpose Timer 1 Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_SCGCTIMER_S2 : 16/32-Bit General-Purpose Timer 2 Sleep Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_SCGCTIMER_S3 : 16/32-Bit General-Purpose Timer 3 Sleep Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_SCGCTIMER_S4 : 16/32-Bit General-Purpose Timer 4 Sleep Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_SCGCTIMER_S5 : 16/32-Bit General-Purpose Timer 5 Sleep Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_SCGCTIMER_S6 : 16/32-Bit General-Purpose Timer 6 Sleep Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_SCGCTIMER_S7 : 16/32-Bit General-Purpose Timer 7 Sleep Mode Clock Gating Control
bits : 7 - 14 (8 bit)
16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control
address_offset : 0x704 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCTIMER_S0 : 16/32-Bit General-Purpose Timer 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGCTIMER_S1 : 16/32-Bit General-Purpose Timer 1 Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_SCGCTIMER_S2 : 16/32-Bit General-Purpose Timer 2 Sleep Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_SCGCTIMER_S3 : 16/32-Bit General-Purpose Timer 3 Sleep Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_SCGCTIMER_S4 : 16/32-Bit General-Purpose Timer 4 Sleep Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_SCGCTIMER_S5 : 16/32-Bit General-Purpose Timer 5 Sleep Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_SCGCTIMER_S6 : 16/32-Bit General-Purpose Timer 6 Sleep Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_SCGCTIMER_S7 : 16/32-Bit General-Purpose Timer 7 Sleep Mode Clock Gating Control
bits : 7 - 14 (8 bit)
General-Purpose Input/Output Sleep Mode Clock Gating Control
address_offset : 0x708 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCGPIO_S0 : GPIO Port A Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGCGPIO_S1 : GPIO Port B Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_SCGCGPIO_S2 : GPIO Port C Sleep Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_SCGCGPIO_S3 : GPIO Port D Sleep Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_SCGCGPIO_S4 : GPIO Port E Sleep Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_SCGCGPIO_S5 : GPIO Port F Sleep Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_SCGCGPIO_S6 : GPIO Port G Sleep Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_SCGCGPIO_S7 : GPIO Port H Sleep Mode Clock Gating Control
bits : 7 - 14 (8 bit)
SYSCTL_SCGCGPIO_S8 : GPIO Port J Sleep Mode Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_SCGCGPIO_S9 : GPIO Port K Sleep Mode Clock Gating Control
bits : 9 - 18 (10 bit)
SYSCTL_SCGCGPIO_S10 : GPIO Port L Sleep Mode Clock Gating Control
bits : 10 - 20 (11 bit)
SYSCTL_SCGCGPIO_S11 : GPIO Port M Sleep Mode Clock Gating Control
bits : 11 - 22 (12 bit)
SYSCTL_SCGCGPIO_S12 : GPIO Port N Sleep Mode Clock Gating Control
bits : 12 - 24 (13 bit)
SYSCTL_SCGCGPIO_S13 : GPIO Port P Sleep Mode Clock Gating Control
bits : 13 - 26 (14 bit)
SYSCTL_SCGCGPIO_S14 : GPIO Port Q Sleep Mode Clock Gating Control
bits : 14 - 28 (15 bit)
General-Purpose Input/Output Sleep Mode Clock Gating Control
address_offset : 0x708 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCGPIO_S0 : GPIO Port A Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGCGPIO_S1 : GPIO Port B Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_SCGCGPIO_S2 : GPIO Port C Sleep Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_SCGCGPIO_S3 : GPIO Port D Sleep Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_SCGCGPIO_S4 : GPIO Port E Sleep Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_SCGCGPIO_S5 : GPIO Port F Sleep Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_SCGCGPIO_S6 : GPIO Port G Sleep Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_SCGCGPIO_S7 : GPIO Port H Sleep Mode Clock Gating Control
bits : 7 - 14 (8 bit)
SYSCTL_SCGCGPIO_S8 : GPIO Port J Sleep Mode Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_SCGCGPIO_S9 : GPIO Port K Sleep Mode Clock Gating Control
bits : 9 - 18 (10 bit)
SYSCTL_SCGCGPIO_S10 : GPIO Port L Sleep Mode Clock Gating Control
bits : 10 - 20 (11 bit)
SYSCTL_SCGCGPIO_S11 : GPIO Port M Sleep Mode Clock Gating Control
bits : 11 - 22 (12 bit)
SYSCTL_SCGCGPIO_S12 : GPIO Port N Sleep Mode Clock Gating Control
bits : 12 - 24 (13 bit)
SYSCTL_SCGCGPIO_S13 : GPIO Port P Sleep Mode Clock Gating Control
bits : 13 - 26 (14 bit)
SYSCTL_SCGCGPIO_S14 : GPIO Port Q Sleep Mode Clock Gating Control
bits : 14 - 28 (15 bit)
Micro Direct Memory Access Sleep Mode Clock Gating Control
address_offset : 0x70C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCDMA_S0 : uDMA Module Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Micro Direct Memory Access Sleep Mode Clock Gating Control
address_offset : 0x70C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCDMA_S0 : uDMA Module Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
EPI Sleep Mode Clock Gating Control
address_offset : 0x710 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCEPI_S0 : EPI Module Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
EPI Sleep Mode Clock Gating Control
address_offset : 0x710 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCEPI_S0 : EPI Module Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Hibernation Sleep Mode Clock Gating Control
address_offset : 0x714 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCHIB_S0 : Hibernation Module Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Hibernation Sleep Mode Clock Gating Control
address_offset : 0x714 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCHIB_S0 : Hibernation Module Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control
address_offset : 0x718 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCUART_S0 : UART Module 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGCUART_S1 : UART Module 1 Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_SCGCUART_S2 : UART Module 2 Sleep Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_SCGCUART_S3 : UART Module 3 Sleep Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_SCGCUART_S4 : UART Module 4 Sleep Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_SCGCUART_S5 : UART Module 5 Sleep Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_SCGCUART_S6 : UART Module 6 Sleep Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_SCGCUART_S7 : UART Module 7 Sleep Mode Clock Gating Control
bits : 7 - 14 (8 bit)
Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control
address_offset : 0x718 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCUART_S0 : UART Module 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGCUART_S1 : UART Module 1 Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_SCGCUART_S2 : UART Module 2 Sleep Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_SCGCUART_S3 : UART Module 3 Sleep Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_SCGCUART_S4 : UART Module 4 Sleep Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_SCGCUART_S5 : UART Module 5 Sleep Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_SCGCUART_S6 : UART Module 6 Sleep Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_SCGCUART_S7 : UART Module 7 Sleep Mode Clock Gating Control
bits : 7 - 14 (8 bit)
Synchronous Serial Interface Sleep Mode Clock Gating Control
address_offset : 0x71C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCSSI_S0 : SSI Module 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGCSSI_S1 : SSI Module 1 Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_SCGCSSI_S2 : SSI Module 2 Sleep Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_SCGCSSI_S3 : SSI Module 3 Sleep Mode Clock Gating Control
bits : 3 - 6 (4 bit)
Synchronous Serial Interface Sleep Mode Clock Gating Control
address_offset : 0x71C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCSSI_S0 : SSI Module 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGCSSI_S1 : SSI Module 1 Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_SCGCSSI_S2 : SSI Module 2 Sleep Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_SCGCSSI_S3 : SSI Module 3 Sleep Mode Clock Gating Control
bits : 3 - 6 (4 bit)
Inter-Integrated Circuit Sleep Mode Clock Gating Control
address_offset : 0x720 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCI2C_S0 : I2C Module 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGCI2C_S1 : I2C Module 1 Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_SCGCI2C_S2 : I2C Module 2 Sleep Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_SCGCI2C_S3 : I2C Module 3 Sleep Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_SCGCI2C_S4 : I2C Module 4 Sleep Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_SCGCI2C_S5 : I2C Module 5 Sleep Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_SCGCI2C_S6 : I2C Module 6 Sleep Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_SCGCI2C_S7 : I2C Module 7 Sleep Mode Clock Gating Control
bits : 7 - 14 (8 bit)
SYSCTL_SCGCI2C_S8 : I2C Module 8 Sleep Mode Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_SCGCI2C_S9 : I2C Module 9 Sleep Mode Clock Gating Control
bits : 9 - 18 (10 bit)
Inter-Integrated Circuit Sleep Mode Clock Gating Control
address_offset : 0x720 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCI2C_S0 : I2C Module 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGCI2C_S1 : I2C Module 1 Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_SCGCI2C_S2 : I2C Module 2 Sleep Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_SCGCI2C_S3 : I2C Module 3 Sleep Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_SCGCI2C_S4 : I2C Module 4 Sleep Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_SCGCI2C_S5 : I2C Module 5 Sleep Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_SCGCI2C_S6 : I2C Module 6 Sleep Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_SCGCI2C_S7 : I2C Module 7 Sleep Mode Clock Gating Control
bits : 7 - 14 (8 bit)
SYSCTL_SCGCI2C_S8 : I2C Module 8 Sleep Mode Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_SCGCI2C_S9 : I2C Module 9 Sleep Mode Clock Gating Control
bits : 9 - 18 (10 bit)
Universal Serial Bus Sleep Mode Clock Gating Control
address_offset : 0x728 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCUSB_S0 : USB Module Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Universal Serial Bus Sleep Mode Clock Gating Control
address_offset : 0x728 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCUSB_S0 : USB Module Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Ethernet PHY Sleep Mode Clock Gating Control
address_offset : 0x730 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCEPHY_S0 : PHY Module Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Ethernet PHY Sleep Mode Clock Gating Control
address_offset : 0x730 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCEPHY_S0 : PHY Module Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Controller Area Network Sleep Mode Clock Gating Control
address_offset : 0x734 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCCAN_S0 : CAN Module 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGCCAN_S1 : CAN Module 1 Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
Controller Area Network Sleep Mode Clock Gating Control
address_offset : 0x734 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCCAN_S0 : CAN Module 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGCCAN_S1 : CAN Module 1 Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
Analog-to-Digital Converter Sleep Mode Clock Gating Control
address_offset : 0x738 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCADC_S0 : ADC Module 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGCADC_S1 : ADC Module 1 Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
Analog-to-Digital Converter Sleep Mode Clock Gating Control
address_offset : 0x738 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCADC_S0 : ADC Module 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_SCGCADC_S1 : ADC Module 1 Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
Analog Comparator Sleep Mode Clock Gating Control
address_offset : 0x73C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCACMP_S0 : Analog Comparator Module 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Analog Comparator Sleep Mode Clock Gating Control
address_offset : 0x73C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCACMP_S0 : Analog Comparator Module 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Pulse Width Modulator Sleep Mode Clock Gating Control
address_offset : 0x740 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCPWM_S0 : PWM Module 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Pulse Width Modulator Sleep Mode Clock Gating Control
address_offset : 0x740 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCPWM_S0 : PWM Module 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Quadrature Encoder Interface Sleep Mode Clock Gating Control
address_offset : 0x744 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCQEI_S0 : QEI Module 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Quadrature Encoder Interface Sleep Mode Clock Gating Control
address_offset : 0x744 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCQEI_S0 : QEI Module 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
EEPROM Sleep Mode Clock Gating Control
address_offset : 0x758 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCEEPROM_S0 : EEPROM Module Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
EEPROM Sleep Mode Clock Gating Control
address_offset : 0x758 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCEEPROM_S0 : EEPROM Module Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
CRC and Cryptographic Modules Sleep Mode Clock Gating Control
address_offset : 0x774 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCCCM_S0 : CRC and Cryptographic Modules Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
CRC and Cryptographic Modules Sleep Mode Clock Gating Control
address_offset : 0x774 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCCCM_S0 : CRC and Cryptographic Modules Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Ethernet MAC Sleep Mode Clock Gating Control
address_offset : 0x79C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCEMAC_S0 : Ethernet MAC Module 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Ethernet MAC Sleep Mode Clock Gating Control
address_offset : 0x79C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_SCGCEMAC_S0 : Ethernet MAC Module 0 Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Main Oscillator Control
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_MOSCCTL_CVAL : Clock Validation for MOSC
bits : 0 - 0 (1 bit)
SYSCTL_MOSCCTL_MOSCIM : MOSC Failure Action
bits : 1 - 2 (2 bit)
SYSCTL_MOSCCTL_NOXTAL : No Crystal Connected
bits : 2 - 4 (3 bit)
SYSCTL_MOSCCTL_PWRDN : Power Down
bits : 3 - 6 (4 bit)
SYSCTL_MOSCCTL_OSCRNG : Oscillator Range
bits : 4 - 8 (5 bit)
Main Oscillator Control
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_MOSCCTL_CVAL : Clock Validation for MOSC
bits : 0 - 0 (1 bit)
SYSCTL_MOSCCTL_MOSCIM : MOSC Failure Action
bits : 1 - 2 (2 bit)
SYSCTL_MOSCCTL_NOXTAL : No Crystal Connected
bits : 2 - 4 (3 bit)
SYSCTL_MOSCCTL_PWRDN : Power Down
bits : 3 - 6 (4 bit)
SYSCTL_MOSCCTL_OSCRNG : Oscillator Range
bits : 4 - 8 (5 bit)
Watchdog Timer Deep-Sleep Mode Clock Gating Control
address_offset : 0x800 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCWD_D0 : Watchdog Timer 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGCWD_D1 : Watchdog Timer 1 Deep-Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
Watchdog Timer Deep-Sleep Mode Clock Gating Control
address_offset : 0x800 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCWD_D0 : Watchdog Timer 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGCWD_D1 : Watchdog Timer 1 Deep-Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control
address_offset : 0x804 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCTIMER_D0 : 16/32-Bit General-Purpose Timer 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGCTIMER_D1 : 16/32-Bit General-Purpose Timer 1 Deep-Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_DCGCTIMER_D2 : 16/32-Bit General-Purpose Timer 2 Deep-Sleep Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_DCGCTIMER_D3 : 16/32-Bit General-Purpose Timer 3 Deep-Sleep Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_DCGCTIMER_D4 : 16/32-Bit General-Purpose Timer 4 Deep-Sleep Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_DCGCTIMER_D5 : 16/32-Bit General-Purpose Timer 5 Deep-Sleep Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_DCGCTIMER_D6 : 16/32-Bit General-Purpose Timer 6 Deep-Sleep Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_DCGCTIMER_D7 : 16/32-Bit General-Purpose Timer 7 Deep-Sleep Mode Clock Gating Control
bits : 7 - 14 (8 bit)
16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control
address_offset : 0x804 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCTIMER_D0 : 16/32-Bit General-Purpose Timer 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGCTIMER_D1 : 16/32-Bit General-Purpose Timer 1 Deep-Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_DCGCTIMER_D2 : 16/32-Bit General-Purpose Timer 2 Deep-Sleep Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_DCGCTIMER_D3 : 16/32-Bit General-Purpose Timer 3 Deep-Sleep Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_DCGCTIMER_D4 : 16/32-Bit General-Purpose Timer 4 Deep-Sleep Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_DCGCTIMER_D5 : 16/32-Bit General-Purpose Timer 5 Deep-Sleep Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_DCGCTIMER_D6 : 16/32-Bit General-Purpose Timer 6 Deep-Sleep Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_DCGCTIMER_D7 : 16/32-Bit General-Purpose Timer 7 Deep-Sleep Mode Clock Gating Control
bits : 7 - 14 (8 bit)
General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control
address_offset : 0x808 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCGPIO_D0 : GPIO Port A Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGCGPIO_D1 : GPIO Port B Deep-Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_DCGCGPIO_D2 : GPIO Port C Deep-Sleep Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_DCGCGPIO_D3 : GPIO Port D Deep-Sleep Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_DCGCGPIO_D4 : GPIO Port E Deep-Sleep Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_DCGCGPIO_D5 : GPIO Port F Deep-Sleep Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_DCGCGPIO_D6 : GPIO Port G Deep-Sleep Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_DCGCGPIO_D7 : GPIO Port H Deep-Sleep Mode Clock Gating Control
bits : 7 - 14 (8 bit)
SYSCTL_DCGCGPIO_D8 : GPIO Port J Deep-Sleep Mode Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_DCGCGPIO_D9 : GPIO Port K Deep-Sleep Mode Clock Gating Control
bits : 9 - 18 (10 bit)
SYSCTL_DCGCGPIO_D10 : GPIO Port L Deep-Sleep Mode Clock Gating Control
bits : 10 - 20 (11 bit)
SYSCTL_DCGCGPIO_D11 : GPIO Port M Deep-Sleep Mode Clock Gating Control
bits : 11 - 22 (12 bit)
SYSCTL_DCGCGPIO_D12 : GPIO Port N Deep-Sleep Mode Clock Gating Control
bits : 12 - 24 (13 bit)
SYSCTL_DCGCGPIO_D13 : GPIO Port P Deep-Sleep Mode Clock Gating Control
bits : 13 - 26 (14 bit)
SYSCTL_DCGCGPIO_D14 : GPIO Port Q Deep-Sleep Mode Clock Gating Control
bits : 14 - 28 (15 bit)
General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control
address_offset : 0x808 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCGPIO_D0 : GPIO Port A Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGCGPIO_D1 : GPIO Port B Deep-Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_DCGCGPIO_D2 : GPIO Port C Deep-Sleep Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_DCGCGPIO_D3 : GPIO Port D Deep-Sleep Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_DCGCGPIO_D4 : GPIO Port E Deep-Sleep Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_DCGCGPIO_D5 : GPIO Port F Deep-Sleep Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_DCGCGPIO_D6 : GPIO Port G Deep-Sleep Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_DCGCGPIO_D7 : GPIO Port H Deep-Sleep Mode Clock Gating Control
bits : 7 - 14 (8 bit)
SYSCTL_DCGCGPIO_D8 : GPIO Port J Deep-Sleep Mode Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_DCGCGPIO_D9 : GPIO Port K Deep-Sleep Mode Clock Gating Control
bits : 9 - 18 (10 bit)
SYSCTL_DCGCGPIO_D10 : GPIO Port L Deep-Sleep Mode Clock Gating Control
bits : 10 - 20 (11 bit)
SYSCTL_DCGCGPIO_D11 : GPIO Port M Deep-Sleep Mode Clock Gating Control
bits : 11 - 22 (12 bit)
SYSCTL_DCGCGPIO_D12 : GPIO Port N Deep-Sleep Mode Clock Gating Control
bits : 12 - 24 (13 bit)
SYSCTL_DCGCGPIO_D13 : GPIO Port P Deep-Sleep Mode Clock Gating Control
bits : 13 - 26 (14 bit)
SYSCTL_DCGCGPIO_D14 : GPIO Port Q Deep-Sleep Mode Clock Gating Control
bits : 14 - 28 (15 bit)
Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control
address_offset : 0x80C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCDMA_D0 : uDMA Module Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control
address_offset : 0x80C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCDMA_D0 : uDMA Module Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
EPI Deep-Sleep Mode Clock Gating Control
address_offset : 0x810 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCEPI_D0 : EPI Module Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
EPI Deep-Sleep Mode Clock Gating Control
address_offset : 0x810 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCEPI_D0 : EPI Module Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Hibernation Deep-Sleep Mode Clock Gating Control
address_offset : 0x814 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCHIB_D0 : Hibernation Module Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Hibernation Deep-Sleep Mode Clock Gating Control
address_offset : 0x814 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCHIB_D0 : Hibernation Module Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control
address_offset : 0x818 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCUART_D0 : UART Module 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGCUART_D1 : UART Module 1 Deep-Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_DCGCUART_D2 : UART Module 2 Deep-Sleep Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_DCGCUART_D3 : UART Module 3 Deep-Sleep Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_DCGCUART_D4 : UART Module 4 Deep-Sleep Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_DCGCUART_D5 : UART Module 5 Deep-Sleep Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_DCGCUART_D6 : UART Module 6 Deep-Sleep Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_DCGCUART_D7 : UART Module 7 Deep-Sleep Mode Clock Gating Control
bits : 7 - 14 (8 bit)
Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control
address_offset : 0x818 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCUART_D0 : UART Module 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGCUART_D1 : UART Module 1 Deep-Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_DCGCUART_D2 : UART Module 2 Deep-Sleep Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_DCGCUART_D3 : UART Module 3 Deep-Sleep Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_DCGCUART_D4 : UART Module 4 Deep-Sleep Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_DCGCUART_D5 : UART Module 5 Deep-Sleep Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_DCGCUART_D6 : UART Module 6 Deep-Sleep Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_DCGCUART_D7 : UART Module 7 Deep-Sleep Mode Clock Gating Control
bits : 7 - 14 (8 bit)
Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control
address_offset : 0x81C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCSSI_D0 : SSI Module 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGCSSI_D1 : SSI Module 1 Deep-Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_DCGCSSI_D2 : SSI Module 2 Deep-Sleep Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_DCGCSSI_D3 : SSI Module 3 Deep-Sleep Mode Clock Gating Control
bits : 3 - 6 (4 bit)
Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control
address_offset : 0x81C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCSSI_D0 : SSI Module 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGCSSI_D1 : SSI Module 1 Deep-Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_DCGCSSI_D2 : SSI Module 2 Deep-Sleep Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_DCGCSSI_D3 : SSI Module 3 Deep-Sleep Mode Clock Gating Control
bits : 3 - 6 (4 bit)
Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control
address_offset : 0x820 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCI2C_D0 : I2C Module 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGCI2C_D1 : I2C Module 1 Deep-Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_DCGCI2C_D2 : I2C Module 2 Deep-Sleep Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_DCGCI2C_D3 : I2C Module 3 Deep-Sleep Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_DCGCI2C_D4 : I2C Module 4 Deep-Sleep Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_DCGCI2C_D5 : I2C Module 5 Deep-Sleep Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_DCGCI2C_D6 : I2C Module 6 Deep-Sleep Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_DCGCI2C_D7 : I2C Module 7 Deep-Sleep Mode Clock Gating Control
bits : 7 - 14 (8 bit)
SYSCTL_DCGCI2C_D8 : I2C Module 8 Deep-Sleep Mode Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_DCGCI2C_D9 : I2C Module 9 Deep-Sleep Mode Clock Gating Control
bits : 9 - 18 (10 bit)
Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control
address_offset : 0x820 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCI2C_D0 : I2C Module 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGCI2C_D1 : I2C Module 1 Deep-Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
SYSCTL_DCGCI2C_D2 : I2C Module 2 Deep-Sleep Mode Clock Gating Control
bits : 2 - 4 (3 bit)
SYSCTL_DCGCI2C_D3 : I2C Module 3 Deep-Sleep Mode Clock Gating Control
bits : 3 - 6 (4 bit)
SYSCTL_DCGCI2C_D4 : I2C Module 4 Deep-Sleep Mode Clock Gating Control
bits : 4 - 8 (5 bit)
SYSCTL_DCGCI2C_D5 : I2C Module 5 Deep-Sleep Mode Clock Gating Control
bits : 5 - 10 (6 bit)
SYSCTL_DCGCI2C_D6 : I2C Module 6 Deep-Sleep Mode Clock Gating Control
bits : 6 - 12 (7 bit)
SYSCTL_DCGCI2C_D7 : I2C Module 7 Deep-Sleep Mode Clock Gating Control
bits : 7 - 14 (8 bit)
SYSCTL_DCGCI2C_D8 : I2C Module 8 Deep-Sleep Mode Clock Gating Control
bits : 8 - 16 (9 bit)
SYSCTL_DCGCI2C_D9 : I2C Module 9 Deep-Sleep Mode Clock Gating Control
bits : 9 - 18 (10 bit)
Universal Serial Bus Deep-Sleep Mode Clock Gating Control
address_offset : 0x828 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCUSB_D0 : USB Module Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Universal Serial Bus Deep-Sleep Mode Clock Gating Control
address_offset : 0x828 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCUSB_D0 : USB Module Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Ethernet PHY Deep-Sleep Mode Clock Gating Control
address_offset : 0x830 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCEPHY_D0 : PHY Module Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Ethernet PHY Deep-Sleep Mode Clock Gating Control
address_offset : 0x830 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCEPHY_D0 : PHY Module Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Controller Area Network Deep-Sleep Mode Clock Gating Control
address_offset : 0x834 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCCAN_D0 : CAN Module 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGCCAN_D1 : CAN Module 1 Deep-Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
Controller Area Network Deep-Sleep Mode Clock Gating Control
address_offset : 0x834 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCCAN_D0 : CAN Module 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGCCAN_D1 : CAN Module 1 Deep-Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control
address_offset : 0x838 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCADC_D0 : ADC Module 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGCADC_D1 : ADC Module 1 Deep-Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control
address_offset : 0x838 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCADC_D0 : ADC Module 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
SYSCTL_DCGCADC_D1 : ADC Module 1 Deep-Sleep Mode Clock Gating Control
bits : 1 - 2 (2 bit)
Analog Comparator Deep-Sleep Mode Clock Gating Control
address_offset : 0x83C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCACMP_D0 : Analog Comparator Module 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Analog Comparator Deep-Sleep Mode Clock Gating Control
address_offset : 0x83C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCACMP_D0 : Analog Comparator Module 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Pulse Width Modulator Deep-Sleep Mode Clock Gating Control
address_offset : 0x840 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCPWM_D0 : PWM Module 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Pulse Width Modulator Deep-Sleep Mode Clock Gating Control
address_offset : 0x840 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCPWM_D0 : PWM Module 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control
address_offset : 0x844 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCQEI_D0 : QEI Module 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control
address_offset : 0x844 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCQEI_D0 : QEI Module 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
EEPROM Deep-Sleep Mode Clock Gating Control
address_offset : 0x858 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCEEPROM_D0 : EEPROM Module Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
EEPROM Deep-Sleep Mode Clock Gating Control
address_offset : 0x858 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCEEPROM_D0 : EEPROM Module Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating Control
address_offset : 0x874 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCCCM_D0 : CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating Control
address_offset : 0x874 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCCCM_D0 : CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Ethernet MAC Deep-Sleep Mode Clock Gating Control
address_offset : 0x89C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCEMAC_D0 : Ethernet MAC Module 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Ethernet MAC Deep-Sleep Mode Clock Gating Control
address_offset : 0x89C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_DCGCEMAC_D0 : Ethernet MAC Module 0 Deep-Sleep Mode Clock Gating Control
bits : 0 - 0 (1 bit)
Watchdog Timer Power Control
address_offset : 0x900 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCWD_P0 : Watchdog Timer 0 Power Control
bits : 0 - 0 (1 bit)
SYSCTL_PCWD_P1 : Watchdog Timer 1 Power Control
bits : 1 - 2 (2 bit)
Watchdog Timer Power Control
address_offset : 0x900 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCWD_P0 : Watchdog Timer 0 Power Control
bits : 0 - 0 (1 bit)
SYSCTL_PCWD_P1 : Watchdog Timer 1 Power Control
bits : 1 - 2 (2 bit)
16/32-Bit General-Purpose Timer Power Control
address_offset : 0x904 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCTIMER_P0 : General-Purpose Timer 0 Power Control
bits : 0 - 0 (1 bit)
SYSCTL_PCTIMER_P1 : General-Purpose Timer 1 Power Control
bits : 1 - 2 (2 bit)
SYSCTL_PCTIMER_P2 : General-Purpose Timer 2 Power Control
bits : 2 - 4 (3 bit)
SYSCTL_PCTIMER_P3 : General-Purpose Timer 3 Power Control
bits : 3 - 6 (4 bit)
SYSCTL_PCTIMER_P4 : General-Purpose Timer 4 Power Control
bits : 4 - 8 (5 bit)
SYSCTL_PCTIMER_P5 : General-Purpose Timer 5 Power Control
bits : 5 - 10 (6 bit)
SYSCTL_PCTIMER_P6 : General-Purpose Timer 6 Power Control
bits : 6 - 12 (7 bit)
SYSCTL_PCTIMER_P7 : General-Purpose Timer 7 Power Control
bits : 7 - 14 (8 bit)
16/32-Bit General-Purpose Timer Power Control
address_offset : 0x904 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCTIMER_P0 : General-Purpose Timer 0 Power Control
bits : 0 - 0 (1 bit)
SYSCTL_PCTIMER_P1 : General-Purpose Timer 1 Power Control
bits : 1 - 2 (2 bit)
SYSCTL_PCTIMER_P2 : General-Purpose Timer 2 Power Control
bits : 2 - 4 (3 bit)
SYSCTL_PCTIMER_P3 : General-Purpose Timer 3 Power Control
bits : 3 - 6 (4 bit)
SYSCTL_PCTIMER_P4 : General-Purpose Timer 4 Power Control
bits : 4 - 8 (5 bit)
SYSCTL_PCTIMER_P5 : General-Purpose Timer 5 Power Control
bits : 5 - 10 (6 bit)
SYSCTL_PCTIMER_P6 : General-Purpose Timer 6 Power Control
bits : 6 - 12 (7 bit)
SYSCTL_PCTIMER_P7 : General-Purpose Timer 7 Power Control
bits : 7 - 14 (8 bit)
General-Purpose Input/Output Power Control
address_offset : 0x908 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCGPIO_P0 : GPIO Port A Power Control
bits : 0 - 0 (1 bit)
SYSCTL_PCGPIO_P1 : GPIO Port B Power Control
bits : 1 - 2 (2 bit)
SYSCTL_PCGPIO_P2 : GPIO Port C Power Control
bits : 2 - 4 (3 bit)
SYSCTL_PCGPIO_P3 : GPIO Port D Power Control
bits : 3 - 6 (4 bit)
SYSCTL_PCGPIO_P4 : GPIO Port E Power Control
bits : 4 - 8 (5 bit)
SYSCTL_PCGPIO_P5 : GPIO Port F Power Control
bits : 5 - 10 (6 bit)
SYSCTL_PCGPIO_P6 : GPIO Port G Power Control
bits : 6 - 12 (7 bit)
SYSCTL_PCGPIO_P7 : GPIO Port H Power Control
bits : 7 - 14 (8 bit)
SYSCTL_PCGPIO_P8 : GPIO Port J Power Control
bits : 8 - 16 (9 bit)
SYSCTL_PCGPIO_P9 : GPIO Port K Power Control
bits : 9 - 18 (10 bit)
SYSCTL_PCGPIO_P10 : GPIO Port L Power Control
bits : 10 - 20 (11 bit)
SYSCTL_PCGPIO_P11 : GPIO Port M Power Control
bits : 11 - 22 (12 bit)
SYSCTL_PCGPIO_P12 : GPIO Port N Power Control
bits : 12 - 24 (13 bit)
SYSCTL_PCGPIO_P13 : GPIO Port P Power Control
bits : 13 - 26 (14 bit)
SYSCTL_PCGPIO_P14 : GPIO Port Q Power Control
bits : 14 - 28 (15 bit)
General-Purpose Input/Output Power Control
address_offset : 0x908 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCGPIO_P0 : GPIO Port A Power Control
bits : 0 - 0 (1 bit)
SYSCTL_PCGPIO_P1 : GPIO Port B Power Control
bits : 1 - 2 (2 bit)
SYSCTL_PCGPIO_P2 : GPIO Port C Power Control
bits : 2 - 4 (3 bit)
SYSCTL_PCGPIO_P3 : GPIO Port D Power Control
bits : 3 - 6 (4 bit)
SYSCTL_PCGPIO_P4 : GPIO Port E Power Control
bits : 4 - 8 (5 bit)
SYSCTL_PCGPIO_P5 : GPIO Port F Power Control
bits : 5 - 10 (6 bit)
SYSCTL_PCGPIO_P6 : GPIO Port G Power Control
bits : 6 - 12 (7 bit)
SYSCTL_PCGPIO_P7 : GPIO Port H Power Control
bits : 7 - 14 (8 bit)
SYSCTL_PCGPIO_P8 : GPIO Port J Power Control
bits : 8 - 16 (9 bit)
SYSCTL_PCGPIO_P9 : GPIO Port K Power Control
bits : 9 - 18 (10 bit)
SYSCTL_PCGPIO_P10 : GPIO Port L Power Control
bits : 10 - 20 (11 bit)
SYSCTL_PCGPIO_P11 : GPIO Port M Power Control
bits : 11 - 22 (12 bit)
SYSCTL_PCGPIO_P12 : GPIO Port N Power Control
bits : 12 - 24 (13 bit)
SYSCTL_PCGPIO_P13 : GPIO Port P Power Control
bits : 13 - 26 (14 bit)
SYSCTL_PCGPIO_P14 : GPIO Port Q Power Control
bits : 14 - 28 (15 bit)
Micro Direct Memory Access Power Control
address_offset : 0x90C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCDMA_P0 : uDMA Module Power Control
bits : 0 - 0 (1 bit)
Micro Direct Memory Access Power Control
address_offset : 0x90C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCDMA_P0 : uDMA Module Power Control
bits : 0 - 0 (1 bit)
External Peripheral Interface Power Control
address_offset : 0x910 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCEPI_P0 : EPI Module Power Control
bits : 0 - 0 (1 bit)
External Peripheral Interface Power Control
address_offset : 0x910 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCEPI_P0 : EPI Module Power Control
bits : 0 - 0 (1 bit)
Hibernation Power Control
address_offset : 0x914 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCHIB_P0 : Hibernation Module Power Control
bits : 0 - 0 (1 bit)
Hibernation Power Control
address_offset : 0x914 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCHIB_P0 : Hibernation Module Power Control
bits : 0 - 0 (1 bit)
Universal Asynchronous Receiver/Transmitter Power Control
address_offset : 0x918 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCUART_P0 : UART Module 0 Power Control
bits : 0 - 0 (1 bit)
SYSCTL_PCUART_P1 : UART Module 1 Power Control
bits : 1 - 2 (2 bit)
SYSCTL_PCUART_P2 : UART Module 2 Power Control
bits : 2 - 4 (3 bit)
SYSCTL_PCUART_P3 : UART Module 3 Power Control
bits : 3 - 6 (4 bit)
SYSCTL_PCUART_P4 : UART Module 4 Power Control
bits : 4 - 8 (5 bit)
SYSCTL_PCUART_P5 : UART Module 5 Power Control
bits : 5 - 10 (6 bit)
SYSCTL_PCUART_P6 : UART Module 6 Power Control
bits : 6 - 12 (7 bit)
SYSCTL_PCUART_P7 : UART Module 7 Power Control
bits : 7 - 14 (8 bit)
Universal Asynchronous Receiver/Transmitter Power Control
address_offset : 0x918 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCUART_P0 : UART Module 0 Power Control
bits : 0 - 0 (1 bit)
SYSCTL_PCUART_P1 : UART Module 1 Power Control
bits : 1 - 2 (2 bit)
SYSCTL_PCUART_P2 : UART Module 2 Power Control
bits : 2 - 4 (3 bit)
SYSCTL_PCUART_P3 : UART Module 3 Power Control
bits : 3 - 6 (4 bit)
SYSCTL_PCUART_P4 : UART Module 4 Power Control
bits : 4 - 8 (5 bit)
SYSCTL_PCUART_P5 : UART Module 5 Power Control
bits : 5 - 10 (6 bit)
SYSCTL_PCUART_P6 : UART Module 6 Power Control
bits : 6 - 12 (7 bit)
SYSCTL_PCUART_P7 : UART Module 7 Power Control
bits : 7 - 14 (8 bit)
Synchronous Serial Interface Power Control
address_offset : 0x91C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCSSI_P0 : SSI Module 0 Power Control
bits : 0 - 0 (1 bit)
SYSCTL_PCSSI_P1 : SSI Module 1 Power Control
bits : 1 - 2 (2 bit)
SYSCTL_PCSSI_P2 : SSI Module 2 Power Control
bits : 2 - 4 (3 bit)
SYSCTL_PCSSI_P3 : SSI Module 3 Power Control
bits : 3 - 6 (4 bit)
Synchronous Serial Interface Power Control
address_offset : 0x91C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCSSI_P0 : SSI Module 0 Power Control
bits : 0 - 0 (1 bit)
SYSCTL_PCSSI_P1 : SSI Module 1 Power Control
bits : 1 - 2 (2 bit)
SYSCTL_PCSSI_P2 : SSI Module 2 Power Control
bits : 2 - 4 (3 bit)
SYSCTL_PCSSI_P3 : SSI Module 3 Power Control
bits : 3 - 6 (4 bit)
Inter-Integrated Circuit Power Control
address_offset : 0x920 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCI2C_P0 : I2C Module 0 Power Control
bits : 0 - 0 (1 bit)
SYSCTL_PCI2C_P1 : I2C Module 1 Power Control
bits : 1 - 2 (2 bit)
SYSCTL_PCI2C_P2 : I2C Module 2 Power Control
bits : 2 - 4 (3 bit)
SYSCTL_PCI2C_P3 : I2C Module 3 Power Control
bits : 3 - 6 (4 bit)
SYSCTL_PCI2C_P4 : I2C Module 4 Power Control
bits : 4 - 8 (5 bit)
SYSCTL_PCI2C_P5 : I2C Module 5 Power Control
bits : 5 - 10 (6 bit)
SYSCTL_PCI2C_P6 : I2C Module 6 Power Control
bits : 6 - 12 (7 bit)
SYSCTL_PCI2C_P7 : I2C Module 7 Power Control
bits : 7 - 14 (8 bit)
SYSCTL_PCI2C_P8 : I2C Module 8 Power Control
bits : 8 - 16 (9 bit)
SYSCTL_PCI2C_P9 : I2C Module 9 Power Control
bits : 9 - 18 (10 bit)
Inter-Integrated Circuit Power Control
address_offset : 0x920 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCI2C_P0 : I2C Module 0 Power Control
bits : 0 - 0 (1 bit)
SYSCTL_PCI2C_P1 : I2C Module 1 Power Control
bits : 1 - 2 (2 bit)
SYSCTL_PCI2C_P2 : I2C Module 2 Power Control
bits : 2 - 4 (3 bit)
SYSCTL_PCI2C_P3 : I2C Module 3 Power Control
bits : 3 - 6 (4 bit)
SYSCTL_PCI2C_P4 : I2C Module 4 Power Control
bits : 4 - 8 (5 bit)
SYSCTL_PCI2C_P5 : I2C Module 5 Power Control
bits : 5 - 10 (6 bit)
SYSCTL_PCI2C_P6 : I2C Module 6 Power Control
bits : 6 - 12 (7 bit)
SYSCTL_PCI2C_P7 : I2C Module 7 Power Control
bits : 7 - 14 (8 bit)
SYSCTL_PCI2C_P8 : I2C Module 8 Power Control
bits : 8 - 16 (9 bit)
SYSCTL_PCI2C_P9 : I2C Module 9 Power Control
bits : 9 - 18 (10 bit)
Universal Serial Bus Power Control
address_offset : 0x928 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCUSB_P0 : USB Module Power Control
bits : 0 - 0 (1 bit)
Universal Serial Bus Power Control
address_offset : 0x928 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCUSB_P0 : USB Module Power Control
bits : 0 - 0 (1 bit)
Ethernet PHY Power Control
address_offset : 0x930 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCEPHY_P0 : Ethernet PHY Module Power Control
bits : 0 - 0 (1 bit)
Ethernet PHY Power Control
address_offset : 0x930 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCEPHY_P0 : Ethernet PHY Module Power Control
bits : 0 - 0 (1 bit)
Controller Area Network Power Control
address_offset : 0x934 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCCAN_P0 : CAN Module 0 Power Control
bits : 0 - 0 (1 bit)
SYSCTL_PCCAN_P1 : CAN Module 1 Power Control
bits : 1 - 2 (2 bit)
Controller Area Network Power Control
address_offset : 0x934 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCCAN_P0 : CAN Module 0 Power Control
bits : 0 - 0 (1 bit)
SYSCTL_PCCAN_P1 : CAN Module 1 Power Control
bits : 1 - 2 (2 bit)
Analog-to-Digital Converter Power Control
address_offset : 0x938 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCADC_P0 : ADC Module 0 Power Control
bits : 0 - 0 (1 bit)
SYSCTL_PCADC_P1 : ADC Module 1 Power Control
bits : 1 - 2 (2 bit)
Analog-to-Digital Converter Power Control
address_offset : 0x938 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCADC_P0 : ADC Module 0 Power Control
bits : 0 - 0 (1 bit)
SYSCTL_PCADC_P1 : ADC Module 1 Power Control
bits : 1 - 2 (2 bit)
Analog Comparator Power Control
address_offset : 0x93C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCACMP_P0 : Analog Comparator Module 0 Power Control
bits : 0 - 0 (1 bit)
Analog Comparator Power Control
address_offset : 0x93C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCACMP_P0 : Analog Comparator Module 0 Power Control
bits : 0 - 0 (1 bit)
Pulse Width Modulator Power Control
address_offset : 0x940 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCPWM_P0 : PWM Module 0 Power Control
bits : 0 - 0 (1 bit)
Pulse Width Modulator Power Control
address_offset : 0x940 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCPWM_P0 : PWM Module 0 Power Control
bits : 0 - 0 (1 bit)
Quadrature Encoder Interface Power Control
address_offset : 0x944 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCQEI_P0 : QEI Module 0 Power Control
bits : 0 - 0 (1 bit)
Quadrature Encoder Interface Power Control
address_offset : 0x944 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCQEI_P0 : QEI Module 0 Power Control
bits : 0 - 0 (1 bit)
EEPROM Power Control
address_offset : 0x958 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCEEPROM_P0 : EEPROM Module 0 Power Control
bits : 0 - 0 (1 bit)
EEPROM Power Control
address_offset : 0x958 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCEEPROM_P0 : EEPROM Module 0 Power Control
bits : 0 - 0 (1 bit)
CRC and Cryptographic Modules Power Control
address_offset : 0x974 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCCCM_P0 : CRC and Cryptographic Modules Power Control
bits : 0 - 0 (1 bit)
CRC and Cryptographic Modules Power Control
address_offset : 0x974 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCCCM_P0 : CRC and Cryptographic Modules Power Control
bits : 0 - 0 (1 bit)
Ethernet MAC Power Control
address_offset : 0x99C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCEMAC_P0 : Ethernet MAC Module 0 Power Control
bits : 0 - 0 (1 bit)
Ethernet MAC Power Control
address_offset : 0x99C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PCEMAC_P0 : Ethernet MAC Module 0 Power Control
bits : 0 - 0 (1 bit)
Watchdog Timer Peripheral Ready
address_offset : 0xA00 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRWD_R0 : Watchdog Timer 0 Peripheral Ready
bits : 0 - 0 (1 bit)
SYSCTL_PRWD_R1 : Watchdog Timer 1 Peripheral Ready
bits : 1 - 2 (2 bit)
Watchdog Timer Peripheral Ready
address_offset : 0xA00 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRWD_R0 : Watchdog Timer 0 Peripheral Ready
bits : 0 - 0 (1 bit)
SYSCTL_PRWD_R1 : Watchdog Timer 1 Peripheral Ready
bits : 1 - 2 (2 bit)
16/32-Bit General-Purpose Timer Peripheral Ready
address_offset : 0xA04 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRTIMER_R0 : 16/32-Bit General-Purpose Timer 0 Peripheral Ready
bits : 0 - 0 (1 bit)
SYSCTL_PRTIMER_R1 : 16/32-Bit General-Purpose Timer 1 Peripheral Ready
bits : 1 - 2 (2 bit)
SYSCTL_PRTIMER_R2 : 16/32-Bit General-Purpose Timer 2 Peripheral Ready
bits : 2 - 4 (3 bit)
SYSCTL_PRTIMER_R3 : 16/32-Bit General-Purpose Timer 3 Peripheral Ready
bits : 3 - 6 (4 bit)
SYSCTL_PRTIMER_R4 : 16/32-Bit General-Purpose Timer 4 Peripheral Ready
bits : 4 - 8 (5 bit)
SYSCTL_PRTIMER_R5 : 16/32-Bit General-Purpose Timer 5 Peripheral Ready
bits : 5 - 10 (6 bit)
SYSCTL_PRTIMER_R6 : 16/32-Bit General-Purpose Timer 6 Peripheral Ready
bits : 6 - 12 (7 bit)
SYSCTL_PRTIMER_R7 : 16/32-Bit General-Purpose Timer 7 Peripheral Ready
bits : 7 - 14 (8 bit)
16/32-Bit General-Purpose Timer Peripheral Ready
address_offset : 0xA04 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRTIMER_R0 : 16/32-Bit General-Purpose Timer 0 Peripheral Ready
bits : 0 - 0 (1 bit)
SYSCTL_PRTIMER_R1 : 16/32-Bit General-Purpose Timer 1 Peripheral Ready
bits : 1 - 2 (2 bit)
SYSCTL_PRTIMER_R2 : 16/32-Bit General-Purpose Timer 2 Peripheral Ready
bits : 2 - 4 (3 bit)
SYSCTL_PRTIMER_R3 : 16/32-Bit General-Purpose Timer 3 Peripheral Ready
bits : 3 - 6 (4 bit)
SYSCTL_PRTIMER_R4 : 16/32-Bit General-Purpose Timer 4 Peripheral Ready
bits : 4 - 8 (5 bit)
SYSCTL_PRTIMER_R5 : 16/32-Bit General-Purpose Timer 5 Peripheral Ready
bits : 5 - 10 (6 bit)
SYSCTL_PRTIMER_R6 : 16/32-Bit General-Purpose Timer 6 Peripheral Ready
bits : 6 - 12 (7 bit)
SYSCTL_PRTIMER_R7 : 16/32-Bit General-Purpose Timer 7 Peripheral Ready
bits : 7 - 14 (8 bit)
General-Purpose Input/Output Peripheral Ready
address_offset : 0xA08 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRGPIO_R0 : GPIO Port A Peripheral Ready
bits : 0 - 0 (1 bit)
SYSCTL_PRGPIO_R1 : GPIO Port B Peripheral Ready
bits : 1 - 2 (2 bit)
SYSCTL_PRGPIO_R2 : GPIO Port C Peripheral Ready
bits : 2 - 4 (3 bit)
SYSCTL_PRGPIO_R3 : GPIO Port D Peripheral Ready
bits : 3 - 6 (4 bit)
SYSCTL_PRGPIO_R4 : GPIO Port E Peripheral Ready
bits : 4 - 8 (5 bit)
SYSCTL_PRGPIO_R5 : GPIO Port F Peripheral Ready
bits : 5 - 10 (6 bit)
SYSCTL_PRGPIO_R6 : GPIO Port G Peripheral Ready
bits : 6 - 12 (7 bit)
SYSCTL_PRGPIO_R7 : GPIO Port H Peripheral Ready
bits : 7 - 14 (8 bit)
SYSCTL_PRGPIO_R8 : GPIO Port J Peripheral Ready
bits : 8 - 16 (9 bit)
SYSCTL_PRGPIO_R9 : GPIO Port K Peripheral Ready
bits : 9 - 18 (10 bit)
SYSCTL_PRGPIO_R10 : GPIO Port L Peripheral Ready
bits : 10 - 20 (11 bit)
SYSCTL_PRGPIO_R11 : GPIO Port M Peripheral Ready
bits : 11 - 22 (12 bit)
SYSCTL_PRGPIO_R12 : GPIO Port N Peripheral Ready
bits : 12 - 24 (13 bit)
SYSCTL_PRGPIO_R13 : GPIO Port P Peripheral Ready
bits : 13 - 26 (14 bit)
SYSCTL_PRGPIO_R14 : GPIO Port Q Peripheral Ready
bits : 14 - 28 (15 bit)
General-Purpose Input/Output Peripheral Ready
address_offset : 0xA08 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRGPIO_R0 : GPIO Port A Peripheral Ready
bits : 0 - 0 (1 bit)
SYSCTL_PRGPIO_R1 : GPIO Port B Peripheral Ready
bits : 1 - 2 (2 bit)
SYSCTL_PRGPIO_R2 : GPIO Port C Peripheral Ready
bits : 2 - 4 (3 bit)
SYSCTL_PRGPIO_R3 : GPIO Port D Peripheral Ready
bits : 3 - 6 (4 bit)
SYSCTL_PRGPIO_R4 : GPIO Port E Peripheral Ready
bits : 4 - 8 (5 bit)
SYSCTL_PRGPIO_R5 : GPIO Port F Peripheral Ready
bits : 5 - 10 (6 bit)
SYSCTL_PRGPIO_R6 : GPIO Port G Peripheral Ready
bits : 6 - 12 (7 bit)
SYSCTL_PRGPIO_R7 : GPIO Port H Peripheral Ready
bits : 7 - 14 (8 bit)
SYSCTL_PRGPIO_R8 : GPIO Port J Peripheral Ready
bits : 8 - 16 (9 bit)
SYSCTL_PRGPIO_R9 : GPIO Port K Peripheral Ready
bits : 9 - 18 (10 bit)
SYSCTL_PRGPIO_R10 : GPIO Port L Peripheral Ready
bits : 10 - 20 (11 bit)
SYSCTL_PRGPIO_R11 : GPIO Port M Peripheral Ready
bits : 11 - 22 (12 bit)
SYSCTL_PRGPIO_R12 : GPIO Port N Peripheral Ready
bits : 12 - 24 (13 bit)
SYSCTL_PRGPIO_R13 : GPIO Port P Peripheral Ready
bits : 13 - 26 (14 bit)
SYSCTL_PRGPIO_R14 : GPIO Port Q Peripheral Ready
bits : 14 - 28 (15 bit)
Micro Direct Memory Access Peripheral Ready
address_offset : 0xA0C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRDMA_R0 : uDMA Module Peripheral Ready
bits : 0 - 0 (1 bit)
Micro Direct Memory Access Peripheral Ready
address_offset : 0xA0C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRDMA_R0 : uDMA Module Peripheral Ready
bits : 0 - 0 (1 bit)
EPI Peripheral Ready
address_offset : 0xA10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PREPI_R0 : EPI Module Peripheral Ready
bits : 0 - 0 (1 bit)
EPI Peripheral Ready
address_offset : 0xA10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PREPI_R0 : EPI Module Peripheral Ready
bits : 0 - 0 (1 bit)
Hibernation Peripheral Ready
address_offset : 0xA14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRHIB_R0 : Hibernation Module Peripheral Ready
bits : 0 - 0 (1 bit)
Hibernation Peripheral Ready
address_offset : 0xA14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRHIB_R0 : Hibernation Module Peripheral Ready
bits : 0 - 0 (1 bit)
Universal Asynchronous Receiver/Transmitter Peripheral Ready
address_offset : 0xA18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRUART_R0 : UART Module 0 Peripheral Ready
bits : 0 - 0 (1 bit)
SYSCTL_PRUART_R1 : UART Module 1 Peripheral Ready
bits : 1 - 2 (2 bit)
SYSCTL_PRUART_R2 : UART Module 2 Peripheral Ready
bits : 2 - 4 (3 bit)
SYSCTL_PRUART_R3 : UART Module 3 Peripheral Ready
bits : 3 - 6 (4 bit)
SYSCTL_PRUART_R4 : UART Module 4 Peripheral Ready
bits : 4 - 8 (5 bit)
SYSCTL_PRUART_R5 : UART Module 5 Peripheral Ready
bits : 5 - 10 (6 bit)
SYSCTL_PRUART_R6 : UART Module 6 Peripheral Ready
bits : 6 - 12 (7 bit)
SYSCTL_PRUART_R7 : UART Module 7 Peripheral Ready
bits : 7 - 14 (8 bit)
Universal Asynchronous Receiver/Transmitter Peripheral Ready
address_offset : 0xA18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRUART_R0 : UART Module 0 Peripheral Ready
bits : 0 - 0 (1 bit)
SYSCTL_PRUART_R1 : UART Module 1 Peripheral Ready
bits : 1 - 2 (2 bit)
SYSCTL_PRUART_R2 : UART Module 2 Peripheral Ready
bits : 2 - 4 (3 bit)
SYSCTL_PRUART_R3 : UART Module 3 Peripheral Ready
bits : 3 - 6 (4 bit)
SYSCTL_PRUART_R4 : UART Module 4 Peripheral Ready
bits : 4 - 8 (5 bit)
SYSCTL_PRUART_R5 : UART Module 5 Peripheral Ready
bits : 5 - 10 (6 bit)
SYSCTL_PRUART_R6 : UART Module 6 Peripheral Ready
bits : 6 - 12 (7 bit)
SYSCTL_PRUART_R7 : UART Module 7 Peripheral Ready
bits : 7 - 14 (8 bit)
Synchronous Serial Interface Peripheral Ready
address_offset : 0xA1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRSSI_R0 : SSI Module 0 Peripheral Ready
bits : 0 - 0 (1 bit)
SYSCTL_PRSSI_R1 : SSI Module 1 Peripheral Ready
bits : 1 - 2 (2 bit)
SYSCTL_PRSSI_R2 : SSI Module 2 Peripheral Ready
bits : 2 - 4 (3 bit)
SYSCTL_PRSSI_R3 : SSI Module 3 Peripheral Ready
bits : 3 - 6 (4 bit)
Synchronous Serial Interface Peripheral Ready
address_offset : 0xA1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRSSI_R0 : SSI Module 0 Peripheral Ready
bits : 0 - 0 (1 bit)
SYSCTL_PRSSI_R1 : SSI Module 1 Peripheral Ready
bits : 1 - 2 (2 bit)
SYSCTL_PRSSI_R2 : SSI Module 2 Peripheral Ready
bits : 2 - 4 (3 bit)
SYSCTL_PRSSI_R3 : SSI Module 3 Peripheral Ready
bits : 3 - 6 (4 bit)
Inter-Integrated Circuit Peripheral Ready
address_offset : 0xA20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRI2C_R0 : I2C Module 0 Peripheral Ready
bits : 0 - 0 (1 bit)
SYSCTL_PRI2C_R1 : I2C Module 1 Peripheral Ready
bits : 1 - 2 (2 bit)
SYSCTL_PRI2C_R2 : I2C Module 2 Peripheral Ready
bits : 2 - 4 (3 bit)
SYSCTL_PRI2C_R3 : I2C Module 3 Peripheral Ready
bits : 3 - 6 (4 bit)
SYSCTL_PRI2C_R4 : I2C Module 4 Peripheral Ready
bits : 4 - 8 (5 bit)
SYSCTL_PRI2C_R5 : I2C Module 5 Peripheral Ready
bits : 5 - 10 (6 bit)
SYSCTL_PRI2C_R6 : I2C Module 6 Peripheral Ready
bits : 6 - 12 (7 bit)
SYSCTL_PRI2C_R7 : I2C Module 7 Peripheral Ready
bits : 7 - 14 (8 bit)
SYSCTL_PRI2C_R8 : I2C Module 8 Peripheral Ready
bits : 8 - 16 (9 bit)
SYSCTL_PRI2C_R9 : I2C Module 9 Peripheral Ready
bits : 9 - 18 (10 bit)
Inter-Integrated Circuit Peripheral Ready
address_offset : 0xA20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRI2C_R0 : I2C Module 0 Peripheral Ready
bits : 0 - 0 (1 bit)
SYSCTL_PRI2C_R1 : I2C Module 1 Peripheral Ready
bits : 1 - 2 (2 bit)
SYSCTL_PRI2C_R2 : I2C Module 2 Peripheral Ready
bits : 2 - 4 (3 bit)
SYSCTL_PRI2C_R3 : I2C Module 3 Peripheral Ready
bits : 3 - 6 (4 bit)
SYSCTL_PRI2C_R4 : I2C Module 4 Peripheral Ready
bits : 4 - 8 (5 bit)
SYSCTL_PRI2C_R5 : I2C Module 5 Peripheral Ready
bits : 5 - 10 (6 bit)
SYSCTL_PRI2C_R6 : I2C Module 6 Peripheral Ready
bits : 6 - 12 (7 bit)
SYSCTL_PRI2C_R7 : I2C Module 7 Peripheral Ready
bits : 7 - 14 (8 bit)
SYSCTL_PRI2C_R8 : I2C Module 8 Peripheral Ready
bits : 8 - 16 (9 bit)
SYSCTL_PRI2C_R9 : I2C Module 9 Peripheral Ready
bits : 9 - 18 (10 bit)
Universal Serial Bus Peripheral Ready
address_offset : 0xA28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRUSB_R0 : USB Module Peripheral Ready
bits : 0 - 0 (1 bit)
Universal Serial Bus Peripheral Ready
address_offset : 0xA28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRUSB_R0 : USB Module Peripheral Ready
bits : 0 - 0 (1 bit)
Ethernet PHY Peripheral Ready
address_offset : 0xA30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PREPHY_R0 : Ethernet PHY Module Peripheral Ready
bits : 0 - 0 (1 bit)
Ethernet PHY Peripheral Ready
address_offset : 0xA30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PREPHY_R0 : Ethernet PHY Module Peripheral Ready
bits : 0 - 0 (1 bit)
Controller Area Network Peripheral Ready
address_offset : 0xA34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRCAN_R0 : CAN Module 0 Peripheral Ready
bits : 0 - 0 (1 bit)
SYSCTL_PRCAN_R1 : CAN Module 1 Peripheral Ready
bits : 1 - 2 (2 bit)
Controller Area Network Peripheral Ready
address_offset : 0xA34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRCAN_R0 : CAN Module 0 Peripheral Ready
bits : 0 - 0 (1 bit)
SYSCTL_PRCAN_R1 : CAN Module 1 Peripheral Ready
bits : 1 - 2 (2 bit)
Analog-to-Digital Converter Peripheral Ready
address_offset : 0xA38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRADC_R0 : ADC Module 0 Peripheral Ready
bits : 0 - 0 (1 bit)
SYSCTL_PRADC_R1 : ADC Module 1 Peripheral Ready
bits : 1 - 2 (2 bit)
Analog-to-Digital Converter Peripheral Ready
address_offset : 0xA38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRADC_R0 : ADC Module 0 Peripheral Ready
bits : 0 - 0 (1 bit)
SYSCTL_PRADC_R1 : ADC Module 1 Peripheral Ready
bits : 1 - 2 (2 bit)
Analog Comparator Peripheral Ready
address_offset : 0xA3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRACMP_R0 : Analog Comparator Module 0 Peripheral Ready
bits : 0 - 0 (1 bit)
Analog Comparator Peripheral Ready
address_offset : 0xA3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRACMP_R0 : Analog Comparator Module 0 Peripheral Ready
bits : 0 - 0 (1 bit)
Pulse Width Modulator Peripheral Ready
address_offset : 0xA40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRPWM_R0 : PWM Module 0 Peripheral Ready
bits : 0 - 0 (1 bit)
Pulse Width Modulator Peripheral Ready
address_offset : 0xA40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRPWM_R0 : PWM Module 0 Peripheral Ready
bits : 0 - 0 (1 bit)
Quadrature Encoder Interface Peripheral Ready
address_offset : 0xA44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRQEI_R0 : QEI Module 0 Peripheral Ready
bits : 0 - 0 (1 bit)
Quadrature Encoder Interface Peripheral Ready
address_offset : 0xA44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRQEI_R0 : QEI Module 0 Peripheral Ready
bits : 0 - 0 (1 bit)
EEPROM Peripheral Ready
address_offset : 0xA58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PREEPROM_R0 : EEPROM Module Peripheral Ready
bits : 0 - 0 (1 bit)
EEPROM Peripheral Ready
address_offset : 0xA58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PREEPROM_R0 : EEPROM Module Peripheral Ready
bits : 0 - 0 (1 bit)
CRC and Cryptographic Modules Peripheral Ready
address_offset : 0xA74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRCCM_R0 : CRC and Cryptographic Modules Peripheral Ready
bits : 0 - 0 (1 bit)
CRC and Cryptographic Modules Peripheral Ready
address_offset : 0xA74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PRCCM_R0 : CRC and Cryptographic Modules Peripheral Ready
bits : 0 - 0 (1 bit)
Ethernet MAC Peripheral Ready
address_offset : 0xA9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PREMAC_R0 : Ethernet MAC Module 0 Peripheral Ready
bits : 0 - 0 (1 bit)
Ethernet MAC Peripheral Ready
address_offset : 0xA9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_PREMAC_R0 : Ethernet MAC Module 0 Peripheral Ready
bits : 0 - 0 (1 bit)
Run and Sleep Mode Configuration Register
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RSCLKCFG_PSYSDIV : PLL System Clock Divisor
bits : 0 - 9 (10 bit)
SYSCTL_RSCLKCFG_OSYSDIV : Oscillator System Clock Divisor
bits : 10 - 29 (20 bit)
SYSCTL_RSCLKCFG_OSCSRC : Oscillator Source
bits : 20 - 43 (24 bit)
Enumeration:
0x0 : SYSCTL_RSCLKCFG_OSCSRC_PIOSC
PIOSC is oscillator source
0x2 : SYSCTL_RSCLKCFG_OSCSRC_LFIOSC
LFIOSC is oscillator source
0x3 : SYSCTL_RSCLKCFG_OSCSRC_MOSC
MOSC is oscillator source
0x4 : SYSCTL_RSCLKCFG_OSCSRC_RTC
Hibernation Module RTC Oscillator (RTCOSC)
End of enumeration elements list.
SYSCTL_RSCLKCFG_PLLSRC : PLL Source
bits : 24 - 51 (28 bit)
Enumeration:
0x0 : SYSCTL_RSCLKCFG_PLLSRC_PIOSC
PIOSC is PLL input clock source
0x3 : SYSCTL_RSCLKCFG_PLLSRC_MOSC
MOSC is the PLL input clock source
End of enumeration elements list.
SYSCTL_RSCLKCFG_USEPLL : Use PLL
bits : 28 - 56 (29 bit)
SYSCTL_RSCLKCFG_ACG : Auto Clock Gating
bits : 29 - 58 (30 bit)
SYSCTL_RSCLKCFG_NEWFREQ : New PLLFREQ Accept
bits : 30 - 60 (31 bit)
SYSCTL_RSCLKCFG_MEMTIMU : Memory Timing Register Update
bits : 31 - 62 (32 bit)
Run and Sleep Mode Configuration Register
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_RSCLKCFG_PSYSDIV : PLL System Clock Divisor
bits : 0 - 9 (10 bit)
SYSCTL_RSCLKCFG_OSYSDIV : Oscillator System Clock Divisor
bits : 10 - 29 (20 bit)
SYSCTL_RSCLKCFG_OSCSRC : Oscillator Source
bits : 20 - 43 (24 bit)
Enumeration:
0x0 : SYSCTL_RSCLKCFG_OSCSRC_PIOSC
PIOSC is oscillator source
0x2 : SYSCTL_RSCLKCFG_OSCSRC_LFIOSC
LFIOSC is oscillator source
0x3 : SYSCTL_RSCLKCFG_OSCSRC_MOSC
MOSC is oscillator source
0x4 : SYSCTL_RSCLKCFG_OSCSRC_RTC
Hibernation Module RTC Oscillator (RTCOSC)
End of enumeration elements list.
SYSCTL_RSCLKCFG_PLLSRC : PLL Source
bits : 24 - 51 (28 bit)
Enumeration:
0x0 : SYSCTL_RSCLKCFG_PLLSRC_PIOSC
PIOSC is PLL input clock source
0x3 : SYSCTL_RSCLKCFG_PLLSRC_MOSC
MOSC is the PLL input clock source
End of enumeration elements list.
SYSCTL_RSCLKCFG_USEPLL : Use PLL
bits : 28 - 56 (29 bit)
SYSCTL_RSCLKCFG_ACG : Auto Clock Gating
bits : 29 - 58 (30 bit)
SYSCTL_RSCLKCFG_NEWFREQ : New PLLFREQ Accept
bits : 30 - 60 (31 bit)
SYSCTL_RSCLKCFG_MEMTIMU : Memory Timing Register Update
bits : 31 - 62 (32 bit)
Memory Timing Parameter Register 0 for Main Flash and EEPROM
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_MEMTIM0_FWS : Flash Wait State
bits : 0 - 3 (4 bit)
SYSCTL_MEMTIM0_FBCE : Flash Bank Clock Edge
bits : 5 - 10 (6 bit)
SYSCTL_MEMTIM0_FBCHT : Flash Bank Clock High Time
bits : 6 - 15 (10 bit)
Enumeration:
0x0 : SYSCTL_MEMTIM0_FBCHT_0_5
1/2 system clock period
0x1 : SYSCTL_MEMTIM0_FBCHT_1
1 system clock period
0x2 : SYSCTL_MEMTIM0_FBCHT_1_5
1.5 system clock periods
0x3 : SYSCTL_MEMTIM0_FBCHT_2
2 system clock periods
0x4 : SYSCTL_MEMTIM0_FBCHT_2_5
2.5 system clock periods
0x5 : SYSCTL_MEMTIM0_FBCHT_3
3 system clock periods
0x6 : SYSCTL_MEMTIM0_FBCHT_3_5
3.5 system clock periods
0x7 : SYSCTL_MEMTIM0_FBCHT_4
4 system clock periods
0x8 : SYSCTL_MEMTIM0_FBCHT_4_5
4.5 system clock periods
End of enumeration elements list.
SYSCTL_MEMTIM0_EWS : EEPROM Wait States
bits : 16 - 35 (20 bit)
SYSCTL_MEMTIM0_EBCE : EEPROM Bank Clock Edge
bits : 21 - 42 (22 bit)
SYSCTL_MEMTIM0_EBCHT : EEPROM Clock High Time
bits : 22 - 47 (26 bit)
Enumeration:
0x0 : SYSCTL_MEMTIM0_EBCHT_0_5
1/2 system clock period
0x1 : SYSCTL_MEMTIM0_EBCHT_1
1 system clock period
0x2 : SYSCTL_MEMTIM0_EBCHT_1_5
1.5 system clock periods
0x3 : SYSCTL_MEMTIM0_EBCHT_2
2 system clock periods
0x4 : SYSCTL_MEMTIM0_EBCHT_2_5
2.5 system clock periods
0x5 : SYSCTL_MEMTIM0_EBCHT_3
3 system clock periods
0x6 : SYSCTL_MEMTIM0_EBCHT_3_5
3.5 system clock periods
0x7 : SYSCTL_MEMTIM0_EBCHT_4
4 system clock periods
0x8 : SYSCTL_MEMTIM0_EBCHT_4_5
4.5 system clock periods
End of enumeration elements list.
Memory Timing Parameter Register 0 for Main Flash and EEPROM
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCTL_MEMTIM0_FWS : Flash Wait State
bits : 0 - 3 (4 bit)
SYSCTL_MEMTIM0_FBCE : Flash Bank Clock Edge
bits : 5 - 10 (6 bit)
SYSCTL_MEMTIM0_FBCHT : Flash Bank Clock High Time
bits : 6 - 15 (10 bit)
Enumeration:
0x0 : SYSCTL_MEMTIM0_FBCHT_0_5
1/2 system clock period
0x1 : SYSCTL_MEMTIM0_FBCHT_1
1 system clock period
0x2 : SYSCTL_MEMTIM0_FBCHT_1_5
1.5 system clock periods
0x3 : SYSCTL_MEMTIM0_FBCHT_2
2 system clock periods
0x4 : SYSCTL_MEMTIM0_FBCHT_2_5
2.5 system clock periods
0x5 : SYSCTL_MEMTIM0_FBCHT_3
3 system clock periods
0x6 : SYSCTL_MEMTIM0_FBCHT_3_5
3.5 system clock periods
0x7 : SYSCTL_MEMTIM0_FBCHT_4
4 system clock periods
0x8 : SYSCTL_MEMTIM0_FBCHT_4_5
4.5 system clock periods
End of enumeration elements list.
SYSCTL_MEMTIM0_EWS : EEPROM Wait States
bits : 16 - 35 (20 bit)
SYSCTL_MEMTIM0_EBCE : EEPROM Bank Clock Edge
bits : 21 - 42 (22 bit)
SYSCTL_MEMTIM0_EBCHT : EEPROM Clock High Time
bits : 22 - 47 (26 bit)
Enumeration:
0x0 : SYSCTL_MEMTIM0_EBCHT_0_5
1/2 system clock period
0x1 : SYSCTL_MEMTIM0_EBCHT_1
1 system clock period
0x2 : SYSCTL_MEMTIM0_EBCHT_1_5
1.5 system clock periods
0x3 : SYSCTL_MEMTIM0_EBCHT_2
2 system clock periods
0x4 : SYSCTL_MEMTIM0_EBCHT_2_5
2.5 system clock periods
0x5 : SYSCTL_MEMTIM0_EBCHT_3
3 system clock periods
0x6 : SYSCTL_MEMTIM0_EBCHT_3_5
3.5 system clock periods
0x7 : SYSCTL_MEMTIM0_EBCHT_4
4 system clock periods
0x8 : SYSCTL_MEMTIM0_EBCHT_4_5
4.5 system clock periods
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.