Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
EPI Configuration
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_CFG_MODE : Mode Select
bits : 0 - 3 (4 bit)
Enumeration:
0x0 : EPI_CFG_MODE_NONE
General Purpose
0x1 : EPI_CFG_MODE_SDRAM
SDRAM
0x2 : EPI_CFG_MODE_HB8
8-Bit Host-Bus (HB8)
0x3 : EPI_CFG_MODE_HB16
16-Bit Host-Bus (HB16)
End of enumeration elements list.
EPI_CFG_BLKEN : Block Enable
bits : 4 - 8 (5 bit)
EPI_CFG_INTDIV : Integer Clock Divider Enable
bits : 8 - 16 (9 bit)
EPI Configuration
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_CFG_MODE : Mode Select
bits : 0 - 3 (4 bit)
Enumeration:
0x0 : EPI_CFG_MODE_NONE
General Purpose
0x1 : EPI_CFG_MODE_SDRAM
SDRAM
0x2 : EPI_CFG_MODE_HB8
8-Bit Host-Bus (HB8)
0x3 : EPI_CFG_MODE_HB16
16-Bit Host-Bus (HB16)
End of enumeration elements list.
EPI_CFG_BLKEN : Block Enable
bits : 4 - 8 (5 bit)
EPI_CFG_INTDIV : Integer Clock Divider Enable
bits : 8 - 16 (9 bit)
EPI Host-Bus 16 Configuration
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : EPI_ALT16
reset_Mask : 0x0
EPI_HB16CFG_MODE : Host Bus Sub-Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_HB16CFG_MODE_ADMUX
ADMUX - AD[15:0]
0x1 : EPI_HB16CFG_MODE_ADNMUX
ADNONMUX - D[15:0]
0x2 : EPI_HB16CFG_MODE_SRAM
Continuous Read - D[15:0]
0x3 : EPI_HB16CFG_MODE_XFIFO
XFIFO - D[15:0]
End of enumeration elements list.
EPI_HB16CFG_BSEL : Byte Select Configuration
bits : 2 - 4 (3 bit)
EPI_HB16CFG_RDWS : Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB16CFG_RDWS_2
Active RDn is 2 EPI clocks
0x1 : EPI_HB16CFG_RDWS_4
Active RDn is 4 EPI clocks
0x2 : EPI_HB16CFG_RDWS_6
Active RDn is 6 EPI clocks
0x3 : EPI_HB16CFG_RDWS_8
Active RDn is 8 EPI clocks
End of enumeration elements list.
EPI_HB16CFG_WRWS : Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB16CFG_WRWS_2
Active WRn is 2 EPI clocks
0x1 : EPI_HB16CFG_WRWS_4
Active WRn is 4 EPI clocks
0x2 : EPI_HB16CFG_WRWS_6
Active WRn is 6 EPI clocks
0x3 : EPI_HB16CFG_WRWS_8
Active WRn is 8 EPI clocks
End of enumeration elements list.
EPI_HB16CFG_MAXWAIT : Maximum Wait
bits : 8 - 23 (16 bit)
EPI_HB16CFG_BURST : Burst Mode
bits : 16 - 32 (17 bit)
EPI_HB16CFG_RDCRE : PSRAM Configuration Register Read
bits : 17 - 34 (18 bit)
EPI_HB16CFG_WRCRE : PSRAM Configuration Register Write
bits : 18 - 36 (19 bit)
EPI_HB16CFG_ALEHIGH : ALE Strobe Polarity
bits : 19 - 38 (20 bit)
EPI_HB16CFG_RDHIGH : READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB16CFG_WRHIGH : WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI_HB16CFG_XFEEN : External FIFO EMPTY Enable
bits : 22 - 44 (23 bit)
EPI_HB16CFG_XFFEN : External FIFO FULL Enable
bits : 23 - 46 (24 bit)
EPI_HB16CFG_IRDYINV : Input Ready Invert
bits : 27 - 54 (28 bit)
EPI_HB16CFG_RDYEN : Input Ready Enable
bits : 28 - 56 (29 bit)
EPI_HB16CFG_CLKINV : Invert Output Clock Enable
bits : 29 - 58 (30 bit)
EPI_HB16CFG_CLKGATEI : Clock Gated Idle
bits : 30 - 60 (31 bit)
EPI_HB16CFG_CLKGATE : Clock Gated
bits : 31 - 62 (32 bit)
EPI General-Purpose Configuration
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_GPCFG_DSIZE : Size of Data Bus
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_GPCFG_DSIZE_4BIT
8 Bits Wide (EPI0S0 to EPI0S7)
0x1 : EPI_GPCFG_DSIZE_16BIT
16 Bits Wide (EPI0S0 to EPI0S15)
0x2 : EPI_GPCFG_DSIZE_24BIT
24 Bits Wide (EPI0S0 to EPI0S23)
0x3 : EPI_GPCFG_DSIZE_32BIT
32 Bits Wide (EPI0S0 to EPI0S31)
End of enumeration elements list.
EPI_GPCFG_ASIZE : Address Bus Size
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_GPCFG_ASIZE_NONE
No address
0x1 : EPI_GPCFG_ASIZE_4BIT
Up to 4 bits wide
0x2 : EPI_GPCFG_ASIZE_12BIT
Up to 12 bits wide. This size cannot be used with 24-bit data
0x3 : EPI_GPCFG_ASIZE_20BIT
Up to 20 bits wide. This size cannot be used with data sizes other than 8
End of enumeration elements list.
EPI_GPCFG_WR2CYC : 2-Cycle Writes
bits : 19 - 38 (20 bit)
EPI_GPCFG_FRMCNT : Frame Count
bits : 22 - 47 (26 bit)
EPI_GPCFG_FRM50 : 50/50 Frame
bits : 26 - 52 (27 bit)
EPI_GPCFG_CLKGATE : Clock Gated
bits : 30 - 60 (31 bit)
EPI_GPCFG_CLKPIN : Clock Pin
bits : 31 - 62 (32 bit)
EPI SDRAM Configuration
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : EPI_ALTSD
reset_Mask : 0x0
EPI_SDRAMCFG_SIZE : Size of SDRAM
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_SDRAMCFG_SIZE_8MB
64 megabits (8MB)
0x1 : EPI_SDRAMCFG_SIZE_16MB
128 megabits (16MB)
0x2 : EPI_SDRAMCFG_SIZE_32MB
256 megabits (32MB)
0x3 : EPI_SDRAMCFG_SIZE_64MB
512 megabits (64MB)
End of enumeration elements list.
EPI_SDRAMCFG_SLEEP : Sleep Mode
bits : 9 - 18 (10 bit)
EPI_SDRAMCFG_RFSH : Refresh Counter
bits : 16 - 42 (27 bit)
EPI_SDRAMCFG_FREQ : EPI Frequency Range
bits : 30 - 61 (32 bit)
Enumeration:
0x0 : EPI_SDRAMCFG_FREQ_NONE
0 - 15 MHz
0x1 : EPI_SDRAMCFG_FREQ_15MHZ
15 - 30 MHz
0x2 : EPI_SDRAMCFG_FREQ_30MHZ
30 - 50 MHz
End of enumeration elements list.
EPI Host-Bus 8 Configuration
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : EPI_ALT8
reset_Mask : 0x0
EPI_HB8CFG_MODE : Host Bus Sub-Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_HB8CFG_MODE_MUX
ADMUX - AD[7:0]
0x1 : EPI_HB8CFG_MODE_NMUX
ADNONMUX - D[7:0]
0x2 : EPI_HB8CFG_MODE_SRAM
Continuous Read - D[7:0]
0x3 : EPI_HB8CFG_MODE_FIFO
XFIFO - D[7:0]
End of enumeration elements list.
EPI_HB8CFG_RDWS : Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB8CFG_RDWS_2
Active RDn is 2 EPI clocks
0x1 : EPI_HB8CFG_RDWS_4
Active RDn is 4 EPI clocks
0x2 : EPI_HB8CFG_RDWS_6
Active RDn is 6 EPI clocks
0x3 : EPI_HB8CFG_RDWS_8
Active RDn is 8 EPI clocks
End of enumeration elements list.
EPI_HB8CFG_WRWS : Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB8CFG_WRWS_2
Active WRn is 2 EPI clocks
0x1 : EPI_HB8CFG_WRWS_4
Active WRn is 4 EPI clocks
0x2 : EPI_HB8CFG_WRWS_6
Active WRn is 6 EPI clocks
0x3 : EPI_HB8CFG_WRWS_8
Active WRn is 8 EPI clocks
End of enumeration elements list.
EPI_HB8CFG_MAXWAIT : Maximum Wait
bits : 8 - 23 (16 bit)
EPI_HB8CFG_ALEHIGH : ALE Strobe Polarity
bits : 19 - 38 (20 bit)
EPI_HB8CFG_RDHIGH : READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB8CFG_WRHIGH : WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI_HB8CFG_XFEEN : External FIFO EMPTY Enable
bits : 22 - 44 (23 bit)
EPI_HB8CFG_XFFEN : External FIFO FULL Enable
bits : 23 - 46 (24 bit)
EPI_HB8CFG_IRDYINV : Input Ready Invert
bits : 27 - 54 (28 bit)
EPI_HB8CFG_RDYEN : Input Ready Enable
bits : 28 - 56 (29 bit)
EPI_HB8CFG_CLKINV : Invert Output Clock Enable
bits : 29 - 58 (30 bit)
EPI_HB8CFG_CLKGATEI : Clock Gated when Idle
bits : 30 - 60 (31 bit)
EPI_HB8CFG_CLKGATE : Clock Gated
bits : 31 - 62 (32 bit)
EPI Host-Bus 16 Configuration
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB16CFG_MODE : Host Bus Sub-Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_HB16CFG_MODE_ADMUX
ADMUX - AD[15:0]
0x1 : EPI_HB16CFG_MODE_ADNMUX
ADNONMUX - D[15:0]
0x2 : EPI_HB16CFG_MODE_SRAM
Continuous Read - D[15:0]
0x3 : EPI_HB16CFG_MODE_XFIFO
XFIFO - D[15:0]
End of enumeration elements list.
EPI_HB16CFG_BSEL : Byte Select Configuration
bits : 2 - 4 (3 bit)
EPI_HB16CFG_RDWS : Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB16CFG_RDWS_2
Active RDn is 2 EPI clocks
0x1 : EPI_HB16CFG_RDWS_4
Active RDn is 4 EPI clocks
0x2 : EPI_HB16CFG_RDWS_6
Active RDn is 6 EPI clocks
0x3 : EPI_HB16CFG_RDWS_8
Active RDn is 8 EPI clocks
End of enumeration elements list.
EPI_HB16CFG_WRWS : Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB16CFG_WRWS_2
Active WRn is 2 EPI clocks
0x1 : EPI_HB16CFG_WRWS_4
Active WRn is 4 EPI clocks
0x2 : EPI_HB16CFG_WRWS_6
Active WRn is 6 EPI clocks
0x3 : EPI_HB16CFG_WRWS_8
Active WRn is 8 EPI clocks
End of enumeration elements list.
EPI_HB16CFG_MAXWAIT : Maximum Wait
bits : 8 - 23 (16 bit)
EPI_HB16CFG_BURST : Burst Mode
bits : 16 - 32 (17 bit)
EPI_HB16CFG_RDCRE : PSRAM Configuration Register Read
bits : 17 - 34 (18 bit)
EPI_HB16CFG_WRCRE : PSRAM Configuration Register Write
bits : 18 - 36 (19 bit)
EPI_HB16CFG_ALEHIGH : ALE Strobe Polarity
bits : 19 - 38 (20 bit)
EPI_HB16CFG_RDHIGH : READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB16CFG_WRHIGH : WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI_HB16CFG_XFEEN : External FIFO EMPTY Enable
bits : 22 - 44 (23 bit)
EPI_HB16CFG_XFFEN : External FIFO FULL Enable
bits : 23 - 46 (24 bit)
EPI_HB16CFG_IRDYINV : Input Ready Invert
bits : 27 - 54 (28 bit)
EPI_HB16CFG_RDYEN : Input Ready Enable
bits : 28 - 56 (29 bit)
EPI_HB16CFG_CLKINV : Invert Output Clock Enable
bits : 29 - 58 (30 bit)
EPI_HB16CFG_CLKGATEI : Clock Gated Idle
bits : 30 - 60 (31 bit)
EPI_HB16CFG_CLKGATE : Clock Gated
bits : 31 - 62 (32 bit)
EPI General-Purpose Configuration
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_GPCFG_DSIZE : Size of Data Bus
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_GPCFG_DSIZE_4BIT
8 Bits Wide (EPI0S0 to EPI0S7)
0x1 : EPI_GPCFG_DSIZE_16BIT
16 Bits Wide (EPI0S0 to EPI0S15)
0x2 : EPI_GPCFG_DSIZE_24BIT
24 Bits Wide (EPI0S0 to EPI0S23)
0x3 : EPI_GPCFG_DSIZE_32BIT
32 Bits Wide (EPI0S0 to EPI0S31)
End of enumeration elements list.
EPI_GPCFG_ASIZE : Address Bus Size
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_GPCFG_ASIZE_NONE
No address
0x1 : EPI_GPCFG_ASIZE_4BIT
Up to 4 bits wide
0x2 : EPI_GPCFG_ASIZE_12BIT
Up to 12 bits wide. This size cannot be used with 24-bit data
0x3 : EPI_GPCFG_ASIZE_20BIT
Up to 20 bits wide. This size cannot be used with data sizes other than 8
End of enumeration elements list.
EPI_GPCFG_WR2CYC : 2-Cycle Writes
bits : 19 - 38 (20 bit)
EPI_GPCFG_FRMCNT : Frame Count
bits : 22 - 47 (26 bit)
EPI_GPCFG_FRM50 : 50/50 Frame
bits : 26 - 52 (27 bit)
EPI_GPCFG_CLKGATE : Clock Gated
bits : 30 - 60 (31 bit)
EPI_GPCFG_CLKPIN : Clock Pin
bits : 31 - 62 (32 bit)
EPI SDRAM Configuration
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_SDRAMCFG_SIZE : Size of SDRAM
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_SDRAMCFG_SIZE_8MB
64 megabits (8MB)
0x1 : EPI_SDRAMCFG_SIZE_16MB
128 megabits (16MB)
0x2 : EPI_SDRAMCFG_SIZE_32MB
256 megabits (32MB)
0x3 : EPI_SDRAMCFG_SIZE_64MB
512 megabits (64MB)
End of enumeration elements list.
EPI_SDRAMCFG_SLEEP : Sleep Mode
bits : 9 - 18 (10 bit)
EPI_SDRAMCFG_RFSH : Refresh Counter
bits : 16 - 42 (27 bit)
EPI_SDRAMCFG_FREQ : EPI Frequency Range
bits : 30 - 61 (32 bit)
Enumeration:
0x0 : EPI_SDRAMCFG_FREQ_NONE
0 - 15 MHz
0x1 : EPI_SDRAMCFG_FREQ_15MHZ
15 - 30 MHz
0x2 : EPI_SDRAMCFG_FREQ_30MHZ
30 - 50 MHz
End of enumeration elements list.
EPI Host-Bus 8 Configuration
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB8CFG_MODE : Host Bus Sub-Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_HB8CFG_MODE_MUX
ADMUX - AD[7:0]
0x1 : EPI_HB8CFG_MODE_NMUX
ADNONMUX - D[7:0]
0x2 : EPI_HB8CFG_MODE_SRAM
Continuous Read - D[7:0]
0x3 : EPI_HB8CFG_MODE_FIFO
XFIFO - D[7:0]
End of enumeration elements list.
EPI_HB8CFG_RDWS : Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB8CFG_RDWS_2
Active RDn is 2 EPI clocks
0x1 : EPI_HB8CFG_RDWS_4
Active RDn is 4 EPI clocks
0x2 : EPI_HB8CFG_RDWS_6
Active RDn is 6 EPI clocks
0x3 : EPI_HB8CFG_RDWS_8
Active RDn is 8 EPI clocks
End of enumeration elements list.
EPI_HB8CFG_WRWS : Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB8CFG_WRWS_2
Active WRn is 2 EPI clocks
0x1 : EPI_HB8CFG_WRWS_4
Active WRn is 4 EPI clocks
0x2 : EPI_HB8CFG_WRWS_6
Active WRn is 6 EPI clocks
0x3 : EPI_HB8CFG_WRWS_8
Active WRn is 8 EPI clocks
End of enumeration elements list.
EPI_HB8CFG_MAXWAIT : Maximum Wait
bits : 8 - 23 (16 bit)
EPI_HB8CFG_ALEHIGH : ALE Strobe Polarity
bits : 19 - 38 (20 bit)
EPI_HB8CFG_RDHIGH : READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB8CFG_WRHIGH : WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI_HB8CFG_XFEEN : External FIFO EMPTY Enable
bits : 22 - 44 (23 bit)
EPI_HB8CFG_XFFEN : External FIFO FULL Enable
bits : 23 - 46 (24 bit)
EPI_HB8CFG_IRDYINV : Input Ready Invert
bits : 27 - 54 (28 bit)
EPI_HB8CFG_RDYEN : Input Ready Enable
bits : 28 - 56 (29 bit)
EPI_HB8CFG_CLKINV : Invert Output Clock Enable
bits : 29 - 58 (30 bit)
EPI_HB8CFG_CLKGATEI : Clock Gated when Idle
bits : 30 - 60 (31 bit)
EPI_HB8CFG_CLKGATE : Clock Gated
bits : 31 - 62 (32 bit)
EPI Host-Bus 8 Configuration 2
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : EPI_ALT8
reset_Mask : 0x0
EPI_HB8CFG2_MODE : CS1n Host Bus Sub-Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_HB8CFG2_MODE_ADMUX
ADMUX - AD[7:0]
0x1 : EPI_HB8CFG2_MODE_AD
ADNONMUX - D[7:0]
End of enumeration elements list.
EPI_HB8CFG2_RDWS : CS1n Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB8CFG2_RDWS_2
Active RDn is 2 EPI clocks
0x1 : EPI_HB8CFG2_RDWS_4
Active RDn is 4 EPI clocks
0x2 : EPI_HB8CFG2_RDWS_6
Active RDn is 6 EPI clocks
0x3 : EPI_HB8CFG2_RDWS_8
Active RDn is 8 EPI clocks
End of enumeration elements list.
EPI_HB8CFG2_WRWS : CS1n Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB8CFG2_WRWS_2
Active WRn is 2 EPI clocks
0x1 : EPI_HB8CFG2_WRWS_4
Active WRn is 4 EPI clocks
0x2 : EPI_HB8CFG2_WRWS_6
Active WRn is 6 EPI clocks
0x3 : EPI_HB8CFG2_WRWS_8
Active WRn is 8 EPI clocks
End of enumeration elements list.
EPI_HB8CFG2_ALEHIGH : CS1n ALE Strobe Polarity
bits : 19 - 38 (20 bit)
EPI_HB8CFG2_RDHIGH : CS1n READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB8CFG2_WRHIGH : CS1n WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI_HB8CFG2_CSCFG : Chip Select Configuration
bits : 24 - 49 (26 bit)
Enumeration:
0x0 : EPI_HB8CFG2_CSCFG_ALE
ALE Configuration
0x1 : EPI_HB8CFG2_CSCFG_CS
CSn Configuration
0x2 : EPI_HB8CFG2_CSCFG_DCS
Dual CSn Configuration
0x3 : EPI_HB8CFG2_CSCFG_ADCS
ALE with Dual CSn Configuration
End of enumeration elements list.
EPI_HB8CFG2_CSBAUD : Chip Select Baud Rate and Multiple Sub-Mode Configuration enable
bits : 26 - 52 (27 bit)
EPI_HB8CFG2_CSCFGEXT : Chip Select Extended Configuration
bits : 27 - 54 (28 bit)
EPI Host-Bus 16 Configuration 2
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : EPI_ALT16
reset_Mask : 0x0
EPI_HB16CFG2_MODE : CS1n Host Bus Sub-Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_HB16CFG2_MODE_ADMUX
ADMUX - AD[15:0]
0x1 : EPI_HB16CFG2_MODE_AD
ADNONMUX - D[15:0]
End of enumeration elements list.
EPI_HB16CFG2_RDWS : CS1n Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB16CFG2_RDWS_2
Active RDn is 2 EPI clocks
0x1 : EPI_HB16CFG2_RDWS_4
Active RDn is 4 EPI clocks
0x2 : EPI_HB16CFG2_RDWS_6
Active RDn is 6 EPI clocks
0x3 : EPI_HB16CFG2_RDWS_8
Active RDn is 8 EPI clocks
End of enumeration elements list.
EPI_HB16CFG2_WRWS : CS1n Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB16CFG2_WRWS_2
Active WRn is 2 EPI clocks
0x1 : EPI_HB16CFG2_WRWS_4
Active WRn is 4 EPI clocks
0x2 : EPI_HB16CFG2_WRWS_6
Active WRn is 6 EPI clocks
0x3 : EPI_HB16CFG2_WRWS_8
Active WRn is 8 EPI clocks
End of enumeration elements list.
EPI_HB16CFG2_BURST : CS1n Burst Mode
bits : 16 - 32 (17 bit)
EPI_HB16CFG2_RDCRE : CS1n PSRAM Configuration Register Read
bits : 17 - 34 (18 bit)
EPI_HB16CFG2_WRCRE : CS1n PSRAM Configuration Register Write
bits : 18 - 36 (19 bit)
EPI_HB16CFG2_ALEHIGH : CS1n ALE Strobe Polarity
bits : 19 - 38 (20 bit)
EPI_HB16CFG2_RDHIGH : CS1n READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB16CFG2_WRHIGH : CS1n WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI_HB16CFG2_CSCFG : Chip Select Configuration
bits : 24 - 49 (26 bit)
Enumeration:
0x0 : EPI_HB16CFG2_CSCFG_ALE
ALE Configuration
0x1 : EPI_HB16CFG2_CSCFG_CS
CSn Configuration
0x2 : EPI_HB16CFG2_CSCFG_DCS
Dual CSn Configuration
0x3 : EPI_HB16CFG2_CSCFG_ADCS
ALE with Dual CSn Configuration
End of enumeration elements list.
EPI_HB16CFG2_CSBAUD : Chip Select Baud Rate and Multiple Sub-Mode Configuration enable
bits : 26 - 52 (27 bit)
EPI_HB16CFG2_CSCFGEXT : Chip Select Extended Configuration
bits : 27 - 54 (28 bit)
EPI Host-Bus 8 Configuration 2
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB8CFG2_MODE : CS1n Host Bus Sub-Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_HB8CFG2_MODE_ADMUX
ADMUX - AD[7:0]
0x1 : EPI_HB8CFG2_MODE_AD
ADNONMUX - D[7:0]
End of enumeration elements list.
EPI_HB8CFG2_RDWS : CS1n Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB8CFG2_RDWS_2
Active RDn is 2 EPI clocks
0x1 : EPI_HB8CFG2_RDWS_4
Active RDn is 4 EPI clocks
0x2 : EPI_HB8CFG2_RDWS_6
Active RDn is 6 EPI clocks
0x3 : EPI_HB8CFG2_RDWS_8
Active RDn is 8 EPI clocks
End of enumeration elements list.
EPI_HB8CFG2_WRWS : CS1n Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB8CFG2_WRWS_2
Active WRn is 2 EPI clocks
0x1 : EPI_HB8CFG2_WRWS_4
Active WRn is 4 EPI clocks
0x2 : EPI_HB8CFG2_WRWS_6
Active WRn is 6 EPI clocks
0x3 : EPI_HB8CFG2_WRWS_8
Active WRn is 8 EPI clocks
End of enumeration elements list.
EPI_HB8CFG2_ALEHIGH : CS1n ALE Strobe Polarity
bits : 19 - 38 (20 bit)
EPI_HB8CFG2_RDHIGH : CS1n READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB8CFG2_WRHIGH : CS1n WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI_HB8CFG2_CSCFG : Chip Select Configuration
bits : 24 - 49 (26 bit)
Enumeration:
0x0 : EPI_HB8CFG2_CSCFG_ALE
ALE Configuration
0x1 : EPI_HB8CFG2_CSCFG_CS
CSn Configuration
0x2 : EPI_HB8CFG2_CSCFG_DCS
Dual CSn Configuration
0x3 : EPI_HB8CFG2_CSCFG_ADCS
ALE with Dual CSn Configuration
End of enumeration elements list.
EPI_HB8CFG2_CSBAUD : Chip Select Baud Rate and Multiple Sub-Mode Configuration enable
bits : 26 - 52 (27 bit)
EPI_HB8CFG2_CSCFGEXT : Chip Select Extended Configuration
bits : 27 - 54 (28 bit)
EPI Host-Bus 16 Configuration 2
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB16CFG2_MODE : CS1n Host Bus Sub-Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_HB16CFG2_MODE_ADMUX
ADMUX - AD[15:0]
0x1 : EPI_HB16CFG2_MODE_AD
ADNONMUX - D[15:0]
End of enumeration elements list.
EPI_HB16CFG2_RDWS : CS1n Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB16CFG2_RDWS_2
Active RDn is 2 EPI clocks
0x1 : EPI_HB16CFG2_RDWS_4
Active RDn is 4 EPI clocks
0x2 : EPI_HB16CFG2_RDWS_6
Active RDn is 6 EPI clocks
0x3 : EPI_HB16CFG2_RDWS_8
Active RDn is 8 EPI clocks
End of enumeration elements list.
EPI_HB16CFG2_WRWS : CS1n Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB16CFG2_WRWS_2
Active WRn is 2 EPI clocks
0x1 : EPI_HB16CFG2_WRWS_4
Active WRn is 4 EPI clocks
0x2 : EPI_HB16CFG2_WRWS_6
Active WRn is 6 EPI clocks
0x3 : EPI_HB16CFG2_WRWS_8
Active WRn is 8 EPI clocks
End of enumeration elements list.
EPI_HB16CFG2_BURST : CS1n Burst Mode
bits : 16 - 32 (17 bit)
EPI_HB16CFG2_RDCRE : CS1n PSRAM Configuration Register Read
bits : 17 - 34 (18 bit)
EPI_HB16CFG2_WRCRE : CS1n PSRAM Configuration Register Write
bits : 18 - 36 (19 bit)
EPI_HB16CFG2_ALEHIGH : CS1n ALE Strobe Polarity
bits : 19 - 38 (20 bit)
EPI_HB16CFG2_RDHIGH : CS1n READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB16CFG2_WRHIGH : CS1n WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI_HB16CFG2_CSCFG : Chip Select Configuration
bits : 24 - 49 (26 bit)
Enumeration:
0x0 : EPI_HB16CFG2_CSCFG_ALE
ALE Configuration
0x1 : EPI_HB16CFG2_CSCFG_CS
CSn Configuration
0x2 : EPI_HB16CFG2_CSCFG_DCS
Dual CSn Configuration
0x3 : EPI_HB16CFG2_CSCFG_ADCS
ALE with Dual CSn Configuration
End of enumeration elements list.
EPI_HB16CFG2_CSBAUD : Chip Select Baud Rate and Multiple Sub-Mode Configuration enable
bits : 26 - 52 (27 bit)
EPI_HB16CFG2_CSCFGEXT : Chip Select Extended Configuration
bits : 27 - 54 (28 bit)
EPI Address Map
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_ADDRMAP_ERADR : External RAM Address
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_ADDRMAP_ERADR_NONE
Not mapped
0x1 : EPI_ADDRMAP_ERADR_6000
At 0x6000.0000
0x2 : EPI_ADDRMAP_ERADR_8000
At 0x8000.0000
0x3 : EPI_ADDRMAP_ERADR_HBQS
Only to be used with Host Bus quad chip select. In quad chip select mode, CS0n maps to 0x6000.0000 and CS1n maps to 0x8000.0000
End of enumeration elements list.
EPI_ADDRMAP_ERSZ : External RAM Size
bits : 2 - 5 (4 bit)
Enumeration:
0x0 : EPI_ADDRMAP_ERSZ_256B
256 bytes; lower address range: 0x00 to 0xFF
0x1 : EPI_ADDRMAP_ERSZ_64KB
64 KB; lower address range: 0x0000 to 0xFFFF
0x2 : EPI_ADDRMAP_ERSZ_16MB
16 MB; lower address range: 0x00.0000 to 0xFF.FFFF
0x3 : EPI_ADDRMAP_ERSZ_256MB
256 MB; lower address range: 0x000.0000 to 0xFFF.FFFF
End of enumeration elements list.
EPI_ADDRMAP_EPADR : External Peripheral Address
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_ADDRMAP_EPADR_NONE
Not mapped
0x1 : EPI_ADDRMAP_EPADR_A000
At 0xA000.0000
0x2 : EPI_ADDRMAP_EPADR_C000
At 0xC000.0000
0x3 : EPI_ADDRMAP_EPADR_HBQS
Only to be used with Host Bus quad chip select. In quad chip select mode, CS2n maps to 0xA000.0000 and CS3n maps to 0xC000.0000
End of enumeration elements list.
EPI_ADDRMAP_EPSZ : External Peripheral Size
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_ADDRMAP_EPSZ_256B
256 bytes; lower address range: 0x00 to 0xFF
0x1 : EPI_ADDRMAP_EPSZ_64KB
64 KB; lower address range: 0x0000 to 0xFFFF
0x2 : EPI_ADDRMAP_EPSZ_16MB
16 MB; lower address range: 0x00.0000 to 0xFF.FFFF
0x3 : EPI_ADDRMAP_EPSZ_256MB
256 MB; lower address range: 0x000.0000 to 0xFFF.FFFF
End of enumeration elements list.
EPI_ADDRMAP_ECADR : External Code Address
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : EPI_ADDRMAP_ECADR_NONE
Not mapped
0x1 : EPI_ADDRMAP_ECADR_1000
At 0x1000.0000
End of enumeration elements list.
EPI_ADDRMAP_ECSZ : External Code Size
bits : 10 - 21 (12 bit)
Enumeration:
0x0 : EPI_ADDRMAP_ECSZ_256B
256 bytes; lower address range: 0x00 to 0xFF
0x1 : EPI_ADDRMAP_ECSZ_64KB
64 KB; lower address range: 0x0000 to 0xFFFF
0x2 : EPI_ADDRMAP_ECSZ_16MB
16 MB; lower address range: 0x00.0000 to 0xFF.FFFF
0x3 : EPI_ADDRMAP_ECSZ_256MB
256MB; lower address range: 0x000.0000 to 0x0FFF.FFFF
End of enumeration elements list.
EPI Address Map
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_ADDRMAP_ERADR : External RAM Address
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_ADDRMAP_ERADR_NONE
Not mapped
0x1 : EPI_ADDRMAP_ERADR_6000
At 0x6000.0000
0x2 : EPI_ADDRMAP_ERADR_8000
At 0x8000.0000
0x3 : EPI_ADDRMAP_ERADR_HBQS
Only to be used with Host Bus quad chip select. In quad chip select mode, CS0n maps to 0x6000.0000 and CS1n maps to 0x8000.0000
End of enumeration elements list.
EPI_ADDRMAP_ERSZ : External RAM Size
bits : 2 - 5 (4 bit)
Enumeration:
0x0 : EPI_ADDRMAP_ERSZ_256B
256 bytes lower address range: 0x00 to 0xFF
0x1 : EPI_ADDRMAP_ERSZ_64KB
64 KB lower address range: 0x0000 to 0xFFFF
0x2 : EPI_ADDRMAP_ERSZ_16MB
16 MB lower address range: 0x00.0000 to 0xFF.FFFF
0x3 : EPI_ADDRMAP_ERSZ_256MB
256 MB lower address range: 0x000.0000 to 0xFFF.FFFF
End of enumeration elements list.
EPI_ADDRMAP_EPADR : External Peripheral Address
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_ADDRMAP_EPADR_NONE
Not mapped
0x1 : EPI_ADDRMAP_EPADR_A000
At 0xA000.0000
0x2 : EPI_ADDRMAP_EPADR_C000
At 0xC000.0000
0x3 : EPI_ADDRMAP_EPADR_HBQS
Only to be used with Host Bus quad chip select. In quad chip select mode, CS2n maps to 0xA000.0000 and CS3n maps to 0xC000.0000
End of enumeration elements list.
EPI_ADDRMAP_EPSZ : External Peripheral Size
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_ADDRMAP_EPSZ_256B
256 bytes lower address range: 0x00 to 0xFF
0x1 : EPI_ADDRMAP_EPSZ_64KB
64 KB lower address range: 0x0000 to 0xFFFF
0x2 : EPI_ADDRMAP_EPSZ_16MB
16 MB lower address range: 0x00.0000 to 0xFF.FFFF
0x3 : EPI_ADDRMAP_EPSZ_256MB
256 MB lower address range: 0x000.0000 to 0xFFF.FFFF
End of enumeration elements list.
EPI_ADDRMAP_ECADR : External Code Address
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : EPI_ADDRMAP_ECADR_NONE
Not mapped
0x1 : EPI_ADDRMAP_ECADR_1000
At 0x1000.0000
End of enumeration elements list.
EPI_ADDRMAP_ECSZ : External Code Size
bits : 10 - 21 (12 bit)
Enumeration:
0x0 : EPI_ADDRMAP_ECSZ_256B
256 bytes lower address range: 0x00 to 0xFF
0x1 : EPI_ADDRMAP_ECSZ_64KB
64 KB lower address range: 0x0000 to 0xFFFF
0x2 : EPI_ADDRMAP_ECSZ_16MB
16 MB lower address range: 0x00.0000 to 0xFF.FFFF
0x3 : EPI_ADDRMAP_ECSZ_256MB
256MB lower address range: 0x000.0000 to 0x0FFF.FFFF
End of enumeration elements list.
EPI Read Size 0
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RSIZE0_SIZE : Current Size
bits : 0 - 1 (2 bit)
Enumeration:
0x1 : EPI_RSIZE0_SIZE_8BIT
Byte (8 bits)
0x2 : EPI_RSIZE0_SIZE_16BIT
Half-word (16 bits)
0x3 : EPI_RSIZE0_SIZE_32BIT
Word (32 bits)
End of enumeration elements list.
EPI Read Size 0
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RSIZE0_SIZE : Current Size
bits : 0 - 1 (2 bit)
Enumeration:
0x1 : EPI_RSIZE0_SIZE_8BIT
Byte (8 bits)
0x2 : EPI_RSIZE0_SIZE_16BIT
Half-word (16 bits)
0x3 : EPI_RSIZE0_SIZE_32BIT
Word (32 bits)
End of enumeration elements list.
EPI FIFO Level Selects
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_FIFOLVL_RDFIFO : Read FIFO
bits : 0 - 2 (3 bit)
Enumeration:
0x1 : EPI_FIFOLVL_RDFIFO_1
Trigger when there are 1 or more entries in the NBRFIFO
0x2 : EPI_FIFOLVL_RDFIFO_2
Trigger when there are 2 or more entries in the NBRFIFO
0x3 : EPI_FIFOLVL_RDFIFO_4
Trigger when there are 4 or more entries in the NBRFIFO
0x4 : EPI_FIFOLVL_RDFIFO_6
Trigger when there are 6 or more entries in the NBRFIFO
0x5 : EPI_FIFOLVL_RDFIFO_7
Trigger when there are 7 or more entries in the NBRFIFO
0x6 : EPI_FIFOLVL_RDFIFO_8
Trigger when there are 8 entries in the NBRFIFO
End of enumeration elements list.
EPI_FIFOLVL_WRFIFO : Write FIFO
bits : 4 - 10 (7 bit)
Enumeration:
0x0 : EPI_FIFOLVL_WRFIFO_EMPT
Interrupt is triggered while WRFIFO is empty.
0x2 : EPI_FIFOLVL_WRFIFO_2
Interrupt is triggered until there are only two slots available. Thus, trigger is deasserted when there are two WRFIFO entries present. This configuration is optimized for bursts of 2
0x3 : EPI_FIFOLVL_WRFIFO_1
Interrupt is triggered until there is one WRFIFO entry available. This configuration expects only single writes
0x4 : EPI_FIFOLVL_WRFIFO_NFULL
Trigger interrupt when WRFIFO is not full, meaning trigger will continue to assert until there are four entries in the WRFIFO
End of enumeration elements list.
EPI_FIFOLVL_RSERR : Read Stall Error
bits : 16 - 32 (17 bit)
EPI_FIFOLVL_WFERR : Write Full Error
bits : 17 - 34 (18 bit)
EPI FIFO Level Selects
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_FIFOLVL_RDFIFO : Read FIFO
bits : 0 - 2 (3 bit)
Enumeration:
0x1 : EPI_FIFOLVL_RDFIFO_1
Trigger when there are 1 or more entries in the NBRFIFO
0x2 : EPI_FIFOLVL_RDFIFO_2
Trigger when there are 2 or more entries in the NBRFIFO
0x3 : EPI_FIFOLVL_RDFIFO_4
Trigger when there are 4 or more entries in the NBRFIFO
0x4 : EPI_FIFOLVL_RDFIFO_6
Trigger when there are 6 or more entries in the NBRFIFO
0x5 : EPI_FIFOLVL_RDFIFO_7
Trigger when there are 7 or more entries in the NBRFIFO
0x6 : EPI_FIFOLVL_RDFIFO_8
Trigger when there are 8 entries in the NBRFIFO
End of enumeration elements list.
EPI_FIFOLVL_WRFIFO : Write FIFO
bits : 4 - 10 (7 bit)
Enumeration:
0x0 : EPI_FIFOLVL_WRFIFO_EMPT
Interrupt is triggered while WRFIFO is empty.
0x2 : EPI_FIFOLVL_WRFIFO_2
Interrupt is triggered until there are only two slots available. Thus, trigger is deasserted when there are two WRFIFO entries present. This configuration is optimized for bursts of 2
0x3 : EPI_FIFOLVL_WRFIFO_1
Interrupt is triggered until there is one WRFIFO entry available. This configuration expects only single writes
0x4 : EPI_FIFOLVL_WRFIFO_NFULL
Trigger interrupt when WRFIFO is not full, meaning trigger will continue to assert until there are four entries in the WRFIFO
End of enumeration elements list.
EPI_FIFOLVL_RSERR : Read Stall Error
bits : 16 - 32 (17 bit)
EPI_FIFOLVL_WFERR : Write Full Error
bits : 17 - 34 (18 bit)
EPI Write FIFO Count
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_WFIFOCNT_WTAV : Available Write Transactions
bits : 0 - 2 (3 bit)
EPI Write FIFO Count
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_WFIFOCNT_WTAV : Available Write Transactions
bits : 0 - 2 (3 bit)
EPI DMA Transmit Count
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_DMATXCNT_TXCNT : DMA Count
bits : 0 - 15 (16 bit)
EPI DMA Transmit Count
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_DMATXCNT_TXCNT : DMA Count
bits : 0 - 15 (16 bit)
EPI Interrupt Mask
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_IM_ERRIM : Error Interrupt Mask
bits : 0 - 0 (1 bit)
EPI_IM_RDIM : Read FIFO Full Interrupt Mask
bits : 1 - 2 (2 bit)
EPI_IM_WRIM : Write FIFO Empty Interrupt Mask
bits : 2 - 4 (3 bit)
EPI_IM_DMARDIM : Read uDMA Interrupt Mask
bits : 3 - 6 (4 bit)
EPI_IM_DMAWRIM : Write uDMA Interrupt Mask
bits : 4 - 8 (5 bit)
EPI Interrupt Mask
address_offset : 0x210 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_IM_ERRIM : Error Interrupt Mask
bits : 0 - 0 (1 bit)
EPI_IM_RDIM : Read FIFO Full Interrupt Mask
bits : 1 - 2 (2 bit)
EPI_IM_WRIM : Write FIFO Empty Interrupt Mask
bits : 2 - 4 (3 bit)
EPI_IM_DMARDIM : Read uDMA Interrupt Mask
bits : 3 - 6 (4 bit)
EPI_IM_DMAWRIM : Write uDMA Interrupt Mask
bits : 4 - 8 (5 bit)
EPI Raw Interrupt Status
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RIS_ERRRIS : Error Raw Interrupt Status
bits : 0 - 0 (1 bit)
EPI_RIS_RDRIS : Read Raw Interrupt Status
bits : 1 - 2 (2 bit)
EPI_RIS_WRRIS : Write Raw Interrupt Status
bits : 2 - 4 (3 bit)
EPI_RIS_DMARDRIS : Read uDMA Raw Interrupt Status
bits : 3 - 6 (4 bit)
EPI_RIS_DMAWRRIS : Write uDMA Raw Interrupt Status
bits : 4 - 8 (5 bit)
EPI Raw Interrupt Status
address_offset : 0x214 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RIS_ERRRIS : Error Raw Interrupt Status
bits : 0 - 0 (1 bit)
EPI_RIS_RDRIS : Read Raw Interrupt Status
bits : 1 - 2 (2 bit)
EPI_RIS_WRRIS : Write Raw Interrupt Status
bits : 2 - 4 (3 bit)
EPI_RIS_DMARDRIS : Read uDMA Raw Interrupt Status
bits : 3 - 6 (4 bit)
EPI_RIS_DMAWRRIS : Write uDMA Raw Interrupt Status
bits : 4 - 8 (5 bit)
EPI Masked Interrupt Status
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_MIS_ERRMIS : Error Masked Interrupt Status
bits : 0 - 0 (1 bit)
EPI_MIS_RDMIS : Read Masked Interrupt Status
bits : 1 - 2 (2 bit)
EPI_MIS_WRMIS : Write Masked Interrupt Status
bits : 2 - 4 (3 bit)
EPI_MIS_DMARDMIS : Read uDMA Masked Interrupt Status
bits : 3 - 6 (4 bit)
EPI_MIS_DMAWRMIS : Write uDMA Masked Interrupt Status
bits : 4 - 8 (5 bit)
EPI Masked Interrupt Status
address_offset : 0x218 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_MIS_ERRMIS : Error Masked Interrupt Status
bits : 0 - 0 (1 bit)
EPI_MIS_RDMIS : Read Masked Interrupt Status
bits : 1 - 2 (2 bit)
EPI_MIS_WRMIS : Write Masked Interrupt Status
bits : 2 - 4 (3 bit)
EPI_MIS_DMARDMIS : Read uDMA Masked Interrupt Status
bits : 3 - 6 (4 bit)
EPI_MIS_DMAWRMIS : Write uDMA Masked Interrupt Status
bits : 4 - 8 (5 bit)
EPI Error and Interrupt Status and Clear
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_EISC_TOUT : Timeout Error
bits : 0 - 0 (1 bit)
EPI_EISC_RSTALL : Read Stalled Error
bits : 1 - 2 (2 bit)
EPI_EISC_WTFULL : Write FIFO Full Error
bits : 2 - 4 (3 bit)
EPI_EISC_DMARDIC : Read uDMA Interrupt Clear
bits : 3 - 6 (4 bit)
EPI_EISC_DMAWRIC : Write uDMA Interrupt Clear
bits : 4 - 8 (5 bit)
EPI Error and Interrupt Status and Clear
address_offset : 0x21C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_EISC_TOUT : Timeout Error
bits : 0 - 0 (1 bit)
EPI_EISC_RSTALL : Read Stalled Error
bits : 1 - 2 (2 bit)
EPI_EISC_WTFULL : Write FIFO Full Error
bits : 2 - 4 (3 bit)
EPI_EISC_DMARDIC : Read uDMA Interrupt Clear
bits : 3 - 6 (4 bit)
EPI_EISC_DMAWRIC : Write uDMA Interrupt Clear
bits : 4 - 8 (5 bit)
EPI Read Address 0
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RADDR0_ADDR : Current Address
bits : 0 - 31 (32 bit)
EPI Read Address 0
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RADDR0_ADDR : Current Address
bits : 0 - 31 (32 bit)
EPI Non-Blocking Read Data 0
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RPSTD0_POSTCNT : Post Count
bits : 0 - 12 (13 bit)
EPI Non-Blocking Read Data 0
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RPSTD0_POSTCNT : Post Count
bits : 0 - 12 (13 bit)
EPI Read Size 1
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RSIZE1_SIZE : Current Size
bits : 0 - 1 (2 bit)
Enumeration:
0x1 : EPI_RSIZE1_SIZE_8BIT
Byte (8 bits)
0x2 : EPI_RSIZE1_SIZE_16BIT
Half-word (16 bits)
0x3 : EPI_RSIZE1_SIZE_32BIT
Word (32 bits)
End of enumeration elements list.
EPI Read Size 1
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RSIZE1_SIZE : Current Size
bits : 0 - 1 (2 bit)
Enumeration:
0x1 : EPI_RSIZE1_SIZE_8BIT
Byte (8 bits)
0x2 : EPI_RSIZE1_SIZE_16BIT
Half-word (16 bits)
0x3 : EPI_RSIZE1_SIZE_32BIT
Word (32 bits)
End of enumeration elements list.
EPI Host-Bus 8 Configuration 3
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB8CFG3_MODE : CS2n Host Bus Sub-Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_HB8CFG3_MODE_ADMUX
ADMUX - AD[7:0]
0x1 : EPI_HB8CFG3_MODE_AD
ADNONMUX - D[7:0]
End of enumeration elements list.
EPI_HB8CFG3_RDWS : CS2n Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB8CFG3_RDWS_2
Active RDn is 2 EPI clocks
0x1 : EPI_HB8CFG3_RDWS_4
Active RDn is 4 EPI clocks
0x2 : EPI_HB8CFG3_RDWS_6
Active RDn is 6 EPI clocks
0x3 : EPI_HB8CFG3_RDWS_8
Active RDn is 8 EPI clocks
End of enumeration elements list.
EPI_HB8CFG3_WRWS : CS2n Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB8CFG3_WRWS_2
Active WRn is 2 EPI clocks
0x1 : EPI_HB8CFG3_WRWS_4
Active WRn is 4 EPI clocks
0x2 : EPI_HB8CFG3_WRWS_6
Active WRn is 6 EPI clocks
0x3 : EPI_HB8CFG3_WRWS_8
Active WRn is 8 EPI clocks
End of enumeration elements list.
EPI_HB8CFG3_ALEHIGH : CS2n ALE Strobe Polarity
bits : 19 - 38 (20 bit)
EPI_HB8CFG3_RDHIGH : CS2n READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB8CFG3_WRHIGH : CS2n WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI Host-Bus 16 Configuration 3
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : EPI_ALT16
reset_Mask : 0x0
EPI_HB16CFG3_MODE : CS2n Host Bus Sub-Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_HB16CFG3_MODE_ADMUX
ADMUX - AD[15:0]
0x1 : EPI_HB16CFG3_MODE_AD
ADNONMUX - D[15:0]
End of enumeration elements list.
EPI_HB16CFG3_RDWS : CS2n Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB16CFG3_RDWS_2
Active RDn is 2 EPI clocks
0x1 : EPI_HB16CFG3_RDWS_4
Active RDn is 4 EPI clocks
0x2 : EPI_HB16CFG3_RDWS_6
Active RDn is 6 EPI clocks
0x3 : EPI_HB16CFG3_RDWS_8
Active RDn is 8 EPI clocks
End of enumeration elements list.
EPI_HB16CFG3_WRWS : CS2n Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB16CFG3_WRWS_2
Active WRn is 2 EPI clocks
0x1 : EPI_HB16CFG3_WRWS_4
Active WRn is 4 EPI clocks
0x2 : EPI_HB16CFG3_WRWS_6
Active WRn is 6 EPI clocks
0x3 : EPI_HB16CFG3_WRWS_8
Active WRn is 8 EPI clocks
End of enumeration elements list.
EPI_HB16CFG3_BURST : CS2n Burst Mode
bits : 16 - 32 (17 bit)
EPI_HB16CFG3_RDCRE : CS2n PSRAM Configuration Register Read
bits : 17 - 34 (18 bit)
EPI_HB16CFG3_WRCRE : CS2n PSRAM Configuration Register Write
bits : 18 - 36 (19 bit)
EPI_HB16CFG3_ALEHIGH : CS2n ALE Strobe Polarity
bits : 19 - 38 (20 bit)
EPI_HB16CFG3_RDHIGH : CS2n READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB16CFG3_WRHIGH : CS2n WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI Host-Bus 8 Configuration 3
address_offset : 0x308 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB8CFG3_MODE : CS2n Host Bus Sub-Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_HB8CFG3_MODE_ADMUX
ADMUX - AD[7:0]
0x1 : EPI_HB8CFG3_MODE_AD
ADNONMUX - D[7:0]
End of enumeration elements list.
EPI_HB8CFG3_RDWS : CS2n Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB8CFG3_RDWS_2
Active RDn is 2 EPI clocks
0x1 : EPI_HB8CFG3_RDWS_4
Active RDn is 4 EPI clocks
0x2 : EPI_HB8CFG3_RDWS_6
Active RDn is 6 EPI clocks
0x3 : EPI_HB8CFG3_RDWS_8
Active RDn is 8 EPI clocks
End of enumeration elements list.
EPI_HB8CFG3_WRWS : CS2n Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB8CFG3_WRWS_2
Active WRn is 2 EPI clocks
0x1 : EPI_HB8CFG3_WRWS_4
Active WRn is 4 EPI clocks
0x2 : EPI_HB8CFG3_WRWS_6
Active WRn is 6 EPI clocks
0x3 : EPI_HB8CFG3_WRWS_8
Active WRn is 8 EPI clocks
End of enumeration elements list.
EPI_HB8CFG3_ALEHIGH : CS2n ALE Strobe Polarity
bits : 19 - 38 (20 bit)
EPI_HB8CFG3_RDHIGH : CS2n READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB8CFG3_WRHIGH : CS2n WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI Host-Bus 16 Configuration 3
address_offset : 0x308 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB16CFG3_MODE : CS2n Host Bus Sub-Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_HB16CFG3_MODE_ADMUX
ADMUX - AD[15:0]
0x1 : EPI_HB16CFG3_MODE_AD
ADNONMUX - D[15:0]
End of enumeration elements list.
EPI_HB16CFG3_RDWS : CS2n Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB16CFG3_RDWS_2
Active RDn is 2 EPI clocks
0x1 : EPI_HB16CFG3_RDWS_4
Active RDn is 4 EPI clocks
0x2 : EPI_HB16CFG3_RDWS_6
Active RDn is 6 EPI clocks
0x3 : EPI_HB16CFG3_RDWS_8
Active RDn is 8 EPI clocks
End of enumeration elements list.
EPI_HB16CFG3_WRWS : CS2n Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB16CFG3_WRWS_2
Active WRn is 2 EPI clocks
0x1 : EPI_HB16CFG3_WRWS_4
Active WRn is 4 EPI clocks
0x2 : EPI_HB16CFG3_WRWS_6
Active WRn is 6 EPI clocks
0x3 : EPI_HB16CFG3_WRWS_8
Active WRn is 8 EPI clocks
End of enumeration elements list.
EPI_HB16CFG3_BURST : CS2n Burst Mode
bits : 16 - 32 (17 bit)
EPI_HB16CFG3_RDCRE : CS2n PSRAM Configuration Register Read
bits : 17 - 34 (18 bit)
EPI_HB16CFG3_WRCRE : CS2n PSRAM Configuration Register Write
bits : 18 - 36 (19 bit)
EPI_HB16CFG3_ALEHIGH : CS2n ALE Strobe Polarity
bits : 19 - 38 (20 bit)
EPI_HB16CFG3_RDHIGH : CS2n READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB16CFG3_WRHIGH : CS2n WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI Host-Bus 16 Configuration 4
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB16CFG4_MODE : CS3n Host Bus Sub-Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_HB16CFG4_MODE_ADMUX
ADMUX - AD[15:0]
0x1 : EPI_HB16CFG4_MODE_AD
ADNONMUX - D[15:0]
End of enumeration elements list.
EPI_HB16CFG4_RDWS : CS3n Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB16CFG4_RDWS_2
Active RDn is 2 EPI clocks
0x1 : EPI_HB16CFG4_RDWS_4
Active RDn is 4 EPI clocks
0x2 : EPI_HB16CFG4_RDWS_6
Active RDn is 6 EPI clocks
0x3 : EPI_HB16CFG4_RDWS_8
Active RDn is 8 EPI clocks
End of enumeration elements list.
EPI_HB16CFG4_WRWS : CS3n Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB16CFG4_WRWS_2
Active WRn is 2 EPI clocks
0x1 : EPI_HB16CFG4_WRWS_4
Active WRn is 4 EPI clocks
0x2 : EPI_HB16CFG4_WRWS_6
Active WRn is 6 EPI clocks
0x3 : EPI_HB16CFG4_WRWS_8
Active WRn is 8 EPI clocks
End of enumeration elements list.
EPI_HB16CFG4_BURST : CS3n Burst Mode
bits : 16 - 32 (17 bit)
EPI_HB16CFG4_RDCRE : CS3n PSRAM Configuration Register Read
bits : 17 - 34 (18 bit)
EPI_HB16CFG4_WRCRE : CS3n PSRAM Configuration Register Write
bits : 18 - 36 (19 bit)
EPI_HB16CFG4_ALEHIGH : CS3n ALE Strobe Polarity
bits : 19 - 38 (20 bit)
EPI_HB16CFG4_RDHIGH : CS3n READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB16CFG4_WRHIGH : CS3n WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI Host-Bus 8 Configuration 4
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : EPI_ALT8
reset_Mask : 0x0
EPI_HB8CFG4_MODE : CS3n Host Bus Sub-Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_HB8CFG4_MODE_ADMUX
ADMUX - AD[7:0]
0x1 : EPI_HB8CFG4_MODE_AD
ADNONMUX - D[7:0]
End of enumeration elements list.
EPI_HB8CFG4_RDWS : CS3n Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB8CFG4_RDWS_2
Active RDn is 2 EPI clocks
0x1 : EPI_HB8CFG4_RDWS_4
Active RDn is 4 EPI clocks
0x2 : EPI_HB8CFG4_RDWS_6
Active RDn is 6 EPI clocks
0x3 : EPI_HB8CFG4_RDWS_8
Active RDn is 8 EPI clocks
End of enumeration elements list.
EPI_HB8CFG4_WRWS : CS3n Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB8CFG4_WRWS_2
Active WRn is 2 EPI clocks
0x1 : EPI_HB8CFG4_WRWS_4
Active WRn is 4 EPI clocks
0x2 : EPI_HB8CFG4_WRWS_6
Active WRn is 6 EPI clocks
0x3 : EPI_HB8CFG4_WRWS_8
Active WRn is 8 EPI clocks
End of enumeration elements list.
EPI_HB8CFG4_ALEHIGH : CS3n ALE Strobe Polarity
bits : 19 - 38 (20 bit)
EPI_HB8CFG4_RDHIGH : CS2n READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB8CFG4_WRHIGH : CS3n WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI Host-Bus 16 Configuration 4
address_offset : 0x30C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB16CFG4_MODE : CS3n Host Bus Sub-Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_HB16CFG4_MODE_ADMUX
ADMUX - AD[15:0]
0x1 : EPI_HB16CFG4_MODE_AD
ADNONMUX - D[15:0]
End of enumeration elements list.
EPI_HB16CFG4_RDWS : CS3n Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB16CFG4_RDWS_2
Active RDn is 2 EPI clocks
0x1 : EPI_HB16CFG4_RDWS_4
Active RDn is 4 EPI clocks
0x2 : EPI_HB16CFG4_RDWS_6
Active RDn is 6 EPI clocks
0x3 : EPI_HB16CFG4_RDWS_8
Active RDn is 8 EPI clocks
End of enumeration elements list.
EPI_HB16CFG4_WRWS : CS3n Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB16CFG4_WRWS_2
Active WRn is 2 EPI clocks
0x1 : EPI_HB16CFG4_WRWS_4
Active WRn is 4 EPI clocks
0x2 : EPI_HB16CFG4_WRWS_6
Active WRn is 6 EPI clocks
0x3 : EPI_HB16CFG4_WRWS_8
Active WRn is 8 EPI clocks
End of enumeration elements list.
EPI_HB16CFG4_BURST : CS3n Burst Mode
bits : 16 - 32 (17 bit)
EPI_HB16CFG4_RDCRE : CS3n PSRAM Configuration Register Read
bits : 17 - 34 (18 bit)
EPI_HB16CFG4_WRCRE : CS3n PSRAM Configuration Register Write
bits : 18 - 36 (19 bit)
EPI_HB16CFG4_ALEHIGH : CS3n ALE Strobe Polarity
bits : 19 - 38 (20 bit)
EPI_HB16CFG4_RDHIGH : CS3n READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB16CFG4_WRHIGH : CS3n WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI Host-Bus 8 Configuration 4
address_offset : 0x30C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB8CFG4_MODE : CS3n Host Bus Sub-Mode
bits : 0 - 1 (2 bit)
Enumeration:
0x0 : EPI_HB8CFG4_MODE_ADMUX
ADMUX - AD[7:0]
0x1 : EPI_HB8CFG4_MODE_AD
ADNONMUX - D[7:0]
End of enumeration elements list.
EPI_HB8CFG4_RDWS : CS3n Read Wait States
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : EPI_HB8CFG4_RDWS_2
Active RDn is 2 EPI clocks
0x1 : EPI_HB8CFG4_RDWS_4
Active RDn is 4 EPI clocks
0x2 : EPI_HB8CFG4_RDWS_6
Active RDn is 6 EPI clocks
0x3 : EPI_HB8CFG4_RDWS_8
Active RDn is 8 EPI clocks
End of enumeration elements list.
EPI_HB8CFG4_WRWS : CS3n Write Wait States
bits : 6 - 13 (8 bit)
Enumeration:
0x0 : EPI_HB8CFG4_WRWS_2
Active WRn is 2 EPI clocks
0x1 : EPI_HB8CFG4_WRWS_4
Active WRn is 4 EPI clocks
0x2 : EPI_HB8CFG4_WRWS_6
Active WRn is 6 EPI clocks
0x3 : EPI_HB8CFG4_WRWS_8
Active WRn is 8 EPI clocks
End of enumeration elements list.
EPI_HB8CFG4_ALEHIGH : CS3n ALE Strobe Polarity
bits : 19 - 38 (20 bit)
EPI_HB8CFG4_RDHIGH : CS2n READ Strobe Polarity
bits : 20 - 40 (21 bit)
EPI_HB8CFG4_WRHIGH : CS3n WRITE Strobe Polarity
bits : 21 - 42 (22 bit)
EPI Host-Bus 8 Timing Extension
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB8TIME_RDWSM : Read Wait State Minus One
bits : 0 - 0 (1 bit)
EPI_HB8TIME_WRWSM : Write Wait State Minus One
bits : 4 - 8 (5 bit)
EPI_HB8TIME_CAPWIDTH : CS0n Inter-transfer Capture Width
bits : 12 - 25 (14 bit)
EPI_HB8TIME_IRDYDLY : CS0n Input Ready Delay
bits : 24 - 49 (26 bit)
EPI Host-Bus 16 Timing Extension
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : EPI_ALT16
reset_Mask : 0x0
EPI_HB16TIME_RDWSM : Read Wait State Minus One
bits : 0 - 0 (1 bit)
EPI_HB16TIME_WRWSM : Write Wait State Minus One
bits : 4 - 8 (5 bit)
EPI_HB16TIME_CAPWIDTH : CS0n Inter-transfer Capture Width
bits : 12 - 25 (14 bit)
EPI_HB16TIME_PSRAMSZ : PSRAM Row Size
bits : 16 - 34 (19 bit)
Enumeration:
0x0 : EPI_HB16TIME_PSRAMSZ_0
No row size limitation
0x1 : EPI_HB16TIME_PSRAMSZ_128B
128 B
0x2 : EPI_HB16TIME_PSRAMSZ_256B
256 B
0x3 : EPI_HB16TIME_PSRAMSZ_512B
512 B
0x4 : EPI_HB16TIME_PSRAMSZ_1KB
1024 B
0x5 : EPI_HB16TIME_PSRAMSZ_2KB
2048 B
0x6 : EPI_HB16TIME_PSRAMSZ_4KB
4096 B
0x7 : EPI_HB16TIME_PSRAMSZ_8KB
8192 B
End of enumeration elements list.
EPI_HB16TIME_IRDYDLY : CS0n Input Ready Delay
bits : 24 - 49 (26 bit)
EPI Host-Bus 8 Timing Extension
address_offset : 0x310 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB8TIME_RDWSM : Read Wait State Minus One
bits : 0 - 0 (1 bit)
EPI_HB8TIME_WRWSM : Write Wait State Minus One
bits : 4 - 8 (5 bit)
EPI_HB8TIME_CAPWIDTH : CS0n Inter-transfer Capture Width
bits : 12 - 25 (14 bit)
EPI_HB8TIME_IRDYDLY : CS0n Input Ready Delay
bits : 24 - 49 (26 bit)
EPI Host-Bus 16 Timing Extension
address_offset : 0x310 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB16TIME_RDWSM : Read Wait State Minus One
bits : 0 - 0 (1 bit)
EPI_HB16TIME_WRWSM : Write Wait State Minus One
bits : 4 - 8 (5 bit)
EPI_HB16TIME_CAPWIDTH : CS0n Inter-transfer Capture Width
bits : 12 - 25 (14 bit)
EPI_HB16TIME_PSRAMSZ : PSRAM Row Size
bits : 16 - 34 (19 bit)
Enumeration:
0x0 : EPI_HB16TIME_PSRAMSZ_0
No row size limitation
0x1 : EPI_HB16TIME_PSRAMSZ_128B
128 B
0x2 : EPI_HB16TIME_PSRAMSZ_256B
256 B
0x3 : EPI_HB16TIME_PSRAMSZ_512B
512 B
0x4 : EPI_HB16TIME_PSRAMSZ_1KB
1024 B
0x5 : EPI_HB16TIME_PSRAMSZ_2KB
2048 B
0x6 : EPI_HB16TIME_PSRAMSZ_4KB
4096 B
0x7 : EPI_HB16TIME_PSRAMSZ_8KB
8192 B
End of enumeration elements list.
EPI_HB16TIME_IRDYDLY : CS0n Input Ready Delay
bits : 24 - 49 (26 bit)
EPI Host-Bus 8 Timing Extension
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB8TIME2_RDWSM : CS1n Read Wait State Minus One
bits : 0 - 0 (1 bit)
EPI_HB8TIME2_WRWSM : CS1n Write Wait State Minus One
bits : 4 - 8 (5 bit)
EPI_HB8TIME2_CAPWIDTH : CS1n Inter-transfer Capture Width
bits : 12 - 25 (14 bit)
EPI_HB8TIME2_IRDYDLY : CS1n Input Ready Delay
bits : 24 - 49 (26 bit)
EPI Host-Bus 16 Timing Extension
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : EPI_ALT16
reset_Mask : 0x0
EPI_HB16TIME2_RDWSM : CS1n Read Wait State Minus One
bits : 0 - 0 (1 bit)
EPI_HB16TIME2_WRWSM : CS1n Write Wait State Minus One
bits : 4 - 8 (5 bit)
EPI_HB16TIME2_CAPWIDTH : CS1n Inter-transfer Capture Width
bits : 12 - 25 (14 bit)
EPI_HB16TIME2_PSRAMSZ : PSRAM Row Size
bits : 16 - 34 (19 bit)
Enumeration:
0x0 : EPI_HB16TIME2_PSRAMSZ_0
No row size limitation
0x1 : EPI_HB16TIME2_PSRAMSZ_128B
128 B
0x2 : EPI_HB16TIME2_PSRAMSZ_256B
256 B
0x3 : EPI_HB16TIME2_PSRAMSZ_512B
512 B
0x4 : EPI_HB16TIME2_PSRAMSZ_1KB
1024 B
0x5 : EPI_HB16TIME2_PSRAMSZ_2KB
2048 B
0x6 : EPI_HB16TIME2_PSRAMSZ_4KB
4096 B
0x7 : EPI_HB16TIME2_PSRAMSZ_8KB
8192 B
End of enumeration elements list.
EPI_HB16TIME2_IRDYDLY : CS1n Input Ready Delay
bits : 24 - 49 (26 bit)
EPI Host-Bus 8 Timing Extension
address_offset : 0x314 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB8TIME2_RDWSM : CS1n Read Wait State Minus One
bits : 0 - 0 (1 bit)
EPI_HB8TIME2_WRWSM : CS1n Write Wait State Minus One
bits : 4 - 8 (5 bit)
EPI_HB8TIME2_CAPWIDTH : CS1n Inter-transfer Capture Width
bits : 12 - 25 (14 bit)
EPI_HB8TIME2_IRDYDLY : CS1n Input Ready Delay
bits : 24 - 49 (26 bit)
EPI Host-Bus 16 Timing Extension
address_offset : 0x314 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB16TIME2_RDWSM : CS1n Read Wait State Minus One
bits : 0 - 0 (1 bit)
EPI_HB16TIME2_WRWSM : CS1n Write Wait State Minus One
bits : 4 - 8 (5 bit)
EPI_HB16TIME2_CAPWIDTH : CS1n Inter-transfer Capture Width
bits : 12 - 25 (14 bit)
EPI_HB16TIME2_PSRAMSZ : PSRAM Row Size
bits : 16 - 34 (19 bit)
Enumeration:
0x0 : EPI_HB16TIME2_PSRAMSZ_0
No row size limitation
0x1 : EPI_HB16TIME2_PSRAMSZ_128B
128 B
0x2 : EPI_HB16TIME2_PSRAMSZ_256B
256 B
0x3 : EPI_HB16TIME2_PSRAMSZ_512B
512 B
0x4 : EPI_HB16TIME2_PSRAMSZ_1KB
1024 B
0x5 : EPI_HB16TIME2_PSRAMSZ_2KB
2048 B
0x6 : EPI_HB16TIME2_PSRAMSZ_4KB
4096 B
0x7 : EPI_HB16TIME2_PSRAMSZ_8KB
8192 B
End of enumeration elements list.
EPI_HB16TIME2_IRDYDLY : CS1n Input Ready Delay
bits : 24 - 49 (26 bit)
EPI Host-Bus 16 Timing Extension
address_offset : 0x318 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB16TIME3_RDWSM : CS2n Read Wait State Minus One
bits : 0 - 0 (1 bit)
EPI_HB16TIME3_WRWSM : CS2n Write Wait State Minus One
bits : 4 - 8 (5 bit)
EPI_HB16TIME3_CAPWIDTH : CS2n Inter-transfer Capture Width
bits : 12 - 25 (14 bit)
EPI_HB16TIME3_PSRAMSZ : PSRAM Row Size
bits : 16 - 34 (19 bit)
Enumeration:
0x0 : EPI_HB16TIME3_PSRAMSZ_0
No row size limitation
0x1 : EPI_HB16TIME3_PSRAMSZ_128B
128 B
0x2 : EPI_HB16TIME3_PSRAMSZ_256B
256 B
0x3 : EPI_HB16TIME3_PSRAMSZ_512B
512 B
0x4 : EPI_HB16TIME3_PSRAMSZ_1KB
1024 B
0x5 : EPI_HB16TIME3_PSRAMSZ_2KB
2048 B
0x6 : EPI_HB16TIME3_PSRAMSZ_4KB
4096 B
0x7 : EPI_HB16TIME3_PSRAMSZ_8KB
8192 B
End of enumeration elements list.
EPI_HB16TIME3_IRDYDLY : CS2n Input Ready Delay
bits : 24 - 49 (26 bit)
EPI Host-Bus 8 Timing Extension
address_offset : 0x318 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : EPI_ALT8
reset_Mask : 0x0
EPI_HB8TIME3_RDWSM : CS2n Read Wait State Minus One
bits : 0 - 0 (1 bit)
EPI_HB8TIME3_WRWSM : CS2n Write Wait State Minus One
bits : 4 - 8 (5 bit)
EPI_HB8TIME3_CAPWIDTH : CS2n Inter-transfer Capture Width
bits : 12 - 25 (14 bit)
EPI_HB8TIME3_IRDYDLY : CS2n Input Ready Delay
bits : 24 - 49 (26 bit)
EPI Host-Bus 16 Timing Extension
address_offset : 0x318 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB16TIME3_RDWSM : CS2n Read Wait State Minus One
bits : 0 - 0 (1 bit)
EPI_HB16TIME3_WRWSM : CS2n Write Wait State Minus One
bits : 4 - 8 (5 bit)
EPI_HB16TIME3_CAPWIDTH : CS2n Inter-transfer Capture Width
bits : 12 - 25 (14 bit)
EPI_HB16TIME3_PSRAMSZ : PSRAM Row Size
bits : 16 - 34 (19 bit)
Enumeration:
0x0 : EPI_HB16TIME3_PSRAMSZ_0
No row size limitation
0x1 : EPI_HB16TIME3_PSRAMSZ_128B
128 B
0x2 : EPI_HB16TIME3_PSRAMSZ_256B
256 B
0x3 : EPI_HB16TIME3_PSRAMSZ_512B
512 B
0x4 : EPI_HB16TIME3_PSRAMSZ_1KB
1024 B
0x5 : EPI_HB16TIME3_PSRAMSZ_2KB
2048 B
0x6 : EPI_HB16TIME3_PSRAMSZ_4KB
4096 B
0x7 : EPI_HB16TIME3_PSRAMSZ_8KB
8192 B
End of enumeration elements list.
EPI_HB16TIME3_IRDYDLY : CS2n Input Ready Delay
bits : 24 - 49 (26 bit)
EPI Host-Bus 8 Timing Extension
address_offset : 0x318 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB8TIME3_RDWSM : CS2n Read Wait State Minus One
bits : 0 - 0 (1 bit)
EPI_HB8TIME3_WRWSM : CS2n Write Wait State Minus One
bits : 4 - 8 (5 bit)
EPI_HB8TIME3_CAPWIDTH : CS2n Inter-transfer Capture Width
bits : 12 - 25 (14 bit)
EPI_HB8TIME3_IRDYDLY : CS2n Input Ready Delay
bits : 24 - 49 (26 bit)
EPI Host-Bus 8 Timing Extension
address_offset : 0x31C Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : EPI_ALT8
reset_Mask : 0x0
EPI_HB8TIME4_RDWSM : CS3n Read Wait State Minus One
bits : 0 - 0 (1 bit)
EPI_HB8TIME4_WRWSM : CS3n Write Wait State Minus One
bits : 4 - 8 (5 bit)
EPI_HB8TIME4_CAPWIDTH : CS3n Inter-transfer Capture Width
bits : 12 - 25 (14 bit)
EPI_HB8TIME4_IRDYDLY : CS3n Input Ready Delay
bits : 24 - 49 (26 bit)
EPI Host-Bus 16 Timing Extension
address_offset : 0x31C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB16TIME4_RDWSM : CS3n Read Wait State Minus One
bits : 0 - 0 (1 bit)
EPI_HB16TIME4_WRWSM : CS3n Write Wait State Minus One
bits : 4 - 8 (5 bit)
EPI_HB16TIME4_CAPWIDTH : CS3n Inter-transfer Capture Width
bits : 12 - 25 (14 bit)
EPI_HB16TIME4_PSRAMSZ : PSRAM Row Size
bits : 16 - 34 (19 bit)
Enumeration:
0x0 : EPI_HB16TIME4_PSRAMSZ_0
No row size limitation
0x1 : EPI_HB16TIME4_PSRAMSZ_128B
128 B
0x2 : EPI_HB16TIME4_PSRAMSZ_256B
256 B
0x3 : EPI_HB16TIME4_PSRAMSZ_512B
512 B
0x4 : EPI_HB16TIME4_PSRAMSZ_1KB
1024 B
0x5 : EPI_HB16TIME4_PSRAMSZ_2KB
2048 B
0x6 : EPI_HB16TIME4_PSRAMSZ_4KB
4096 B
0x7 : EPI_HB16TIME4_PSRAMSZ_8KB
8192 B
End of enumeration elements list.
EPI_HB16TIME4_IRDYDLY : CS3n Input Ready Delay
bits : 24 - 49 (26 bit)
EPI Host-Bus 8 Timing Extension
address_offset : 0x31C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB8TIME4_RDWSM : CS3n Read Wait State Minus One
bits : 0 - 0 (1 bit)
EPI_HB8TIME4_WRWSM : CS3n Write Wait State Minus One
bits : 4 - 8 (5 bit)
EPI_HB8TIME4_CAPWIDTH : CS3n Inter-transfer Capture Width
bits : 12 - 25 (14 bit)
EPI_HB8TIME4_IRDYDLY : CS3n Input Ready Delay
bits : 24 - 49 (26 bit)
EPI Host-Bus 16 Timing Extension
address_offset : 0x31C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HB16TIME4_RDWSM : CS3n Read Wait State Minus One
bits : 0 - 0 (1 bit)
EPI_HB16TIME4_WRWSM : CS3n Write Wait State Minus One
bits : 4 - 8 (5 bit)
EPI_HB16TIME4_CAPWIDTH : CS3n Inter-transfer Capture Width
bits : 12 - 25 (14 bit)
EPI_HB16TIME4_PSRAMSZ : PSRAM Row Size
bits : 16 - 34 (19 bit)
Enumeration:
0x0 : EPI_HB16TIME4_PSRAMSZ_0
No row size limitation
0x1 : EPI_HB16TIME4_PSRAMSZ_128B
128 B
0x2 : EPI_HB16TIME4_PSRAMSZ_256B
256 B
0x3 : EPI_HB16TIME4_PSRAMSZ_512B
512 B
0x4 : EPI_HB16TIME4_PSRAMSZ_1KB
1024 B
0x5 : EPI_HB16TIME4_PSRAMSZ_2KB
2048 B
0x6 : EPI_HB16TIME4_PSRAMSZ_4KB
4096 B
0x7 : EPI_HB16TIME4_PSRAMSZ_8KB
8192 B
End of enumeration elements list.
EPI_HB16TIME4_IRDYDLY : CS3n Input Ready Delay
bits : 24 - 49 (26 bit)
EPI Read Address 1
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RADDR1_ADDR : Current Address
bits : 0 - 31 (32 bit)
EPI Read Address 1
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RADDR1_ADDR : Current Address
bits : 0 - 31 (32 bit)
EPI Host-Bus PSRAM
address_offset : 0x360 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HBPSRAM_CR : PSRAM Config Register
bits : 0 - 20 (21 bit)
EPI Host-Bus PSRAM
address_offset : 0x360 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_HBPSRAM_CR : PSRAM Config Register
bits : 0 - 20 (21 bit)
EPI Non-Blocking Read Data 1
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RPSTD1_POSTCNT : Post Count
bits : 0 - 12 (13 bit)
EPI Non-Blocking Read Data 1
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RPSTD1_POSTCNT : Post Count
bits : 0 - 12 (13 bit)
EPI Main Baud Rate
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_BAUD_COUNT0 : Baud Rate Counter 0
bits : 0 - 15 (16 bit)
EPI_BAUD_COUNT1 : Baud Rate Counter 1
bits : 16 - 47 (32 bit)
EPI Main Baud Rate
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_BAUD_COUNT0 : Baud Rate Counter 0
bits : 0 - 15 (16 bit)
EPI_BAUD_COUNT1 : Baud Rate Counter 1
bits : 16 - 47 (32 bit)
EPI Status
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_STAT_ACTIVE : Register Active
bits : 0 - 0 (1 bit)
EPI_STAT_NBRBUSY : Non-Blocking Read Busy
bits : 4 - 8 (5 bit)
EPI_STAT_WBUSY : Write Busy
bits : 5 - 10 (6 bit)
EPI_STAT_INITSEQ : Initialization Sequence
bits : 6 - 12 (7 bit)
EPI_STAT_XFEMPTY : External FIFO Empty
bits : 7 - 14 (8 bit)
EPI_STAT_XFFULL : External FIFO Full
bits : 8 - 16 (9 bit)
EPI Status
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_STAT_ACTIVE : Register Active
bits : 0 - 0 (1 bit)
EPI_STAT_NBRBUSY : Non-Blocking Read Busy
bits : 4 - 8 (5 bit)
EPI_STAT_WBUSY : Write Busy
bits : 5 - 10 (6 bit)
EPI_STAT_INITSEQ : Initialization Sequence
bits : 6 - 12 (7 bit)
EPI_STAT_XFEMPTY : External FIFO Empty
bits : 7 - 14 (8 bit)
EPI_STAT_XFFULL : External FIFO Full
bits : 8 - 16 (9 bit)
EPI Read FIFO Count
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RFIFOCNT_COUNT : FIFO Count
bits : 0 - 3 (4 bit)
EPI Read FIFO Count
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_RFIFOCNT_COUNT : FIFO Count
bits : 0 - 3 (4 bit)
EPI Read FIFO
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO0_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO0_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 1
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO1_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 1
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO1_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 2
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO2_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 2
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO2_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 3
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO3_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 3
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO3_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Main Baud Rate
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_BAUD2_COUNT0 : CS2n Baud Rate Counter 0
bits : 0 - 15 (16 bit)
EPI_BAUD2_COUNT1 : CS3n Baud Rate Counter 1
bits : 16 - 47 (32 bit)
EPI Main Baud Rate
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_BAUD2_COUNT0 : CS2n Baud Rate Counter 0
bits : 0 - 15 (16 bit)
EPI_BAUD2_COUNT1 : CS3n Baud Rate Counter 1
bits : 16 - 47 (32 bit)
EPI Read FIFO Alias 4
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO4_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 4
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO4_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 5
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO5_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 5
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO5_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 6
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO6_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 6
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO6_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 7
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO7_DATA : Reads Data
bits : 0 - 31 (32 bit)
EPI Read FIFO Alias 7
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPI_READFIFO7_DATA : Reads Data
bits : 0 - 31 (32 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.