\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Hibernation RTC Counter
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_RTCC : RTC Counter
bits : 0 - 31 (32 bit)
Hibernation RTC Counter
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_RTCC : RTC Counter
bits : 0 - 31 (32 bit)
Hibernation Control
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_CTL_RTCEN : RTC Timer Enable
bits : 0 - 0 (1 bit)
HIB_CTL_HIBREQ : Hibernation Request
bits : 1 - 2 (2 bit)
HIB_CTL_RTCWEN : RTC Wake-up Enable
bits : 3 - 6 (4 bit)
HIB_CTL_PINWEN : External Wake Pin Enable
bits : 4 - 8 (5 bit)
HIB_CTL_CLK32EN : Clocking Enable
bits : 6 - 12 (7 bit)
HIB_CTL_VABORT : Power Cut Abort Enable
bits : 7 - 14 (8 bit)
HIB_CTL_VDD3ON : VDD Powered
bits : 8 - 16 (9 bit)
HIB_CTL_BATWKEN : Wake on Low Battery
bits : 9 - 18 (10 bit)
HIB_CTL_BATCHK : Check Battery Status
bits : 10 - 20 (11 bit)
HIB_CTL_VBATSEL : Select for Low-Battery Comparator
bits : 13 - 27 (15 bit)
Enumeration:
0x0 : HIB_CTL_VBATSEL_1_9V
1.9 Volts
0x1 : HIB_CTL_VBATSEL_2_1V
2.1 Volts (default)
0x2 : HIB_CTL_VBATSEL_2_3V
2.3 Volts
0x3 : HIB_CTL_VBATSEL_2_5V
2.5 Volts
End of enumeration elements list.
HIB_CTL_OSCBYP : Oscillator Bypass
bits : 16 - 32 (17 bit)
HIB_CTL_OSCDRV : Oscillator Drive Capability
bits : 17 - 34 (18 bit)
HIB_CTL_OSCSEL : Oscillator Select
bits : 19 - 38 (20 bit)
HIB_CTL_RETCLR : GPIO Retention/Clear
bits : 30 - 60 (31 bit)
HIB_CTL_WRC : Write Complete/Capable
bits : 31 - 62 (32 bit)
Hibernation Control
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_CTL_RTCEN : RTC Timer Enable
bits : 0 - 0 (1 bit)
HIB_CTL_HIBREQ : Hibernation Request
bits : 1 - 2 (2 bit)
HIB_CTL_RTCWEN : RTC Wake-up Enable
bits : 3 - 6 (4 bit)
HIB_CTL_PINWEN : External Wake Pin Enable
bits : 4 - 8 (5 bit)
HIB_CTL_CLK32EN : Clocking Enable
bits : 6 - 12 (7 bit)
HIB_CTL_VABORT : Power Cut Abort Enable
bits : 7 - 14 (8 bit)
HIB_CTL_VDD3ON : VDD Powered
bits : 8 - 16 (9 bit)
HIB_CTL_BATWKEN : Wake on Low Battery
bits : 9 - 18 (10 bit)
HIB_CTL_BATCHK : Check Battery Status
bits : 10 - 20 (11 bit)
HIB_CTL_VBATSEL : Select for Low-Battery Comparator
bits : 13 - 27 (15 bit)
Enumeration:
0x0 : HIB_CTL_VBATSEL_1_9V
1.9 Volts
0x1 : HIB_CTL_VBATSEL_2_1V
2.1 Volts (default)
0x2 : HIB_CTL_VBATSEL_2_3V
2.3 Volts
0x3 : HIB_CTL_VBATSEL_2_5V
2.5 Volts
End of enumeration elements list.
HIB_CTL_OSCBYP : Oscillator Bypass
bits : 16 - 32 (17 bit)
HIB_CTL_OSCDRV : Oscillator Drive Capability
bits : 17 - 34 (18 bit)
HIB_CTL_OSCSEL : Oscillator Select
bits : 19 - 38 (20 bit)
HIB_CTL_RETCLR : GPIO Retention/Clear
bits : 30 - 60 (31 bit)
HIB_CTL_WRC : Write Complete/Capable
bits : 31 - 62 (32 bit)
Hibernation Interrupt Mask
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_IM_RTCALT0 : RTC Alert 0 Interrupt Mask
bits : 0 - 0 (1 bit)
HIB_IM_LOWBAT : Low Battery Voltage Interrupt Mask
bits : 2 - 4 (3 bit)
HIB_IM_EXTW : External Wake-Up Interrupt Mask
bits : 3 - 6 (4 bit)
HIB_IM_WC : External Write Complete/Capable Interrupt Mask
bits : 4 - 8 (5 bit)
HIB_IM_PADIOWK : Pad I/O Wake-Up Interrupt Mask
bits : 5 - 10 (6 bit)
HIB_IM_RSTWK : Reset Pad I/O Wake-Up Interrupt Mask
bits : 6 - 12 (7 bit)
HIB_IM_VDDFAIL : VDD Fail Interrupt Mask
bits : 7 - 14 (8 bit)
Hibernation Interrupt Mask
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_IM_RTCALT0 : RTC Alert 0 Interrupt Mask
bits : 0 - 0 (1 bit)
HIB_IM_LOWBAT : Low Battery Voltage Interrupt Mask
bits : 2 - 4 (3 bit)
HIB_IM_EXTW : External Wake-Up Interrupt Mask
bits : 3 - 6 (4 bit)
HIB_IM_WC : External Write Complete/Capable Interrupt Mask
bits : 4 - 8 (5 bit)
HIB_IM_PADIOWK : Pad I/O Wake-Up Interrupt Mask
bits : 5 - 10 (6 bit)
HIB_IM_RSTWK : Reset Pad I/O Wake-Up Interrupt Mask
bits : 6 - 12 (7 bit)
HIB_IM_VDDFAIL : VDD Fail Interrupt Mask
bits : 7 - 14 (8 bit)
Hibernation Raw Interrupt Status
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_RIS_RTCALT0 : RTC Alert 0 Raw Interrupt Status
bits : 0 - 0 (1 bit)
HIB_RIS_LOWBAT : Low Battery Voltage Raw Interrupt Status
bits : 2 - 4 (3 bit)
HIB_RIS_EXTW : External Wake-Up Raw Interrupt Status
bits : 3 - 6 (4 bit)
HIB_RIS_WC : Write Complete/Capable Raw Interrupt Status
bits : 4 - 8 (5 bit)
HIB_RIS_PADIOWK : Pad I/O Wake-Up Raw Interrupt Status
bits : 5 - 10 (6 bit)
HIB_RIS_RSTWK : Reset Pad I/O Wake-Up Raw Interrupt Status
bits : 6 - 12 (7 bit)
HIB_RIS_VDDFAIL : VDD Fail Raw Interrupt Status
bits : 7 - 14 (8 bit)
Hibernation Raw Interrupt Status
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_RIS_RTCALT0 : RTC Alert 0 Raw Interrupt Status
bits : 0 - 0 (1 bit)
HIB_RIS_LOWBAT : Low Battery Voltage Raw Interrupt Status
bits : 2 - 4 (3 bit)
HIB_RIS_EXTW : External Wake-Up Raw Interrupt Status
bits : 3 - 6 (4 bit)
HIB_RIS_WC : Write Complete/Capable Raw Interrupt Status
bits : 4 - 8 (5 bit)
HIB_RIS_PADIOWK : Pad I/O Wake-Up Raw Interrupt Status
bits : 5 - 10 (6 bit)
HIB_RIS_RSTWK : Reset Pad I/O Wake-Up Raw Interrupt Status
bits : 6 - 12 (7 bit)
HIB_RIS_VDDFAIL : VDD Fail Raw Interrupt Status
bits : 7 - 14 (8 bit)
Hibernation Masked Interrupt Status
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_MIS_RTCALT0 : RTC Alert 0 Masked Interrupt Status
bits : 0 - 0 (1 bit)
HIB_MIS_LOWBAT : Low Battery Voltage Masked Interrupt Status
bits : 2 - 4 (3 bit)
HIB_MIS_EXTW : External Wake-Up Masked Interrupt Status
bits : 3 - 6 (4 bit)
HIB_MIS_WC : Write Complete/Capable Masked Interrupt Status
bits : 4 - 8 (5 bit)
HIB_MIS_PADIOWK : Pad I/O Wake-Up Interrupt Mask
bits : 5 - 10 (6 bit)
HIB_MIS_RSTWK : Reset Pad I/O Wake-Up Interrupt Mask
bits : 6 - 12 (7 bit)
HIB_MIS_VDDFAIL : VDD Fail Interrupt Mask
bits : 7 - 14 (8 bit)
Hibernation Masked Interrupt Status
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_MIS_RTCALT0 : RTC Alert 0 Masked Interrupt Status
bits : 0 - 0 (1 bit)
HIB_MIS_LOWBAT : Low Battery Voltage Masked Interrupt Status
bits : 2 - 4 (3 bit)
HIB_MIS_EXTW : External Wake-Up Masked Interrupt Status
bits : 3 - 6 (4 bit)
HIB_MIS_WC : Write Complete/Capable Masked Interrupt Status
bits : 4 - 8 (5 bit)
HIB_MIS_PADIOWK : Pad I/O Wake-Up Interrupt Mask
bits : 5 - 10 (6 bit)
HIB_MIS_RSTWK : Reset Pad I/O Wake-Up Interrupt Mask
bits : 6 - 12 (7 bit)
HIB_MIS_VDDFAIL : VDD Fail Interrupt Mask
bits : 7 - 14 (8 bit)
Hibernation Interrupt Clear
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_IC_RTCALT0 : RTC Alert0 Masked Interrupt Clear
bits : 0 - 0 (1 bit)
HIB_IC_LOWBAT : Low Battery Voltage Interrupt Clear
bits : 2 - 4 (3 bit)
HIB_IC_EXTW : External Wake-Up Interrupt Clear
bits : 3 - 6 (4 bit)
HIB_IC_WC : Write Complete/Capable Interrupt Clear
bits : 4 - 8 (5 bit)
HIB_IC_PADIOWK : Pad I/O Wake-Up Interrupt Clear
bits : 5 - 10 (6 bit)
HIB_IC_RSTWK : Reset Pad I/O Wake-Up Interrupt Clear
bits : 6 - 12 (7 bit)
HIB_IC_VDDFAIL : VDD Fail Interrupt Clear
bits : 7 - 14 (8 bit)
Hibernation Interrupt Clear
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_IC_RTCALT0 : RTC Alert0 Masked Interrupt Clear
bits : 0 - 0 (1 bit)
HIB_IC_LOWBAT : Low Battery Voltage Interrupt Clear
bits : 2 - 4 (3 bit)
HIB_IC_EXTW : External Wake-Up Interrupt Clear
bits : 3 - 6 (4 bit)
HIB_IC_WC : Write Complete/Capable Interrupt Clear
bits : 4 - 8 (5 bit)
HIB_IC_PADIOWK : Pad I/O Wake-Up Interrupt Clear
bits : 5 - 10 (6 bit)
HIB_IC_RSTWK : Reset Pad I/O Wake-Up Interrupt Clear
bits : 6 - 12 (7 bit)
HIB_IC_VDDFAIL : VDD Fail Interrupt Clear
bits : 7 - 14 (8 bit)
Hibernation RTC Trim
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_RTCT_TRIM : RTC Trim Value
bits : 0 - 15 (16 bit)
Hibernation RTC Trim
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_RTCT_TRIM : RTC Trim Value
bits : 0 - 15 (16 bit)
Hibernation RTC Sub Seconds
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_RTCSS_RTCSSC : RTC Sub Seconds Count
bits : 0 - 14 (15 bit)
HIB_RTCSS_RTCSSM : RTC Sub Seconds Match
bits : 16 - 46 (31 bit)
Hibernation RTC Sub Seconds
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_RTCSS_RTCSSC : RTC Sub Seconds Count
bits : 0 - 14 (15 bit)
HIB_RTCSS_RTCSSM : RTC Sub Seconds Match
bits : 16 - 46 (31 bit)
Hibernation IO Configuration
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_IO_WUUNLK : I/O Wake Pad Configuration Enable
bits : 0 - 0 (1 bit)
HIB_IO_WURSTEN : Reset Wake Source Enable
bits : 4 - 8 (5 bit)
HIB_IO_IOWRC : I/O Write Complete
bits : 31 - 62 (32 bit)
Hibernation IO Configuration
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_IO_WUUNLK : I/O Wake Pad Configuration Enable
bits : 0 - 0 (1 bit)
HIB_IO_WURSTEN : Reset Wake Source Enable
bits : 4 - 8 (5 bit)
HIB_IO_IOWRC : I/O Write Complete
bits : 31 - 62 (32 bit)
Hibernation Data
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_DATA_RTD : Hibernation Module NV Data
bits : 0 - 31 (32 bit)
Hibernation Data
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_DATA_RTD : Hibernation Module NV Data
bits : 0 - 31 (32 bit)
Hibernation Calendar Control
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_CALCTL_CALEN : RTC Calendar/Counter Mode Select
bits : 0 - 0 (1 bit)
HIB_CALCTL_CAL24 : Calendar Mode
bits : 2 - 4 (3 bit)
Hibernation Calendar Control
address_offset : 0x300 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_CALCTL_CALEN : RTC Calendar/Counter Mode Select
bits : 0 - 0 (1 bit)
HIB_CALCTL_CAL24 : Calendar Mode
bits : 2 - 4 (3 bit)
Hibernation Calendar 0
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_CAL0_SEC : Seconds
bits : 0 - 5 (6 bit)
HIB_CAL0_MIN : Minutes
bits : 8 - 21 (14 bit)
HIB_CAL0_HR : Hours
bits : 16 - 36 (21 bit)
HIB_CAL0_AMPM : AM/PM Designation
bits : 22 - 44 (23 bit)
HIB_CAL0_VALID : Valid Calendar Load
bits : 31 - 62 (32 bit)
Hibernation Calendar 0
address_offset : 0x310 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_CAL0_SEC : Seconds
bits : 0 - 5 (6 bit)
HIB_CAL0_MIN : Minutes
bits : 8 - 21 (14 bit)
HIB_CAL0_HR : Hours
bits : 16 - 36 (21 bit)
HIB_CAL0_AMPM : AM/PM Designation
bits : 22 - 44 (23 bit)
HIB_CAL0_VALID : Valid Calendar Load
bits : 31 - 62 (32 bit)
Hibernation Calendar 1
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_CAL1_DOM : Day of Month
bits : 0 - 4 (5 bit)
HIB_CAL1_MON : Month
bits : 8 - 19 (12 bit)
HIB_CAL1_YEAR : Year Value
bits : 16 - 38 (23 bit)
HIB_CAL1_DOW : Day of Week
bits : 24 - 50 (27 bit)
HIB_CAL1_VALID : Valid Calendar Load
bits : 31 - 62 (32 bit)
Hibernation Calendar 1
address_offset : 0x314 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_CAL1_DOM : Day of Month
bits : 0 - 4 (5 bit)
HIB_CAL1_MON : Month
bits : 8 - 19 (12 bit)
HIB_CAL1_YEAR : Year Value
bits : 16 - 38 (23 bit)
HIB_CAL1_DOW : Day of Week
bits : 24 - 50 (27 bit)
HIB_CAL1_VALID : Valid Calendar Load
bits : 31 - 62 (32 bit)
Hibernation Calendar Load 0
address_offset : 0x320 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
HIB_CALLD0_SEC : Seconds
bits : 0 - 5 (6 bit)
access : write-only
HIB_CALLD0_MIN : Minutes
bits : 8 - 21 (14 bit)
access : write-only
HIB_CALLD0_HR : Hours
bits : 16 - 36 (21 bit)
access : write-only
HIB_CALLD0_AMPM : AM/PM Designation
bits : 22 - 44 (23 bit)
access : write-only
Hibernation Calendar Load 0
address_offset : 0x320 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
HIB_CALLD0_SEC : Seconds
bits : 0 - 5 (6 bit)
access : write-only
HIB_CALLD0_MIN : Minutes
bits : 8 - 21 (14 bit)
access : write-only
HIB_CALLD0_HR : Hours
bits : 16 - 36 (21 bit)
access : write-only
HIB_CALLD0_AMPM : AM/PM Designation
bits : 22 - 44 (23 bit)
access : write-only
Hibernation Calendar Load
address_offset : 0x324 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
HIB_CALLD1_DOM : Day of Month
bits : 0 - 4 (5 bit)
access : write-only
HIB_CALLD1_MON : Month
bits : 8 - 19 (12 bit)
access : write-only
HIB_CALLD1_YEAR : Year Value
bits : 16 - 38 (23 bit)
access : write-only
HIB_CALLD1_DOW : Day of Week
bits : 24 - 50 (27 bit)
access : write-only
Hibernation Calendar Load
address_offset : 0x324 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
HIB_CALLD1_DOM : Day of Month
bits : 0 - 4 (5 bit)
access : write-only
HIB_CALLD1_MON : Month
bits : 8 - 19 (12 bit)
access : write-only
HIB_CALLD1_YEAR : Year Value
bits : 16 - 38 (23 bit)
access : write-only
HIB_CALLD1_DOW : Day of Week
bits : 24 - 50 (27 bit)
access : write-only
Hibernation Calendar Match 0
address_offset : 0x330 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_CALM0_SEC : Seconds
bits : 0 - 5 (6 bit)
HIB_CALM0_MIN : Minutes
bits : 8 - 21 (14 bit)
HIB_CALM0_HR : Hours
bits : 16 - 36 (21 bit)
HIB_CALM0_AMPM : AM/PM Designation
bits : 22 - 44 (23 bit)
Hibernation Calendar Match 0
address_offset : 0x330 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_CALM0_SEC : Seconds
bits : 0 - 5 (6 bit)
HIB_CALM0_MIN : Minutes
bits : 8 - 21 (14 bit)
HIB_CALM0_HR : Hours
bits : 16 - 36 (21 bit)
HIB_CALM0_AMPM : AM/PM Designation
bits : 22 - 44 (23 bit)
Hibernation Calendar Match 1
address_offset : 0x334 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_CALM1_DOM : Day of Month
bits : 0 - 4 (5 bit)
Hibernation Calendar Match 1
address_offset : 0x334 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_CALM1_DOM : Day of Month
bits : 0 - 4 (5 bit)
Hibernation Lock
address_offset : 0x360 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_LOCK_HIBLOCK : HIbernate Lock
bits : 0 - 31 (32 bit)
Hibernation Lock
address_offset : 0x360 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_LOCK_HIBLOCK : HIbernate Lock
bits : 0 - 31 (32 bit)
Hibernation RTC Match 0
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_RTCM0 : RTC Match 0
bits : 0 - 31 (32 bit)
Hibernation RTC Match 0
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_RTCM0 : RTC Match 0
bits : 0 - 31 (32 bit)
HIB Tamper Control
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPCTL_TPEN : Tamper Module Enable
bits : 0 - 0 (1 bit)
HIB_TPCTL_TPCLR : Tamper Event Clear
bits : 4 - 8 (5 bit)
HIB_TPCTL_MEMCLR : HIB Memory Clear on Tamper Event
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : HIB_TPCTL_MEMCLR_NONE
Do not Clear HIB memory on tamper event
0x1 : HIB_TPCTL_MEMCLR_LOW32
Clear Lower 32 Bytes of HIB memory on tamper event
0x2 : HIB_TPCTL_MEMCLR_HIGH32
Clear upper 32 Bytes of HIB memory on tamper event
0x3 : HIB_TPCTL_MEMCLR_ALL
Clear all HIB memory on tamper event
End of enumeration elements list.
HIB_TPCTL_WAKE : Wake from Hibernate on a Tamper Event
bits : 11 - 22 (12 bit)
HIB Tamper Control
address_offset : 0x400 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPCTL_TPEN : Tamper Module Enable
bits : 0 - 0 (1 bit)
HIB_TPCTL_TPCLR : Tamper Event Clear
bits : 4 - 8 (5 bit)
HIB_TPCTL_MEMCLR : HIB Memory Clear on Tamper Event
bits : 8 - 17 (10 bit)
Enumeration:
0x0 : HIB_TPCTL_MEMCLR_NONE
Do not Clear HIB memory on tamper event
0x1 : HIB_TPCTL_MEMCLR_LOW32
Clear Lower 32 Bytes of HIB memory on tamper event
0x2 : HIB_TPCTL_MEMCLR_HIGH32
Clear upper 32 Bytes of HIB memory on tamper event
0x3 : HIB_TPCTL_MEMCLR_ALL
Clear all HIB memory on tamper event
End of enumeration elements list.
HIB_TPCTL_WAKE : Wake from Hibernate on a Tamper Event
bits : 11 - 22 (12 bit)
HIB Tamper Status
address_offset : 0x404 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPSTAT_XOSCFAIL : External Oscillator Failure
bits : 0 - 0 (1 bit)
HIB_TPSTAT_XOSCST : External Oscillator Status
bits : 1 - 2 (2 bit)
HIB_TPSTAT_STATE : Tamper Module Status
bits : 2 - 5 (4 bit)
Enumeration:
0x0 : HIB_TPSTAT_STATE_DISABLED
Tamper disabled
0x1 : HIB_TPSTAT_STATE_CONFIGED
Tamper configured
0x2 : HIB_TPSTAT_STATE_ERROR
Tamper pin event occurred
End of enumeration elements list.
HIB Tamper Status
address_offset : 0x404 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPSTAT_XOSCFAIL : External Oscillator Failure
bits : 0 - 0 (1 bit)
HIB_TPSTAT_XOSCST : External Oscillator Status
bits : 1 - 2 (2 bit)
HIB_TPSTAT_STATE : Tamper Module Status
bits : 2 - 5 (4 bit)
Enumeration:
0x0 : HIB_TPSTAT_STATE_DISABLED
Tamper disabled
0x1 : HIB_TPSTAT_STATE_CONFIGED
Tamper configured
0x2 : HIB_TPSTAT_STATE_ERROR
Tamper pin event occurred
End of enumeration elements list.
HIB Tamper I/O Control
address_offset : 0x410 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPIO_EN0 : TMPR0 Enable
bits : 0 - 0 (1 bit)
HIB_TPIO_LEV0 : TMPR0 Trigger Level
bits : 1 - 2 (2 bit)
HIB_TPIO_PUEN0 : TMPR0 Internal Weak Pull-up Enable
bits : 2 - 4 (3 bit)
HIB_TPIO_GFLTR0 : TMPR0 Glitch Filtering
bits : 3 - 6 (4 bit)
HIB_TPIO_EN1 : TMPR1Enable
bits : 8 - 16 (9 bit)
HIB_TPIO_LEV1 : TMPR1 Trigger Level
bits : 9 - 18 (10 bit)
HIB_TPIO_PUEN1 : TMPR1 Internal Weak Pull-up Enable
bits : 10 - 20 (11 bit)
HIB_TPIO_GFLTR1 : TMPR1 Glitch Filtering
bits : 11 - 22 (12 bit)
HIB_TPIO_EN2 : TMPR2 Enable
bits : 16 - 32 (17 bit)
HIB_TPIO_LEV2 : TMPR2 Trigger Level
bits : 17 - 34 (18 bit)
HIB_TPIO_PUEN2 : TMPR2 Internal Weak Pull-up Enable
bits : 18 - 36 (19 bit)
HIB_TPIO_GFLTR2 : TMPR2 Glitch Filtering
bits : 19 - 38 (20 bit)
HIB_TPIO_EN3 : TMPR3 Enable
bits : 24 - 48 (25 bit)
HIB_TPIO_LEV3 : TMPR3 Trigger Level
bits : 25 - 50 (26 bit)
HIB_TPIO_PUEN3 : TMPR3 Internal Weak Pull-up Enable
bits : 26 - 52 (27 bit)
HIB_TPIO_GFLTR3 : TMPR3 Glitch Filtering
bits : 27 - 54 (28 bit)
HIB Tamper I/O Control
address_offset : 0x410 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPIO_EN0 : TMPR0 Enable
bits : 0 - 0 (1 bit)
HIB_TPIO_LEV0 : TMPR0 Trigger Level
bits : 1 - 2 (2 bit)
HIB_TPIO_PUEN0 : TMPR0 Internal Weak Pull-up Enable
bits : 2 - 4 (3 bit)
HIB_TPIO_GFLTR0 : TMPR0 Glitch Filtering
bits : 3 - 6 (4 bit)
HIB_TPIO_EN1 : TMPR1Enable
bits : 8 - 16 (9 bit)
HIB_TPIO_LEV1 : TMPR1 Trigger Level
bits : 9 - 18 (10 bit)
HIB_TPIO_PUEN1 : TMPR1 Internal Weak Pull-up Enable
bits : 10 - 20 (11 bit)
HIB_TPIO_GFLTR1 : TMPR1 Glitch Filtering
bits : 11 - 22 (12 bit)
HIB_TPIO_EN2 : TMPR2 Enable
bits : 16 - 32 (17 bit)
HIB_TPIO_LEV2 : TMPR2 Trigger Level
bits : 17 - 34 (18 bit)
HIB_TPIO_PUEN2 : TMPR2 Internal Weak Pull-up Enable
bits : 18 - 36 (19 bit)
HIB_TPIO_GFLTR2 : TMPR2 Glitch Filtering
bits : 19 - 38 (20 bit)
HIB_TPIO_EN3 : TMPR3 Enable
bits : 24 - 48 (25 bit)
HIB_TPIO_LEV3 : TMPR3 Trigger Level
bits : 25 - 50 (26 bit)
HIB_TPIO_PUEN3 : TMPR3 Internal Weak Pull-up Enable
bits : 26 - 52 (27 bit)
HIB_TPIO_GFLTR3 : TMPR3 Glitch Filtering
bits : 27 - 54 (28 bit)
HIB Tamper Log 0
address_offset : 0x4E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPLOG0_TIME : Tamper Log Calendar Information
bits : 0 - 31 (32 bit)
HIB Tamper Log 0
address_offset : 0x4E0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPLOG0_TIME : Tamper Log Calendar Information
bits : 0 - 31 (32 bit)
HIB Tamper Log 1
address_offset : 0x4E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPLOG1_TRIG0 : Status of TMPR[0] Trigger
bits : 0 - 0 (1 bit)
HIB_TPLOG1_TRIG1 : Status of TMPR[1] Trigger
bits : 1 - 2 (2 bit)
HIB_TPLOG1_TRIG2 : Status of TMPR[2] Trigger
bits : 2 - 4 (3 bit)
HIB_TPLOG1_TRIG3 : Status of TMPR[3] Trigger
bits : 3 - 6 (4 bit)
HIB_TPLOG1_XOSC : Status of external 32
bits : 16 - 32 (17 bit)
HIB Tamper Log 1
address_offset : 0x4E4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPLOG1_TRIG0 : Status of TMPR[0] Trigger
bits : 0 - 0 (1 bit)
HIB_TPLOG1_TRIG1 : Status of TMPR[1] Trigger
bits : 1 - 2 (2 bit)
HIB_TPLOG1_TRIG2 : Status of TMPR[2] Trigger
bits : 2 - 4 (3 bit)
HIB_TPLOG1_TRIG3 : Status of TMPR[3] Trigger
bits : 3 - 6 (4 bit)
HIB_TPLOG1_XOSC : Status of external 32
bits : 16 - 32 (17 bit)
HIB Tamper Log 2
address_offset : 0x4E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPLOG2_TIME : Tamper Log Calendar Information
bits : 0 - 31 (32 bit)
HIB Tamper Log 2
address_offset : 0x4E8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPLOG2_TIME : Tamper Log Calendar Information
bits : 0 - 31 (32 bit)
HIB Tamper Log 3
address_offset : 0x4EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPLOG3_TRIG0 : Status of TMPR[0] Trigger
bits : 0 - 0 (1 bit)
HIB_TPLOG3_TRIG1 : Status of TMPR[1] Trigger
bits : 1 - 2 (2 bit)
HIB_TPLOG3_TRIG2 : Status of TMPR[2] Trigger
bits : 2 - 4 (3 bit)
HIB_TPLOG3_TRIG3 : Status of TMPR[3] Trigger
bits : 3 - 6 (4 bit)
HIB_TPLOG3_XOSC : Status of external 32
bits : 16 - 32 (17 bit)
HIB Tamper Log 3
address_offset : 0x4EC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPLOG3_TRIG0 : Status of TMPR[0] Trigger
bits : 0 - 0 (1 bit)
HIB_TPLOG3_TRIG1 : Status of TMPR[1] Trigger
bits : 1 - 2 (2 bit)
HIB_TPLOG3_TRIG2 : Status of TMPR[2] Trigger
bits : 2 - 4 (3 bit)
HIB_TPLOG3_TRIG3 : Status of TMPR[3] Trigger
bits : 3 - 6 (4 bit)
HIB_TPLOG3_XOSC : Status of external 32
bits : 16 - 32 (17 bit)
HIB Tamper Log 4
address_offset : 0x4F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPLOG4_TIME : Tamper Log Calendar Information
bits : 0 - 31 (32 bit)
HIB Tamper Log 4
address_offset : 0x4F0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPLOG4_TIME : Tamper Log Calendar Information
bits : 0 - 31 (32 bit)
HIB Tamper Log 5
address_offset : 0x4F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPLOG5_TRIG0 : Status of TMPR[0] Trigger
bits : 0 - 0 (1 bit)
HIB_TPLOG5_TRIG1 : Status of TMPR[1] Trigger
bits : 1 - 2 (2 bit)
HIB_TPLOG5_TRIG2 : Status of TMPR[2] Trigger
bits : 2 - 4 (3 bit)
HIB_TPLOG5_TRIG3 : Status of TMPR[3] Trigger
bits : 3 - 6 (4 bit)
HIB_TPLOG5_XOSC : Status of external 32
bits : 16 - 32 (17 bit)
HIB Tamper Log 5
address_offset : 0x4F4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPLOG5_TRIG0 : Status of TMPR[0] Trigger
bits : 0 - 0 (1 bit)
HIB_TPLOG5_TRIG1 : Status of TMPR[1] Trigger
bits : 1 - 2 (2 bit)
HIB_TPLOG5_TRIG2 : Status of TMPR[2] Trigger
bits : 2 - 4 (3 bit)
HIB_TPLOG5_TRIG3 : Status of TMPR[3] Trigger
bits : 3 - 6 (4 bit)
HIB_TPLOG5_XOSC : Status of external 32
bits : 16 - 32 (17 bit)
HIB Tamper Log 6
address_offset : 0x4F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPLOG6_TIME : Tamper Log Calendar Information
bits : 0 - 31 (32 bit)
HIB Tamper Log 6
address_offset : 0x4F8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPLOG6_TIME : Tamper Log Calendar Information
bits : 0 - 31 (32 bit)
HIB Tamper Log 7
address_offset : 0x4FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPLOG7_TRIG0 : Status of TMPR[0] Trigger
bits : 0 - 0 (1 bit)
HIB_TPLOG7_TRIG1 : Status of TMPR[1] Trigger
bits : 1 - 2 (2 bit)
HIB_TPLOG7_TRIG2 : Status of TMPR[2] Trigger
bits : 2 - 4 (3 bit)
HIB_TPLOG7_TRIG3 : Status of TMPR[3] Trigger
bits : 3 - 6 (4 bit)
HIB_TPLOG7_XOSC : Status of external 32
bits : 16 - 32 (17 bit)
HIB Tamper Log 7
address_offset : 0x4FC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_TPLOG7_TRIG0 : Status of TMPR[0] Trigger
bits : 0 - 0 (1 bit)
HIB_TPLOG7_TRIG1 : Status of TMPR[1] Trigger
bits : 1 - 2 (2 bit)
HIB_TPLOG7_TRIG2 : Status of TMPR[2] Trigger
bits : 2 - 4 (3 bit)
HIB_TPLOG7_TRIG3 : Status of TMPR[3] Trigger
bits : 3 - 6 (4 bit)
HIB_TPLOG7_XOSC : Status of external 32
bits : 16 - 32 (17 bit)
Hibernation RTC Load
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_RTCLD : RTC Load
bits : 0 - 31 (32 bit)
Hibernation RTC Load
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_RTCLD : RTC Load
bits : 0 - 31 (32 bit)
Hibernation Peripheral Properties
address_offset : 0xFC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_PP_WAKENC : Wake Pin Presence
bits : 0 - 0 (1 bit)
HIB_PP_TAMPER : Tamper Pin Presence
bits : 1 - 2 (2 bit)
Hibernation Peripheral Properties
address_offset : 0xFC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_PP_WAKENC : Wake Pin Presence
bits : 0 - 0 (1 bit)
HIB_PP_TAMPER : Tamper Pin Presence
bits : 1 - 2 (2 bit)
Hibernation Clock Control
address_offset : 0xFC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_CC_SYSCLKEN : RTCOSC to System Clock Enable
bits : 0 - 0 (1 bit)
Hibernation Clock Control
address_offset : 0xFC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_CC_SYSCLKEN : RTCOSC to System Clock Enable
bits : 0 - 0 (1 bit)
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