\n
address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected
8-bit Counter Mode - - Control A
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only
ENABLE : Enable
bits : 1 - 1 (1 bit)
MODE : TC Mode
bits : 2 - 3 (2 bit)
Enumeration: MODESelect
0x0 : COUNT16
Counter in 16-bit mode
0x1 : COUNT8
Counter in 8-bit mode
0x2 : COUNT32
Counter in 32-bit mode
End of enumeration elements list.
WAVEGEN : Waveform Generation Operation
bits : 5 - 6 (2 bit)
Enumeration: WAVEGENSelect
0x0 : NFRQ
None
0x1 : MFRQ
None
0x2 : NPWM
None
0x3 : MPWM
None
End of enumeration elements list.
PRESCALER : Prescaler
bits : 8 - 10 (3 bit)
Enumeration: PRESCALERSelect
0x0 : DIV1
Prescaler: GCLK_TC
0x1 : DIV2
Prescaler: GCLK_TC/2
0x2 : DIV4
Prescaler: GCLK_TC/4
0x3 : DIV8
Prescaler: GCLK_TC/8
0x4 : DIV16
Prescaler: GCLK_TC/16
0x5 : DIV64
Prescaler: GCLK_TC/64
0x6 : DIV256
Prescaler: GCLK_TC/256
0x7 : DIV1024
Prescaler: GCLK_TC/1024
End of enumeration elements list.
RUNSTDBY : Run in Standby
bits : 11 - 11 (1 bit)
PRESCSYNC : Prescaler and Counter Synchronization
bits : 12 - 13 (2 bit)
Enumeration: PRESCSYNCSelect
0x0 : GCLK
Reload or reset the counter on next generic clock
0x1 : PRESC
Reload or reset the counter on next prescaler clock
0x2 : RESYNC
Reload or reset the counter on next generic clock. Reset the prescaler counter
End of enumeration elements list.
16-bit Counter Mode - - Control A
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only
ENABLE : Enable
bits : 1 - 1 (1 bit)
MODE : TC Mode
bits : 2 - 3 (2 bit)
Enumeration: MODESelect
0x0 : COUNT16
Counter in 16-bit mode
0x1 : COUNT8
Counter in 8-bit mode
0x2 : COUNT32
Counter in 32-bit mode
End of enumeration elements list.
WAVEGEN : Waveform Generation Operation
bits : 5 - 6 (2 bit)
Enumeration: WAVEGENSelect
0x0 : NFRQ
None
0x1 : MFRQ
None
0x2 : NPWM
None
0x3 : MPWM
None
End of enumeration elements list.
PRESCALER : Prescaler
bits : 8 - 10 (3 bit)
Enumeration: PRESCALERSelect
0x0 : DIV1
Prescaler: GCLK_TC
0x1 : DIV2
Prescaler: GCLK_TC/2
0x2 : DIV4
Prescaler: GCLK_TC/4
0x3 : DIV8
Prescaler: GCLK_TC/8
0x4 : DIV16
Prescaler: GCLK_TC/16
0x5 : DIV64
Prescaler: GCLK_TC/64
0x6 : DIV256
Prescaler: GCLK_TC/256
0x7 : DIV1024
Prescaler: GCLK_TC/1024
End of enumeration elements list.
RUNSTDBY : Run in Standby
bits : 11 - 11 (1 bit)
PRESCSYNC : Prescaler and Counter Synchronization
bits : 12 - 13 (2 bit)
Enumeration: PRESCSYNCSelect
0x0 : GCLK
Reload or reset the counter on next generic clock
0x1 : PRESC
Reload or reset the counter on next prescaler clock
0x2 : RESYNC
Reload or reset the counter on next generic clock. Reset the prescaler counter
End of enumeration elements list.
32-bit Counter Mode - - Control A
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only
ENABLE : Enable
bits : 1 - 1 (1 bit)
MODE : TC Mode
bits : 2 - 3 (2 bit)
Enumeration: MODESelect
0x0 : COUNT16
Counter in 16-bit mode
0x1 : COUNT8
Counter in 8-bit mode
0x2 : COUNT32
Counter in 32-bit mode
End of enumeration elements list.
WAVEGEN : Waveform Generation Operation
bits : 5 - 6 (2 bit)
Enumeration: WAVEGENSelect
0x0 : NFRQ
None
0x1 : MFRQ
None
0x2 : NPWM
None
0x3 : MPWM
None
End of enumeration elements list.
PRESCALER : Prescaler
bits : 8 - 10 (3 bit)
Enumeration: PRESCALERSelect
0x0 : DIV1
Prescaler: GCLK_TC
0x1 : DIV2
Prescaler: GCLK_TC/2
0x2 : DIV4
Prescaler: GCLK_TC/4
0x3 : DIV8
Prescaler: GCLK_TC/8
0x4 : DIV16
Prescaler: GCLK_TC/16
0x5 : DIV64
Prescaler: GCLK_TC/64
0x6 : DIV256
Prescaler: GCLK_TC/256
0x7 : DIV1024
Prescaler: GCLK_TC/1024
End of enumeration elements list.
RUNSTDBY : Run in Standby
bits : 11 - 11 (1 bit)
PRESCSYNC : Prescaler and Counter Synchronization
bits : 12 - 13 (2 bit)
Enumeration: PRESCSYNCSelect
0x0 : GCLK
Reload or reset the counter on next generic clock
0x1 : PRESC
Reload or reset the counter on next prescaler clock
0x2 : RESYNC
Reload or reset the counter on next generic clock. Reset the prescaler counter
End of enumeration elements list.
Control A
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only
ENABLE : Enable
bits : 1 - 1 (1 bit)
MODE : TC Mode
bits : 2 - 3 (2 bit)
Enumeration: MODESelect
0x0 : COUNT16
Counter in 16-bit mode
0x1 : COUNT8
Counter in 8-bit mode
0x2 : COUNT32
Counter in 32-bit mode
End of enumeration elements list.
WAVEGEN : Waveform Generation Operation
bits : 5 - 6 (2 bit)
Enumeration: WAVEGENSelect
0x0 : NFRQ
0x1 : MFRQ
0x2 : NPWM
0x3 : MPWM
End of enumeration elements list.
PRESCALER : Prescaler
bits : 8 - 10 (3 bit)
Enumeration: PRESCALERSelect
0x0 : DIV1
Prescaler: GCLK_TC
0x1 : DIV2
Prescaler: GCLK_TC/2
0x2 : DIV4
Prescaler: GCLK_TC/4
0x3 : DIV8
Prescaler: GCLK_TC/8
0x4 : DIV16
Prescaler: GCLK_TC/16
0x5 : DIV64
Prescaler: GCLK_TC/64
0x6 : DIV256
Prescaler: GCLK_TC/256
0x7 : DIV1024
Prescaler: GCLK_TC/1024
End of enumeration elements list.
RUNSTDBY : Run in Standby
bits : 11 - 11 (1 bit)
PRESCSYNC : Prescaler and Counter Synchronization
bits : 12 - 13 (2 bit)
Enumeration: PRESCSYNCSelect
0x0 : GCLK
Reload or reset the counter on next generic clock
0x1 : PRESC
Reload or reset the counter on next prescaler clock
0x2 : RESYNC
Reload or reset the counter on next generic clock. Reset the prescaler counter
End of enumeration elements list.
8-bit Counter Mode - - COUNT8 Counter Value
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Counter Value
bits : 0 - 7 (8 bit)
16-bit Counter Mode - - COUNT16 Counter Value
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Count Value
bits : 0 - 15 (16 bit)
32-bit Counter Mode - - COUNT32 Counter Value
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Count Value
bits : 0 - 31 (32 bit)
COUNT16 Counter Value
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Count Value
bits : 0 - 31 (32 bit)
8-bit Counter Mode - - COUNT8 Period Value
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PER : Period Value
bits : 0 - 7 (8 bit)
COUNT8 Period Value
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PER : Period Value
bits : 0 - 7 (8 bit)
COUNT16 Compare/Capture
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Compare/Capture Value
bits : 0 - 31 (32 bit)
COUNT16 Compare/Capture
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Compare/Capture Value
bits : 0 - 31 (32 bit)
8-bit Counter Mode - - Read Request
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address
bits : 0 - 4 (5 bit)
RCONT : Read Continuously
bits : 14 - 14 (1 bit)
RREQ : Read Request
bits : 15 - 15 (1 bit)
16-bit Counter Mode - - Read Request
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address
bits : 0 - 4 (5 bit)
RCONT : Read Continuously
bits : 14 - 14 (1 bit)
RREQ : Read Request
bits : 15 - 15 (1 bit)
32-bit Counter Mode - - Read Request
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address
bits : 0 - 4 (5 bit)
RCONT : Read Continuously
bits : 14 - 14 (1 bit)
RREQ : Read Request
bits : 15 - 15 (1 bit)
Read Request
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address
bits : 0 - 4 (5 bit)
RCONT : Read Continuously
bits : 14 - 14 (1 bit)
RREQ : Read Request
bits : 15 - 15 (1 bit)
8-bit Counter Mode - - COUNT8 Compare/Capture
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Compare/Capture Value
bits : 0 - 7 (8 bit)
16-bit Counter Mode - - COUNT16 Compare/Capture
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Compare/Capture Value
bits : 0 - 15 (16 bit)
32-bit Counter Mode - - COUNT32 Compare/Capture
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Compare/Capture Value
bits : 0 - 31 (32 bit)
8-bit Counter Mode - - Control B Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Counter Direction
bits : 0 - 0 (1 bit)
ONESHOT : One-Shot
bits : 2 - 2 (1 bit)
CMD : Command
bits : 6 - 7 (2 bit)
Enumeration: CMDSelect
0x0 : NONE
No action
0x1 : RETRIGGER
Force a start, restart or retrigger
0x2 : STOP
Force a stop
End of enumeration elements list.
16-bit Counter Mode - - Control B Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Counter Direction
bits : 0 - 0 (1 bit)
ONESHOT : One-Shot
bits : 2 - 2 (1 bit)
CMD : Command
bits : 6 - 7 (2 bit)
Enumeration: CMDSelect
0x0 : NONE
No action
0x1 : RETRIGGER
Force a start, restart or retrigger
0x2 : STOP
Force a stop
End of enumeration elements list.
32-bit Counter Mode - - Control B Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Counter Direction
bits : 0 - 0 (1 bit)
ONESHOT : One-Shot
bits : 2 - 2 (1 bit)
CMD : Command
bits : 6 - 7 (2 bit)
Enumeration: CMDSelect
0x0 : NONE
No action
0x1 : RETRIGGER
Force a start, restart or retrigger
0x2 : STOP
Force a stop
End of enumeration elements list.
Control B Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Counter Direction
bits : 0 - 0 (1 bit)
ONESHOT : One-Shot
bits : 2 - 2 (1 bit)
CMD : Command
bits : 6 - 7 (2 bit)
Enumeration: CMDSelect
0x0 : NONE
No action
0x1 : RETRIGGER
Force a start, restart or retrigger
0x2 : STOP
Force a stop
End of enumeration elements list.
8-bit Counter Mode - - COUNT8 Compare/Capture
address_offset : 0x49 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Compare/Capture Value
bits : 0 - 7 (8 bit)
16-bit Counter Mode - - COUNT16 Compare/Capture
address_offset : 0x4A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Compare/Capture Value
bits : 0 - 15 (16 bit)
32-bit Counter Mode - - COUNT32 Compare/Capture
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Compare/Capture Value
bits : 0 - 31 (32 bit)
8-bit Counter Mode - - Control B Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Counter Direction
bits : 0 - 0 (1 bit)
ONESHOT : One-Shot
bits : 2 - 2 (1 bit)
CMD : Command
bits : 6 - 7 (2 bit)
Enumeration: CMDSelect
0x0 : NONE
No action
0x1 : RETRIGGER
Force a start, restart or retrigger
0x2 : STOP
Force a stop
End of enumeration elements list.
16-bit Counter Mode - - Control B Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Counter Direction
bits : 0 - 0 (1 bit)
ONESHOT : One-Shot
bits : 2 - 2 (1 bit)
CMD : Command
bits : 6 - 7 (2 bit)
Enumeration: CMDSelect
0x0 : NONE
No action
0x1 : RETRIGGER
Force a start, restart or retrigger
0x2 : STOP
Force a stop
End of enumeration elements list.
32-bit Counter Mode - - Control B Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Counter Direction
bits : 0 - 0 (1 bit)
ONESHOT : One-Shot
bits : 2 - 2 (1 bit)
CMD : Command
bits : 6 - 7 (2 bit)
Enumeration: CMDSelect
0x0 : NONE
No action
0x1 : RETRIGGER
Force a start, restart or retrigger
0x2 : STOP
Force a stop
End of enumeration elements list.
Control B Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Counter Direction
bits : 0 - 0 (1 bit)
ONESHOT : One-Shot
bits : 2 - 2 (1 bit)
CMD : Command
bits : 6 - 7 (2 bit)
Enumeration: CMDSelect
0x0 : NONE
No action
0x1 : RETRIGGER
Force a start, restart or retrigger
0x2 : STOP
Force a stop
End of enumeration elements list.
8-bit Counter Mode - - Control C
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INVEN0 : Output Waveform 0 Invert Enable
bits : 0 - 0 (1 bit)
INVEN1 : Output Waveform 1 Invert Enable
bits : 1 - 1 (1 bit)
CPTEN0 : Capture Channel 0 Enable
bits : 4 - 4 (1 bit)
CPTEN1 : Capture Channel 1 Enable
bits : 5 - 5 (1 bit)
16-bit Counter Mode - - Control C
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INVEN0 : Output Waveform 0 Invert Enable
bits : 0 - 0 (1 bit)
INVEN1 : Output Waveform 1 Invert Enable
bits : 1 - 1 (1 bit)
CPTEN0 : Capture Channel 0 Enable
bits : 4 - 4 (1 bit)
CPTEN1 : Capture Channel 1 Enable
bits : 5 - 5 (1 bit)
32-bit Counter Mode - - Control C
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INVEN0 : Output Waveform 0 Invert Enable
bits : 0 - 0 (1 bit)
INVEN1 : Output Waveform 1 Invert Enable
bits : 1 - 1 (1 bit)
CPTEN0 : Capture Channel 0 Enable
bits : 4 - 4 (1 bit)
CPTEN1 : Capture Channel 1 Enable
bits : 5 - 5 (1 bit)
Control C
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INVEN0 : Output Waveform 0 Invert Enable
bits : 0 - 0 (1 bit)
INVEN1 : Output Waveform 1 Invert Enable
bits : 1 - 1 (1 bit)
CPTEN0 : Capture Channel 0 Enable
bits : 4 - 4 (1 bit)
CPTEN1 : Capture Channel 1 Enable
bits : 5 - 5 (1 bit)
8-bit Counter Mode - - Debug Control
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGRUN : Debug Run Mode
bits : 0 - 0 (1 bit)
16-bit Counter Mode - - Debug Control
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGRUN : Debug Run Mode
bits : 0 - 0 (1 bit)
32-bit Counter Mode - - Debug Control
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGRUN : Debug Run Mode
bits : 0 - 0 (1 bit)
Debug Control
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGRUN : Debug Run Mode
bits : 0 - 0 (1 bit)
8-bit Counter Mode - - Event Control
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Event Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0x0 : OFF
Event action disabled
0x1 : RETRIGGER
Start, restart or retrigger TC on event
0x2 : COUNT
Count on event
0x3 : START
Start TC on event
0x5 : PPW
Period captured in CC0, pulse width in CC1
0x6 : PWP
Period captured in CC1, pulse width in CC0
End of enumeration elements list.
TCINV : TC Inverted Event Input
bits : 4 - 4 (1 bit)
TCEI : TC Event Input
bits : 5 - 5 (1 bit)
OVFEO : Overflow/Underflow Event Output Enable
bits : 8 - 8 (1 bit)
MCEO0 : Match or Capture Channel 0 Event Output Enable
bits : 12 - 12 (1 bit)
MCEO1 : Match or Capture Channel 1 Event Output Enable
bits : 13 - 13 (1 bit)
16-bit Counter Mode - - Event Control
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Event Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0x0 : OFF
Event action disabled
0x1 : RETRIGGER
Start, restart or retrigger TC on event
0x2 : COUNT
Count on event
0x3 : START
Start TC on event
0x5 : PPW
Period captured in CC0, pulse width in CC1
0x6 : PWP
Period captured in CC1, pulse width in CC0
End of enumeration elements list.
TCINV : TC Inverted Event Input
bits : 4 - 4 (1 bit)
TCEI : TC Event Input
bits : 5 - 5 (1 bit)
OVFEO : Overflow/Underflow Event Output Enable
bits : 8 - 8 (1 bit)
MCEO0 : Match or Capture Channel 0 Event Output Enable
bits : 12 - 12 (1 bit)
MCEO1 : Match or Capture Channel 1 Event Output Enable
bits : 13 - 13 (1 bit)
32-bit Counter Mode - - Event Control
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Event Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0x0 : OFF
Event action disabled
0x1 : RETRIGGER
Start, restart or retrigger TC on event
0x2 : COUNT
Count on event
0x3 : START
Start TC on event
0x5 : PPW
Period captured in CC0, pulse width in CC1
0x6 : PWP
Period captured in CC1, pulse width in CC0
End of enumeration elements list.
TCINV : TC Inverted Event Input
bits : 4 - 4 (1 bit)
TCEI : TC Event Input
bits : 5 - 5 (1 bit)
OVFEO : Overflow/Underflow Event Output Enable
bits : 8 - 8 (1 bit)
MCEO0 : Match or Capture Channel 0 Event Output Enable
bits : 12 - 12 (1 bit)
MCEO1 : Match or Capture Channel 1 Event Output Enable
bits : 13 - 13 (1 bit)
Event Control
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Event Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0x0 : OFF
Event action disabled
0x1 : RETRIGGER
Start, restart or retrigger TC on event
0x2 : COUNT
Count on event
0x3 : START
Start TC on event
0x5 : PPW
Period captured in CC0, pulse width in CC1
0x6 : PWP
Period captured in CC1, pulse width in CC0
End of enumeration elements list.
TCINV : TC Inverted Event Input
bits : 4 - 4 (1 bit)
TCEI : TC Event Input
bits : 5 - 5 (1 bit)
OVFEO : Overflow/Underflow Event Output Enable
bits : 8 - 8 (1 bit)
MCEO0 : Match or Capture Channel 0 Event Output Enable
bits : 12 - 12 (1 bit)
MCEO1 : Match or Capture Channel 1 Event Output Enable
bits : 13 - 13 (1 bit)
8-bit Counter Mode - - Interrupt Enable Clear
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : Overflow Interrupt Enable
bits : 0 - 0 (1 bit)
ERR : Error Interrupt Enable
bits : 1 - 1 (1 bit)
SYNCRDY : Synchronization Ready Interrupt Enable
bits : 3 - 3 (1 bit)
MC0 : Match or Capture Channel 0 Interrupt Enable
bits : 4 - 4 (1 bit)
MC1 : Match or Capture Channel 1 Interrupt Enable
bits : 5 - 5 (1 bit)
16-bit Counter Mode - - Interrupt Enable Clear
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : Overflow Interrupt Enable
bits : 0 - 0 (1 bit)
ERR : Error Interrupt Enable
bits : 1 - 1 (1 bit)
SYNCRDY : Synchronization Ready Interrupt Enable
bits : 3 - 3 (1 bit)
MC0 : Match or Capture Channel 0 Interrupt Enable
bits : 4 - 4 (1 bit)
MC1 : Match or Capture Channel 1 Interrupt Enable
bits : 5 - 5 (1 bit)
32-bit Counter Mode - - Interrupt Enable Clear
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : Overflow Interrupt Enable
bits : 0 - 0 (1 bit)
ERR : Error Interrupt Enable
bits : 1 - 1 (1 bit)
SYNCRDY : Synchronization Ready Interrupt Enable
bits : 3 - 3 (1 bit)
MC0 : Match or Capture Channel 0 Interrupt Enable
bits : 4 - 4 (1 bit)
MC1 : Match or Capture Channel 1 Interrupt Enable
bits : 5 - 5 (1 bit)
Interrupt Enable Clear
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : Overflow Interrupt Enable
bits : 0 - 0 (1 bit)
ERR : Error Interrupt Enable
bits : 1 - 1 (1 bit)
SYNCRDY : Synchronization Ready Interrupt Enable
bits : 3 - 3 (1 bit)
MC0 : Match or Capture Channel 0 Interrupt Enable
bits : 4 - 4 (1 bit)
MC1 : Match or Capture Channel 1 Interrupt Enable
bits : 5 - 5 (1 bit)
8-bit Counter Mode - - Interrupt Enable Set
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : Overflow Interrupt Enable
bits : 0 - 0 (1 bit)
ERR : Error Interrupt Enable
bits : 1 - 1 (1 bit)
SYNCRDY : Synchronization Ready Interrupt Enable
bits : 3 - 3 (1 bit)
MC0 : Match or Capture Channel 0 Interrupt Enable
bits : 4 - 4 (1 bit)
MC1 : Match or Capture Channel 1 Interrupt Enable
bits : 5 - 5 (1 bit)
16-bit Counter Mode - - Interrupt Enable Set
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : Overflow Interrupt Enable
bits : 0 - 0 (1 bit)
ERR : Error Interrupt Enable
bits : 1 - 1 (1 bit)
SYNCRDY : Synchronization Ready Interrupt Enable
bits : 3 - 3 (1 bit)
MC0 : Match or Capture Channel 0 Interrupt Enable
bits : 4 - 4 (1 bit)
MC1 : Match or Capture Channel 1 Interrupt Enable
bits : 5 - 5 (1 bit)
32-bit Counter Mode - - Interrupt Enable Set
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : Overflow Interrupt Enable
bits : 0 - 0 (1 bit)
ERR : Error Interrupt Enable
bits : 1 - 1 (1 bit)
SYNCRDY : Synchronization Ready Interrupt Enable
bits : 3 - 3 (1 bit)
MC0 : Match or Capture Channel 0 Interrupt Enable
bits : 4 - 4 (1 bit)
MC1 : Match or Capture Channel 1 Interrupt Enable
bits : 5 - 5 (1 bit)
Interrupt Enable Set
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : Overflow Interrupt Enable
bits : 0 - 0 (1 bit)
ERR : Error Interrupt Enable
bits : 1 - 1 (1 bit)
SYNCRDY : Synchronization Ready Interrupt Enable
bits : 3 - 3 (1 bit)
MC0 : Match or Capture Channel 0 Interrupt Enable
bits : 4 - 4 (1 bit)
MC1 : Match or Capture Channel 1 Interrupt Enable
bits : 5 - 5 (1 bit)
8-bit Counter Mode - - Interrupt Flag Status and Clear
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : Overflow
bits : 0 - 0 (1 bit)
ERR : Error
bits : 1 - 1 (1 bit)
SYNCRDY : Synchronization Ready
bits : 3 - 3 (1 bit)
MC0 : Match or Capture Channel 0
bits : 4 - 4 (1 bit)
MC1 : Match or Capture Channel 1
bits : 5 - 5 (1 bit)
16-bit Counter Mode - - Interrupt Flag Status and Clear
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : Overflow
bits : 0 - 0 (1 bit)
ERR : Error
bits : 1 - 1 (1 bit)
SYNCRDY : Synchronization Ready
bits : 3 - 3 (1 bit)
MC0 : Match or Capture Channel 0
bits : 4 - 4 (1 bit)
MC1 : Match or Capture Channel 1
bits : 5 - 5 (1 bit)
32-bit Counter Mode - - Interrupt Flag Status and Clear
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : Overflow
bits : 0 - 0 (1 bit)
ERR : Error
bits : 1 - 1 (1 bit)
SYNCRDY : Synchronization Ready
bits : 3 - 3 (1 bit)
MC0 : Match or Capture Channel 0
bits : 4 - 4 (1 bit)
MC1 : Match or Capture Channel 1
bits : 5 - 5 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : Overflow
bits : 0 - 0 (1 bit)
ERR : Error
bits : 1 - 1 (1 bit)
SYNCRDY : Synchronization Ready
bits : 3 - 3 (1 bit)
MC0 : Match or Capture Channel 0
bits : 4 - 4 (1 bit)
MC1 : Match or Capture Channel 1
bits : 5 - 5 (1 bit)
8-bit Counter Mode - - Status
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STOP : Stop
bits : 3 - 3 (1 bit)
access : read-only
SLAVE : Slave
bits : 4 - 4 (1 bit)
access : read-only
SYNCBUSY : Synchronization Busy
bits : 7 - 7 (1 bit)
access : read-only
16-bit Counter Mode - - Status
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STOP : Stop
bits : 3 - 3 (1 bit)
access : read-only
SLAVE : Slave
bits : 4 - 4 (1 bit)
access : read-only
SYNCBUSY : Synchronization Busy
bits : 7 - 7 (1 bit)
access : read-only
32-bit Counter Mode - - Status
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STOP : Stop
bits : 3 - 3 (1 bit)
access : read-only
SLAVE : Slave
bits : 4 - 4 (1 bit)
access : read-only
SYNCBUSY : Synchronization Busy
bits : 7 - 7 (1 bit)
access : read-only
Status
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STOP : Stop
bits : 3 - 3 (1 bit)
access : read-only
SLAVE : Slave
bits : 4 - 4 (1 bit)
access : read-only
SYNCBUSY : Synchronization Busy
bits : 7 - 7 (1 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.