\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
CRC Control
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCM_CRCCTRL_TYPE : Operation Type
bits : 0 - 3 (4 bit)
Enumeration:
0x0 : CCM_CRCCTRL_TYPE_P8055
Polynomial 0x8005
0x1 : CCM_CRCCTRL_TYPE_P1021
Polynomial 0x1021
0x2 : CCM_CRCCTRL_TYPE_P4C11DB7
Polynomial 0x4C11DB7
0x3 : CCM_CRCCTRL_TYPE_P1EDC6F41
Polynomial 0x1EDC6F41
0x8 : CCM_CRCCTRL_TYPE_TCPCHKSUM
TCP checksum
End of enumeration elements list.
CCM_CRCCTRL_ENDIAN : Endian Control
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : CCM_CRCCTRL_ENDIAN_SBHW
Configuration unchanged. (B3, B2, B1, B0)
0x1 : CCM_CRCCTRL_ENDIAN_SHW
Bytes are swapped in half-words but half-words are not swapped (B2, B3, B0, B1)
0x2 : CCM_CRCCTRL_ENDIAN_SHWNB
Half-words are swapped but bytes are not swapped in half-word. (B1, B0, B3, B2)
0x3 : CCM_CRCCTRL_ENDIAN_SBSW
Bytes are swapped in half-words and half-words are swapped. (B0, B1, B2, B3)
End of enumeration elements list.
CCM_CRCCTRL_BR : Bit reverse enable
bits : 7 - 14 (8 bit)
CCM_CRCCTRL_OBR : Output Reverse Enable
bits : 8 - 16 (9 bit)
CCM_CRCCTRL_RESINV : Result Inverse Enable
bits : 9 - 18 (10 bit)
CCM_CRCCTRL_SIZE : Input Data Size
bits : 12 - 24 (13 bit)
CCM_CRCCTRL_INIT : CRC Initialization
bits : 13 - 27 (15 bit)
Enumeration:
0x0 : CCM_CRCCTRL_INIT_SEED
Use the CRCSEED register context as the starting value
0x2 : CCM_CRCCTRL_INIT_0
Initialize to all '0s'
0x3 : CCM_CRCCTRL_INIT_1
Initialize to all '1s'
End of enumeration elements list.
CRC Control
address_offset : 0x400 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCM_CRCCTRL_TYPE : Operation Type
bits : 0 - 3 (4 bit)
Enumeration:
0x0 : CCM_CRCCTRL_TYPE_P8055
Polynomial 0x8005
0x1 : CCM_CRCCTRL_TYPE_P1021
Polynomial 0x1021
0x2 : CCM_CRCCTRL_TYPE_P4C11DB7
Polynomial 0x4C11DB7
0x3 : CCM_CRCCTRL_TYPE_P1EDC6F41
Polynomial 0x1EDC6F41
0x8 : CCM_CRCCTRL_TYPE_TCPCHKSUM
TCP checksum
End of enumeration elements list.
CCM_CRCCTRL_ENDIAN : Endian Control
bits : 4 - 9 (6 bit)
Enumeration:
0x0 : CCM_CRCCTRL_ENDIAN_SBHW
Configuration unchanged. (B3, B2, B1, B0)
0x1 : CCM_CRCCTRL_ENDIAN_SHW
Bytes are swapped in half-words but half-words are not swapped (B2, B3, B0, B1)
0x2 : CCM_CRCCTRL_ENDIAN_SHWNB
Half-words are swapped but bytes are not swapped in half-word. (B1, B0, B3, B2)
0x3 : CCM_CRCCTRL_ENDIAN_SBSW
Bytes are swapped in half-words and half-words are swapped. (B0, B1, B2, B3)
End of enumeration elements list.
CCM_CRCCTRL_BR : Bit reverse enable
bits : 7 - 14 (8 bit)
CCM_CRCCTRL_OBR : Output Reverse Enable
bits : 8 - 16 (9 bit)
CCM_CRCCTRL_RESINV : Result Inverse Enable
bits : 9 - 18 (10 bit)
CCM_CRCCTRL_SIZE : Input Data Size
bits : 12 - 24 (13 bit)
CCM_CRCCTRL_INIT : CRC Initialization
bits : 13 - 27 (15 bit)
Enumeration:
0x0 : CCM_CRCCTRL_INIT_SEED
Use the CRCSEED register context as the starting value
0x2 : CCM_CRCCTRL_INIT_0
Initialize to all '0s'
0x3 : CCM_CRCCTRL_INIT_1
Initialize to all '1s'
End of enumeration elements list.
CRC SEED/Context
address_offset : 0x410 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCM_CRCSEED_SEED : SEED/Context Value
bits : 0 - 31 (32 bit)
CRC SEED/Context
address_offset : 0x410 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCM_CRCSEED_SEED : SEED/Context Value
bits : 0 - 31 (32 bit)
CRC Data Input
address_offset : 0x414 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCM_CRCDIN_DATAIN : Data Input
bits : 0 - 31 (32 bit)
CRC Data Input
address_offset : 0x414 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCM_CRCDIN_DATAIN : Data Input
bits : 0 - 31 (32 bit)
CRC Post Processing Result
address_offset : 0x418 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCM_CRCRSLTPP_RSLTPP : Post Processing Result
bits : 0 - 31 (32 bit)
CRC Post Processing Result
address_offset : 0x418 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCM_CRCRSLTPP_RSLTPP : Post Processing Result
bits : 0 - 31 (32 bit)
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