\n

TD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : reserved
protection : not protected

Registers

BCR

EN

CONF


BCR

Update Flag Setting Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCR BCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDSFT00 TDSFT01 TDSFT10 TDSFT11 PHSCHG

TDSFT00 : TDSFT00
bits : 0 - 0 (1 bit)
access : read-write

TDSFT01 : TDSFT01
bits : 1 - 1 (1 bit)
access : read-write

TDSFT10 : TDSFT10
bits : 2 - 2 (1 bit)
access : read-write

TDSFT11 : TDSFT11
bits : 3 - 3 (1 bit)
access : read-write

PHSCHG : PHSCHG
bits : 4 - 4 (1 bit)
access : read-write


EN

Timer Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDHALT TDEN0 TDEN1

TDHALT : TDHALT
bits : 5 - 5 (1 bit)
access : read-write

TDEN0 : TDEN0
bits : 6 - 6 (1 bit)
access : read-write

TDEN1 : TDEN1
bits : 7 - 7 (1 bit)
access : read-write


CONF

Timer Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONF CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRDMOD

TMRDMOD : TMRDMOD
bits : 0 - 2 (3 bit)
access : read-write



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