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TD1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x3C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x14 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x44 Bytes (0x0)
size : 0x90 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0xD4 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xE4 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x114 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x13C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

Registers

RG0

RG4

CP0

CP1

CP2

CP3

CP4

HSW0

HSW1

HSWB0

RG1

HSWB1

RG2

RG3

RUN

CR

MOD

DMA


RG0

Timer Register0 (Unit1)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG0 RG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDRG0

TDRG0 : TDRG0
bits : 0 - 15 (16 bit)
access : read-write


RG4

Timer Register4 (Unit1)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG4 RG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDMDRT TDRG4 DIR

TDMDRT : TDMDRT
bits : 0 - 3 (4 bit)
access : read-write

TDRG4 : TDRG4
bits : 4 - 19 (16 bit)
access : read-write

DIR : DIR
bits : 31 - 31 (1 bit)
access : read-write


CP0

Compare Register0 (Unit1)
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CP0 CP0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRG0

CPRG0 : CPRG0
bits : 0 - 15 (16 bit)
access : read-only


CP1

Compare Register1 (Unit1)
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CP1 CP1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRG1

CPRG1 : CPRG1
bits : 0 - 15 (16 bit)
access : read-only


CP2

Compare Register2 (Unit1)
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CP2 CP2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPMDRT CPRG2 DIR

CPMDRT : CPMDRT
bits : 0 - 3 (4 bit)
access : read-only

CPRG2 : CPRG2
bits : 4 - 19 (16 bit)
access : read-only

DIR : DIR
bits : 31 - 31 (1 bit)
access : read-only


CP3

Compare Register3 (Unit1)
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CP3 CP3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRG3

CPRG3 : CPRG3
bits : 0 - 15 (16 bit)
access : read-only


CP4

Compare Register4 (Unit1)
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CP4 CP4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPMDRT CPRG4 DIR

CPMDRT : CPMDRT
bits : 0 - 3 (4 bit)
access : read-only

CPRG4 : CPRG4
bits : 4 - 19 (16 bit)
access : read-only

DIR : DIR
bits : 31 - 31 (1 bit)
access : read-only


HSW0

H-SW Control Circuit Register (Unit1)
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSW0 HSW0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSWMD0 OUTV0

HSWMD0 : HSWMD0
bits : 0 - 1 (2 bit)
access : read-only

OUTV0 : OUTV0
bits : 2 - 2 (1 bit)
access : read-only


HSW1

H-SW Control Circuit Register (Unit1)
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSW1 HSW1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSWMD1 OUTV1

HSWMD1 : HSWMD1
bits : 0 - 1 (2 bit)
access : read-only

OUTV1 : OUTV1
bits : 2 - 2 (1 bit)
access : read-only


HSWB0

H-SW Control Circuit Register Buffer0 (Unit1)
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSWB0 HSWB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSWMD0 OUTV0

HSWMD0 : HSWMD0
bits : 0 - 1 (2 bit)
access : read-write

OUTV0 : OUTV0
bits : 2 - 2 (1 bit)
access : read-write


RG1

Timer Register1 (Unit1)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG1 RG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDRG1

TDRG1 : TDRG1
bits : 0 - 15 (16 bit)
access : read-write


HSWB1

H-SW Control Circuit Register Buffer1 (Unit1)
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSWB1 HSWB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSWMD1 OUTV1

HSWMD1 : HSWMD1
bits : 0 - 1 (2 bit)
access : read-write

OUTV1 : OUTV1
bits : 2 - 2 (1 bit)
access : read-write


RG2

Timer Register2 (Unit1)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG2 RG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDMDRT TDRG2 DIR

TDMDRT : TDMDRT
bits : 0 - 3 (4 bit)
access : read-write

TDRG2 : TDRG2
bits : 4 - 19 (16 bit)
access : read-write

DIR : DIR
bits : 31 - 31 (1 bit)
access : read-write


RG3

Timer Register3 (Unit1)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG3 RG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDRG3

TDRG3 : TDRG3
bits : 0 - 15 (16 bit)
access : read-write


RUN

Timer Run Register (Unit1)
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RUN RUN write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDRUN

TDRUN : TDRUN
bits : 0 - 0 (1 bit)
access : write-only


CR

Timer Control Register (Unit1)
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDISO TDRDE TDMDPT10 TDMDCY10 TDMDPT11 TDMDCY11

TDISO : TDISO
bits : 0 - 1 (2 bit)
access : read-write

TDRDE : TDRDE
bits : 2 - 2 (1 bit)
access : read-write

TDMDPT10 : TDMDPT10
bits : 4 - 4 (1 bit)
access : read-write

TDMDCY10 : TDMDCY10
bits : 5 - 7 (3 bit)
access : read-write

TDMDPT11 : TDMDPT11
bits : 8 - 8 (1 bit)
access : read-write

TDMDCY11 : TDMDCY11
bits : 9 - 11 (3 bit)
access : read-write


MOD

Timer Mode Register (Unit1)
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDCLK TDCLE TDIV0 TDIV1

TDCLK : TDCLK
bits : 0 - 3 (4 bit)
access : read-write

TDCLE : TDCLE
bits : 4 - 4 (1 bit)
access : read-write

TDIV0 : TDIV0
bits : 6 - 6 (1 bit)
access : read-write

TDIV1 : TDIV1
bits : 7 - 7 (1 bit)
access : read-write


DMA

DMA Request Enable Register (Unit1)
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAEN

DMAEN : DMAEN
bits : 0 - 0 (1 bit)
access : read-write



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