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CG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x50 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x24 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x34 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x58 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x5C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PROTECT

PLL0SEL

WUPHCR

OSCCR

FSYSENA

FSYSENB

SPCLKEN

EXTENDO0

SYSCR

STBYCR


PROTECT

Protect Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROTECT PROTECT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROTECT

PROTECT : PROTECT
bits : 0 - 7 (8 bit)
access : read-write


PLL0SEL

PLL select register for fsys
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLL0SEL PLL0SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL0ON PPL0SEL PLL0ST PLL0SET

PLL0ON : PLL0ON
bits : 0 - 0 (1 bit)
access : read-write

PPL0SEL : PPL0SEL
bits : 1 - 1 (1 bit)
access : read-write

PLL0ST : PLL0ST
bits : 2 - 2 (1 bit)
access : read-write

PLL0SET : PLL0SET
bits : 8 - 31 (24 bit)
access : read-write


WUPHCR

Warmup register for HOSC
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WUPHCR WUPHCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUON WUEF WUCLK WUPT

WUON : WUON
bits : 0 - 0 (1 bit)
access : write-only

WUEF : WUEF
bits : 1 - 1 (1 bit)
access : read-only

WUCLK : WUCLK
bits : 8 - 8 (1 bit)
access : read-write

WUPT : WUPT
bits : 20 - 31 (12 bit)
access : read-write


OSCCR

Oscillation Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSCCR OSCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSCEN EOSEN OSCSEL OSCF

IOSCEN : IOSCEN
bits : 0 - 0 (1 bit)
access : read-write

EOSEN : EOSEN
bits : 1 - 2 (2 bit)
access : read-write

OSCSEL : OSCSEL
bits : 8 - 8 (1 bit)
access : read-write

OSCF : OSCF
bits : 9 - 9 (1 bit)
access : read-only


FSYSENA

output control register A for fsys clock
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FSYSENA FSYSENA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPENA07 IPENA08 IPENA09 IPENA10 IPENA11 IPENA12 IPENA13 IPENA14 IPENA15 IPENA16 IPENA17 IPENA18

IPENA07 : IPENA07
bits : 7 - 7 (1 bit)
access : read-write

IPENA08 : IPENA08
bits : 8 - 8 (1 bit)
access : read-write

IPENA09 : IPENA09
bits : 9 - 9 (1 bit)
access : read-write

IPENA10 : IPENA10
bits : 10 - 10 (1 bit)
access : read-write

IPENA11 : IPENA11
bits : 11 - 11 (1 bit)
access : read-write

IPENA12 : IPENA12
bits : 12 - 12 (1 bit)
access : read-write

IPENA13 : IPENA13
bits : 13 - 13 (1 bit)
access : read-write

IPENA14 : IPENA14
bits : 14 - 14 (1 bit)
access : read-write

IPENA15 : IPENA15
bits : 15 - 15 (1 bit)
access : read-write

IPENA16 : IPENA16
bits : 16 - 16 (1 bit)
access : read-write

IPENA17 : IPENA17
bits : 17 - 17 (1 bit)
access : read-write

IPENA18 : IPENA18
bits : 18 - 18 (1 bit)
access : read-write


FSYSENB

output control register B for fsys clock
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FSYSENB FSYSENB write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPENB28 IPENB29 IPENB30 IPENB31

IPENB28 : IPENB28
bits : 28 - 28 (1 bit)
access : read-write

IPENB29 : IPENB29
bits : 29 - 29 (1 bit)
access : read-write

IPENB30 : IPENB30
bits : 30 - 30 (1 bit)
access : read-write

IPENB31 : IPENB31
bits : 31 - 31 (1 bit)
access : read-write


SPCLKEN

Output control register for ADC and TRACE CLOCK
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPCLKEN SPCLKEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCKEN

ADCKEN : ADCKEN
bits : 16 - 16 (1 bit)
access : read-write


EXTENDO0

Optional Function setting Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTENDO0 EXTENDO0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBENA USBSEL EHCLKSEL DCLKEN

USBENA : USBENA
bits : 0 - 0 (1 bit)
access : read-write

USBSEL : USBSEL
bits : 1 - 1 (1 bit)
access : read-write

EHCLKSEL : EHCLKSEL
bits : 4 - 4 (1 bit)
access : read-write

DCLKEN : DCLKEN
bits : 5 - 5 (1 bit)
access : read-write


SYSCR

System clock control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCR SYSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEAR PRCK GEARST PRCKST

GEAR : GEAR
bits : 0 - 2 (3 bit)
access : read-write

PRCK : PRCK
bits : 8 - 10 (3 bit)
access : read-write

GEARST : GEARST
bits : 16 - 18 (3 bit)
access : read-only

PRCKST : PRCKST
bits : 24 - 27 (4 bit)
access : read-only


STBYCR

Standby Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STBYCR STBYCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STBY

STBY : STBY
bits : 0 - 1 (2 bit)
access : read-write



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