\n
address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected
PMD Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMEN : PWMEN
bits : 0 - 0 (1 bit)
access : read-write
PMD PWM Counter Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MDCNT : MDCNT
bits : 0 - 15 (16 bit)
access : read-only
PMD PWM Period Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDPRD : MDPRD
bits : 0 - 15 (16 bit)
access : read-write
PMD PWM Compare U Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPU : CMPU
bits : 0 - 15 (16 bit)
access : read-write
PMD PWM Compare V Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPV : CMPV
bits : 0 - 15 (16 bit)
access : read-write
PMD PWM Compare W Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPW : CMPW
bits : 0 - 15 (16 bit)
access : read-write
PMD Conduction Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UOC : UOC
bits : 0 - 1 (2 bit)
access : read-write
VOC : VOC
bits : 2 - 3 (2 bit)
access : read-write
WOC : WOC
bits : 4 - 5 (2 bit)
access : read-write
UPWM : UPWM
bits : 8 - 8 (1 bit)
access : read-write
VPWM : VPWM
bits : 9 - 9 (1 bit)
access : read-write
WPWM : WPWM
bits : 10 - 10 (1 bit)
access : read-write
PMD Output Setting Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSYNCS : PSYNCS
bits : 0 - 1 (2 bit)
access : read-write
POLL : POLL
bits : 2 - 2 (1 bit)
access : read-write
POLH : POLH
bits : 3 - 3 (1 bit)
access : read-write
SYNCS : SYNCS
bits : 8 - 9 (2 bit)
access : read-write
PMD EMG Release Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EMGREL : EMGREL
bits : 0 - 7 (8 bit)
access : write-only
PMD EMG Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMGEN : EMGEN
bits : 0 - 0 (1 bit)
access : read-write
EMGRS : EMGRS
bits : 1 - 1 (1 bit)
access : write-only
EMGMD : EMGMD
bits : 3 - 4 (2 bit)
access : read-write
INHEN : INHEN
bits : 5 - 5 (1 bit)
access : read-write
EMGCNT : EMGCNT
bits : 8 - 11 (4 bit)
access : read-write
PMD EMG Status Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EMGST : EMGST
bits : 0 - 0 (1 bit)
access : read-only
EMGI : EMGI
bits : 1 - 1 (1 bit)
access : read-only
PMD OVV Control Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVVEN : OVVEN
bits : 0 - 0 (1 bit)
access : read-write
OVVRS : OVVRS
bits : 1 - 1 (1 bit)
access : read-write
OVVISEL : OVVISEL
bits : 2 - 2 (1 bit)
access : read-write
OVVMD : OVVMD
bits : 3 - 4 (2 bit)
access : read-write
ADIN0EN : ADIN0EN
bits : 5 - 5 (1 bit)
access : read-write
ADIN1EN : ADIN1EN
bits : 6 - 6 (1 bit)
access : read-write
OVVCNT : OVVCNT
bits : 8 - 11 (4 bit)
access : read-write
PMD Port Output Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORTMD : PORTMD
bits : 0 - 1 (2 bit)
access : read-write
PMD OVV Status Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OVVST : OVVST
bits : 0 - 0 (1 bit)
access : read-only
OVVI : OVVI
bits : 1 - 1 (1 bit)
access : read-only
PMD Dead Time Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTR : DTR
bits : 0 - 7 (8 bit)
access : read-write
PMD Trigger Compare Register 0
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGCMP0 : TRGCMP0
bits : 0 - 15 (16 bit)
access : read-write
PMD Trigger Compare Register 1
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGCMP1 : TRGCMP1
bits : 0 - 15 (16 bit)
access : read-write
PMD Trigger Compare Register 2
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGCMP2 : TRGCMP2
bits : 0 - 15 (16 bit)
access : read-write
PMD Trigger Compare Register 3
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGCMP3 : TRGCMP3
bits : 0 - 15 (16 bit)
access : read-write
PMD Trigger Control Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRG0MD : TRG0MD
bits : 0 - 2 (3 bit)
access : read-write
TRG0BE : TRG0BE
bits : 3 - 3 (1 bit)
access : read-write
TRG1MD : TRG1MD
bits : 4 - 6 (3 bit)
access : read-write
TRG1BE : TRG1BE
bits : 7 - 7 (1 bit)
access : read-write
TRG2MD : TRG2MD
bits : 8 - 10 (3 bit)
access : read-write
TRG2BE : TRG2BE
bits : 11 - 11 (1 bit)
access : read-write
TRG3MD : TRG3MD
bits : 12 - 14 (3 bit)
access : read-write
TRG3BE : TRG3BE
bits : 15 - 15 (1 bit)
access : read-write
PMD Trigger Output Mode Setting Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMGTGE : EMGTGE
bits : 0 - 0 (1 bit)
access : read-write
TRGOUT : TRGOUT
bits : 1 - 1 (1 bit)
access : read-write
PMD Trigger Output Select Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL : TRGSEL
bits : 0 - 2 (3 bit)
access : read-write
PMD Trigger Update Timing Setting Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSYNCS : TSYNCS
bits : 0 - 1 (2 bit)
access : read-write
PMD Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMMD : PWMMD
bits : 0 - 0 (1 bit)
access : read-write
INTPRD : INTPRD
bits : 1 - 2 (2 bit)
access : read-write
PINT : PINT
bits : 3 - 3 (1 bit)
access : read-write
DTYMD : DTYMD
bits : 4 - 4 (1 bit)
access : read-write
SYNTMD : SYNTMD
bits : 5 - 5 (1 bit)
access : read-write
PWMCK : PWMCK
bits : 6 - 6 (1 bit)
access : read-write
DTCREN : DTCREN
bits : 7 - 7 (1 bit)
access : read-write
DSYNCS : DSYNCS
bits : 8 - 9 (2 bit)
access : read-write
UPWMES : UPWMES
bits : 10 - 11 (2 bit)
access : read-write
VPWMES : VPWMES
bits : 12 - 13 (2 bit)
access : read-write
WPWMES : WPWMES
bits : 14 - 15 (2 bit)
access : read-write
PMD PWM Counter Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UPDWN : UPDWN
bits : 0 - 0 (1 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.