\n

PL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x38 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection : not protected

address_offset : 0x1C Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : reserved
protection : not protected

Registers

DATA

FR3

FR4

FR5

OD

PUP

PDN

IE

CR

FR1

FR2


DATA

PL Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0 PL1 PL2 PL3 PL4

PL0 : PL0
bits : 0 - 0 (1 bit)
access : read-write

PL1 : PL1
bits : 1 - 1 (1 bit)
access : read-write

PL2 : PL2
bits : 2 - 2 (1 bit)
access : read-write

PL3 : PL3
bits : 3 - 3 (1 bit)
access : read-write

PL4 : PL4
bits : 4 - 4 (1 bit)
access : read-write


FR3

PL Function Register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR3 FR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0F3 PL1F3 PL2F3 PL3F3 PL4F3

PL0F3 : PL0F3
bits : 0 - 0 (1 bit)
access : read-write

PL1F3 : PL1F3
bits : 1 - 1 (1 bit)
access : read-write

PL2F3 : PL2F3
bits : 2 - 2 (1 bit)
access : read-write

PL3F3 : PL3F3
bits : 3 - 3 (1 bit)
access : read-write

PL4F3 : PL4F3
bits : 4 - 4 (1 bit)
access : read-write


FR4

PL Function Register 4
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR4 FR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FR5

PL Function Register 4
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR5 FR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0F5 PL1F5 PL2F5 PL3F5 PL4F5

PL0F5 : PL0F5
bits : 0 - 0 (1 bit)
access : read-write

PL1F5 : PL1F5
bits : 1 - 1 (1 bit)
access : read-write

PL2F5 : PL2F5
bits : 2 - 2 (1 bit)
access : read-write

PL3F5 : PL3F5
bits : 3 - 3 (1 bit)
access : read-write

PL4F5 : PL4F5
bits : 4 - 4 (1 bit)
access : read-write


OD

PL Open Drain Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OD OD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0OD PL1OD PL2OD PL3OD PL4OD

PL0OD : PL0OD
bits : 0 - 0 (1 bit)
access : read-write

PL1OD : PL1OD
bits : 1 - 1 (1 bit)
access : read-write

PL2OD : PL2OD
bits : 2 - 2 (1 bit)
access : read-write

PL3OD : PL3OD
bits : 3 - 3 (1 bit)
access : read-write

PL4OD : PL4OD
bits : 4 - 4 (1 bit)
access : read-write


PUP

PL Pull-up Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUP PUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0UP PL1UP PL2UP PL3UP PL4UP

PL0UP : PL0UP
bits : 0 - 0 (1 bit)
access : read-write

PL1UP : PL1UP
bits : 1 - 1 (1 bit)
access : read-write

PL2UP : PL2UP
bits : 2 - 2 (1 bit)
access : read-write

PL3UP : PL3UP
bits : 3 - 3 (1 bit)
access : read-write

PL4UP : PL4UP
bits : 4 - 4 (1 bit)
access : read-write


PDN

PL Pull-Down Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDN PDN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0DN PL1DN PL2DN PL3DN PL4DN

PL0DN : PL0DN
bits : 0 - 0 (1 bit)
access : read-write

PL1DN : PL1DN
bits : 1 - 1 (1 bit)
access : read-write

PL2DN : PL2DN
bits : 2 - 2 (1 bit)
access : read-write

PL3DN : PL3DN
bits : 3 - 3 (1 bit)
access : read-write

PL4DN : PL4DN
bits : 4 - 4 (1 bit)
access : read-write


IE

PL Input Enable Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0IE PL1IE PL2IE PL3IE PL4IE

PL0IE : PL0IE
bits : 0 - 0 (1 bit)
access : read-write

PL1IE : PL1IE
bits : 1 - 1 (1 bit)
access : read-write

PL2IE : PL2IE
bits : 2 - 2 (1 bit)
access : read-write

PL3IE : PL3IE
bits : 3 - 3 (1 bit)
access : read-write

PL4IE : PL4IE
bits : 4 - 4 (1 bit)
access : read-write


CR

PL Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0C PL1C PL2C PL3C PL4C

PL0C : PL0C
bits : 0 - 0 (1 bit)
access : read-write

PL1C : PL1C
bits : 1 - 1 (1 bit)
access : read-write

PL2C : PL2C
bits : 2 - 2 (1 bit)
access : read-write

PL3C : PL3C
bits : 3 - 3 (1 bit)
access : read-write

PL4C : PL4C
bits : 4 - 4 (1 bit)
access : read-write


FR1

PL Function Register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR1 FR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0F1 PL1F1 PL2F1 PL3F1

PL0F1 : PL0F1
bits : 0 - 0 (1 bit)
access : read-write

PL1F1 : PL1F1
bits : 1 - 1 (1 bit)
access : read-write

PL2F1 : PL2F1
bits : 2 - 2 (1 bit)
access : read-write

PL3F1 : PL3F1
bits : 3 - 3 (1 bit)
access : read-write


FR2

PL Function Register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FR2 FR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL0F2 PL1F2 PL2F2 PL3F2

PL0F2 : PL0F2
bits : 0 - 0 (1 bit)
access : read-write

PL1F2 : PL1F2
bits : 1 - 1 (1 bit)
access : read-write

PL2F2 : PL2F2
bits : 2 - 2 (1 bit)
access : read-write

PL3F2 : PL3F2
bits : 3 - 3 (1 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.