\n

DSU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

STATUSA

END

DID

MEMTYPE

PID4

PID0

PID1

PID2

PID3

CID0

CID1

CID2

CID3

STATUSB

DCC0

ENTRY0

ENTRY1

DCC1

ADDR

LENGTH

DATA


CTRL

Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRST CRC MBIST CE

SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only

CRC : 32-bit Cyclic Redundancy Check
bits : 2 - 2 (1 bit)
access : write-only

MBIST : Memory Built-In Self-Test
bits : 3 - 3 (1 bit)
access : write-only

CE : Chip Erase
bits : 4 - 4 (1 bit)
access : write-only


STATUSA

Status A
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUSA STATUSA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DONE CRSTEXT BERR FAIL PERR

DONE : Done
bits : 0 - 0 (1 bit)

CRSTEXT : CPU Reset Phase Extension
bits : 1 - 1 (1 bit)

BERR : Bus Error
bits : 2 - 2 (1 bit)

FAIL : Failure
bits : 3 - 3 (1 bit)

PERR : Protection Error
bits : 4 - 4 (1 bit)


END

Coresight ROM Table End
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

END END read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 END

END : End Marker
bits : 0 - 31 (32 bit)


DID

Device Identification
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DID DID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEVSEL REVISION DIE SERIES FAMILY PROCESSOR

DEVSEL : Device Select
bits : 0 - 7 (8 bit)
access : read-only

REVISION : Revision
bits : 8 - 11 (4 bit)
access : read-only

DIE : Die Identification
bits : 12 - 15 (4 bit)
access : read-only

SERIES : Product Series
bits : 16 - 21 (6 bit)
access : read-only

FAMILY : Product Family
bits : 23 - 27 (5 bit)
access : read-only

PROCESSOR : Processor
bits : 28 - 31 (4 bit)
access : read-only


MEMTYPE

Coresight ROM Table Memory Type
address_offset : 0x1FCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MEMTYPE MEMTYPE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMEMP

SMEMP : System Memory Present
bits : 0 - 0 (1 bit)


PID4

Peripheral Identification 4
address_offset : 0x1FD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID4 PID4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEPCC FKBC

JEPCC : JEP-106 Continuation Code
bits : 0 - 3 (4 bit)

FKBC : 4KB Count
bits : 4 - 7 (4 bit)
access : read-only


PID0

Peripheral Identification 0
address_offset : 0x1FE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID0 PID0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARTNBL

PARTNBL : Part Number Low
bits : 0 - 7 (8 bit)


PID1

Peripheral Identification 1
address_offset : 0x1FE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID1 PID1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARTNBH JEPIDCL

PARTNBH : Part Number High
bits : 0 - 3 (4 bit)

JEPIDCL : Low part of the JEP-106 Identity Code
bits : 4 - 7 (4 bit)
access : read-only


PID2

Peripheral Identification 2
address_offset : 0x1FE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID2 PID2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEPIDCH JEPU REVISION

JEPIDCH : JEP-106 Identity Code High
bits : 0 - 2 (3 bit)

JEPU : JEP-106 Identity Code is used
bits : 3 - 3 (1 bit)
access : read-only

REVISION : Revision Number
bits : 4 - 7 (4 bit)
access : read-only


PID3

Peripheral Identification 3
address_offset : 0x1FEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID3 PID3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CUSMOD REVAND

CUSMOD : ARM CUSMOD
bits : 0 - 3 (4 bit)

REVAND : Revision Number
bits : 4 - 7 (4 bit)
access : read-only


CID0

Component Identification 0
address_offset : 0x1FF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CID0 CID0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLEB0

PREAMBLEB0 : Preamble Byte 0
bits : 0 - 7 (8 bit)
access : read-only


CID1

Component Identification 1
address_offset : 0x1FF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CID1 CID1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLE CCLASS

PREAMBLE : Preamble
bits : 0 - 3 (4 bit)
access : read-only

CCLASS : Component Class
bits : 4 - 7 (4 bit)
access : read-only


CID2

Component Identification 2
address_offset : 0x1FF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CID2 CID2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLEB2

PREAMBLEB2 : Preamble Byte 2
bits : 0 - 7 (8 bit)
access : read-only


CID3

Component Identification 3
address_offset : 0x1FFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CID3 CID3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLEB3

PREAMBLEB3 : Preamble Byte 3
bits : 0 - 7 (8 bit)


STATUSB

Status B
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUSB STATUSB read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PROT DBGPRES DCCD0 DCCD1 HPE

PROT : Protected
bits : 0 - 0 (1 bit)

DBGPRES : Debugger Present
bits : 1 - 1 (1 bit)

DCCD0 : Debug Communication Channel 0 Dirty
bits : 2 - 2 (1 bit)

DCCD1 : Debug Communication Channel 1 Dirty
bits : 3 - 3 (1 bit)

HPE : Hot-Plugging Enable
bits : 4 - 4 (1 bit)


DCC0

Debug Communication Channel n
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCC0 DCC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data
bits : 0 - 31 (32 bit)


ENTRY0

Coresight ROM Table Entry n
address_offset : 0x2000 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENTRY0 ENTRY0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPRES FMT ADDOFF

EPRES : Entry Present
bits : 0 - 0 (1 bit)

FMT : Format
bits : 1 - 1 (1 bit)
access : read-only

ADDOFF : Address Offset
bits : 12 - 31 (20 bit)
access : read-only


ENTRY1

Coresight ROM Table Entry n
address_offset : 0x3004 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENTRY1 ENTRY1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPRES FMT ADDOFF

EPRES : Entry Present
bits : 0 - 0 (1 bit)

FMT : Format
bits : 1 - 1 (1 bit)
access : read-only

ADDOFF : Address Offset
bits : 12 - 31 (20 bit)
access : read-only


DCC1

Debug Communication Channel n
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCC1 DCC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data
bits : 0 - 31 (32 bit)


ADDR

Address
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Address
bits : 2 - 31 (30 bit)


LENGTH

Length
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LENGTH LENGTH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH

LENGTH : Length
bits : 2 - 31 (30 bit)


DATA

Data
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data
bits : 0 - 31 (32 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.