\n
address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
SSP Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSS : DSS
bits : 0 - 3 (4 bit)
access : read-write
FRF : FRF
bits : 4 - 5 (2 bit)
access : read-write
SPO : SPO
bits : 6 - 6 (1 bit)
access : read-write
SPH : SPH
bits : 7 - 7 (1 bit)
access : read-write
SCR : SCR
bits : 8 - 15 (8 bit)
access : read-write
SSP Clock Prescaler Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPSDVSR : CPSDVSR
bits : 0 - 7 (8 bit)
access : read-write
SSP Interrupt Mask Set and Clear Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RORIM : RORIM
bits : 0 - 0 (1 bit)
access : read-write
RTIM : RTIM
bits : 1 - 1 (1 bit)
access : read-write
RXIM : RXIM
bits : 2 - 2 (1 bit)
access : read-write
TXIM : TXIM
bits : 3 - 3 (1 bit)
access : read-write
SSP Raw Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RORRIS : RORRIS
bits : 0 - 0 (1 bit)
access : read-only
RTRIS : RTRIS
bits : 1 - 1 (1 bit)
access : read-only
RXRIS : RXRIS
bits : 2 - 2 (1 bit)
access : read-only
TXRIS : TXRIS
bits : 3 - 3 (1 bit)
access : read-only
SSP Masked Interrupt Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RORMIS : RORMIS
bits : 0 - 0 (1 bit)
access : read-only
RTMIS : RTMIS
bits : 1 - 1 (1 bit)
access : read-only
RXMIS : RXMIS
bits : 2 - 2 (1 bit)
access : read-only
TXMIS : TXMIS
bits : 3 - 3 (1 bit)
access : read-only
SSP Interrupt Clear Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RORIC : RORIC
bits : 0 - 0 (1 bit)
access : write-only
RTIC : RTIC
bits : 1 - 1 (1 bit)
access : write-only
SSP Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LBM : LBM
bits : 0 - 0 (1 bit)
access : read-write
SSE : SSE
bits : 1 - 1 (1 bit)
access : read-write
MS : MS
bits : 2 - 2 (1 bit)
access : read-write
SOD : SOD
bits : 3 - 3 (1 bit)
access : read-write
SSP Data Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : DATA
bits : 0 - 15 (16 bit)
access : read-write
SSP Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TFE : TFE
bits : 0 - 0 (1 bit)
access : read-only
TNF : TNF
bits : 1 - 1 (1 bit)
access : read-only
RNE : RNE
bits : 2 - 2 (1 bit)
access : read-only
RFF : RFF
bits : 3 - 3 (1 bit)
access : read-only
BSY : BSY
bits : 4 - 4 (1 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.